X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=a5c05b832d7b746734af825a81e3a5bb03f6b4bd;hb=536ef282dbc04bbd6033aaab60801981d0eb5dd7;hp=e0c62739fb21a4aa5a2dcd768705a04ab5d9c800;hpb=a8e4a954b36da58bce5413b569532ef54b87abcd;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index e0c62739f..a5c05b832 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -27,8 +27,8 @@ #include "config.h" #endif -#include -#include +#include "lc_opts.h" +#include "lc_opts_enum.h" #include "pseudo_irg.h" #include "irgwalk.h" @@ -36,10 +36,13 @@ #include "irprintf.h" #include "ircons.h" #include "irgmod.h" +#include "irgopt.h" +#include "iroptimize.h" #include "lowering.h" #include "bitset.h" #include "debug.h" +#include "irtools.h" #include "../bearch_t.h" /* the general register allocator interface */ #include "../benode_t.h" @@ -85,36 +88,30 @@ static set *cur_reg_set = NULL; */ static const arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node, - int pos) { + int pos) +{ long node_pos = pos == -1 ? 0 : pos; ir_mode *mode = get_irn_mode(node); - FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); + (void) self; - if (is_Block(node) || mode == mode_X || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node)); + if (is_Block(node) || mode == mode_X) { return arch_no_register_req; } if (mode == mode_T && pos < 0) { - DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node)); return arch_no_register_req; } - DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node)); - if (is_Proj(node)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ - if (pos == -1) { - node_pos = arm_translate_proj_pos(node); - } - else { - node_pos = pos; - } + if(mode == mode_M) + return arch_no_register_req; - node = skip_Proj_const(node); + if(pos >= 0) { + return arch_no_register_req; + } - DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos)); + node_pos = (pos == -1) ? get_Proj_proj(node) : pos; + node = skip_Proj_const(node); } /* get requirements for our own nodes */ @@ -126,27 +123,26 @@ arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node, req = get_arm_out_req(node, node_pos); } - DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos)); return req; } - /* unknown should be tranformed by now */ + /* unknown should be transformed by now */ assert(!is_Unknown(node)); - DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node)); - return arch_no_register_req; } -static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { +static void arm_set_irn_reg(const void *self, ir_node *irn, + const arch_register_t *reg) +{ int pos = 0; + (void) self; - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return; - } + if (get_irn_mode(irn) == mode_X) { + return; + } - pos = arm_translate_proj_pos(irn); + if (is_Proj(irn)) { + pos = get_Proj_proj(irn); irn = skip_Proj(irn); } @@ -162,9 +158,12 @@ static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_ } } -static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) { +static const arch_register_t *arm_get_irn_reg(const void *self, + const ir_node *irn) +{ int pos = 0; const arch_register_t *reg = NULL; + (void) self; if (is_Proj(irn)) { @@ -172,7 +171,7 @@ static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *i return NULL; } - pos = arm_translate_proj_pos(irn); + pos = get_Proj_proj(irn); irn = skip_Proj_const(irn); } @@ -188,7 +187,9 @@ static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *i return reg; } -static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) { +static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) +{ + (void) self; irn = skip_Proj_const(irn); if (is_cfop(irn)) { @@ -201,25 +202,43 @@ static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) { return 0; } -static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) { - irn = skip_Proj_const(irn); +static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) +{ + arch_irn_flags_t flags = arch_irn_flags_none; + (void) self; - if (is_arm_irn(irn)) { - return get_arm_flags(irn); - } - else if (is_Unknown(irn)) { + if(is_Unknown(irn)) { return arch_irn_flags_ignore; } - return 0; + if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) { + ir_node *pred = get_Proj_pred(irn); + if (is_arm_irn(pred)) { + flags = get_arm_out_flags(pred, get_Proj_proj(irn)); + } + irn = pred; + } + + if (is_arm_irn(irn)) { + flags |= get_arm_flags(irn); + } + + return flags; } -static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) { +static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) +{ + (void) self; + (void) irn; /* TODO: return the entity assigned to the frame */ return NULL; } -static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { +static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) +{ + (void) self; + (void) irn; + (void) ent; /* TODO: set the entity assigned to the frame */ } @@ -227,11 +246,18 @@ static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ -static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) { +static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) +{ + (void) self; + (void) irn; + (void) bias; /* TODO: correct offset if irn accesses the stack */ } -static int arm_get_sp_bias(const void *self, const ir_node *irn) { +static int arm_get_sp_bias(const void *self, const ir_node *irn) +{ + (void) self; + (void) irn; return 0; } @@ -278,17 +304,28 @@ arm_irn_ops_t arm_irn_ops = { static void arm_prepare_graph(void *self) { arm_code_gen_t *cg = self; - arm_register_transformers(); - irg_walk_blkwise_graph(cg->irg, NULL, arm_move_consts, cg); - irg_walk_blkwise_graph(cg->irg, NULL, arm_transform_node, cg); -} + /* transform nodes into assembler instructions */ + arm_transform_graph(cg); + + /* do local optimizations (mainly CSE) */ + local_optimize_graph(cg->irg); + + if (cg->dump) + be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched); + /* do code placement, to optimize the position of constants */ + place_code(cg->irg); + if (cg->dump) + be_dump(cg->irg, "-place", dump_ir_block_graph_sched); +} /** * Called immediately before emit phase. */ -static void arm_finish_irg(void *self) { +static void arm_finish_irg(void *self) +{ + (void) self; /* TODO: - fix offsets for nodes accessing stack - ... */ @@ -298,11 +335,15 @@ static void arm_finish_irg(void *self) { /** * These are some hooks which must be filled but are probably not needed. */ -static void arm_before_sched(void *self) { +static void arm_before_sched(void *self) +{ + (void) self; /* Some stuff you need to do after scheduling but before register allocation */ } -static void arm_before_ra(void *self) { +static void arm_before_ra(void *self) +{ + (void) self; /* Some stuff you need to do immediately after register allocation */ } @@ -310,7 +351,8 @@ static void arm_before_ra(void *self) { * We transform Spill and Reload here. This needs to be done before * stack biasing otherwise we would miss the corrected offset for these nodes. */ -static void arm_after_ra(void *self) { +static void arm_after_ra(void *self) +{ arm_code_gen_t *cg = self; be_coalesce_spillslots(cg->birg); } @@ -385,7 +427,10 @@ static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem, * 1.) A constant: simply move * 2.) A load: simply load */ -static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) { +static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) +{ + (void) bl; + if (is_Const(arg)) { tarval *tv = get_Const_tarval(arg); unsigned v; @@ -414,7 +459,7 @@ static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) { static void handle_calls(ir_node *call, void *env) { arm_code_gen_t *cg = env; - int i, j, n, size, idx, flag, n_param, n_res; + int i, j, n, size, idx, flag, n_param, n_res, first_variadic; ir_type *mtp, *new_mtd, *new_tp[5]; ir_node *new_in[5], **in; ir_node *bl; @@ -493,7 +538,9 @@ static void handle_calls(ir_node *call, void *env) set_method_res_type(new_mtd, i, get_method_res_type(mtp, i)); set_method_calling_convention(new_mtd, get_method_calling_convention(mtp)); - set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp)); + first_variadic = get_method_first_variadic_param_index(mtp); + if (first_variadic >= 0) + set_method_first_variadic_param_index(new_mtd, first_variadic); if (is_lowered_type(mtp)) { mtp = get_associated_type(mtp); @@ -525,6 +572,7 @@ static void arm_before_abi(void *self) { irg_walk_graph(cg->irg, NULL, handle_calls, cg); } +/* forward */ static void *arm_cg_init(be_irg_t *birg); static const arch_code_generator_if_t arm_code_gen_if = { @@ -553,14 +601,17 @@ static void *arm_cg_init(be_irg_t *birg) { } cg = xmalloc(sizeof(*cg)); - cg->impl = &arm_code_gen_if; - cg->irg = birg->irg; - cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); - cg->arch_env = birg->main_env->arch_env; - cg->isa = isa; - cg->birg = birg; - cg->int_tp = int_tp; - cg->have_fp = 0; + cg->impl = &arm_code_gen_if; + cg->irg = birg->irg; + cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); + cg->arch_env = birg->main_env->arch_env; + cg->isa = isa; + cg->birg = birg; + cg->int_tp = int_tp; + cg->have_fp_insn = 0; + cg->unknown_gp = NULL; + cg->unknown_fpa = NULL; + cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg"); @@ -585,6 +636,8 @@ static void arm_handle_intrinsics(void) { i_record records[8]; int n_records = 0; + runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod; + #define ID(x) new_id_from_chars(x, sizeof(x)-1) int_tp = new_type_primitive(ID("int"), mode_Is); @@ -592,7 +645,6 @@ static void arm_handle_intrinsics(void) { /* ARM has neither a signed div instruction ... */ { - runtime_rt rt_Div; i_instr_record *map_Div = &records[n_records++].i_instr; tp = new_type_method(ID("rt_iDiv"), 2, 1); @@ -600,25 +652,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); - rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp); - rt_Div.mode = mode_T; - rt_Div.res_mode = mode_Is; - rt_Div.mem_proj_nr = pn_Div_M; - rt_Div.regular_proj_nr = pn_Div_X_regular; - rt_Div.exc_proj_nr = pn_Div_X_except; - rt_Div.exc_mem_proj_nr = pn_Div_M; - rt_Div.res_proj_nr = pn_Div_res; + rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp); + set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3")); + rt_iDiv.mode = mode_T; + rt_iDiv.res_mode = mode_Is; + rt_iDiv.mem_proj_nr = pn_Div_M; + rt_iDiv.regular_proj_nr = pn_Div_X_regular; + rt_iDiv.exc_proj_nr = pn_Div_X_except; + rt_iDiv.exc_mem_proj_nr = pn_Div_M; + rt_iDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_Div.ent, visibility_external_allocated); + set_entity_visibility(rt_iDiv.ent, visibility_external_allocated); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Div->ctx = &rt_Div; + map_Div->ctx = &rt_iDiv; } /* ... nor an unsigned div instruction ... */ { - runtime_rt rt_Div; i_instr_record *map_Div = &records[n_records++].i_instr; tp = new_type_method(ID("rt_uDiv"), 2, 1); @@ -626,25 +678,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); - rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp); - rt_Div.mode = mode_T; - rt_Div.res_mode = mode_Iu; - rt_Div.mem_proj_nr = pn_Div_M; - rt_Div.regular_proj_nr = pn_Div_X_regular; - rt_Div.exc_proj_nr = pn_Div_X_except; - rt_Div.exc_mem_proj_nr = pn_Div_M; - rt_Div.res_proj_nr = pn_Div_res; + rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp); + set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3")); + rt_uDiv.mode = mode_T; + rt_uDiv.res_mode = mode_Iu; + rt_uDiv.mem_proj_nr = pn_Div_M; + rt_uDiv.regular_proj_nr = pn_Div_X_regular; + rt_uDiv.exc_proj_nr = pn_Div_X_except; + rt_uDiv.exc_mem_proj_nr = pn_Div_M; + rt_uDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_Div.ent, visibility_external_allocated); + set_entity_visibility(rt_uDiv.ent, visibility_external_allocated); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Div->ctx = &rt_Div; + map_Div->ctx = &rt_uDiv; } /* ... nor a signed mod instruction ... */ { - runtime_rt rt_Mod; i_instr_record *map_Mod = &records[n_records++].i_instr; tp = new_type_method(ID("rt_iMod"), 2, 1); @@ -652,25 +704,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); - rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp); - rt_Mod.mode = mode_T; - rt_Mod.res_mode = mode_Is; - rt_Mod.mem_proj_nr = pn_Mod_M; - rt_Mod.regular_proj_nr = pn_Mod_X_regular; - rt_Mod.exc_proj_nr = pn_Mod_X_except; - rt_Mod.exc_mem_proj_nr = pn_Mod_M; - rt_Mod.res_proj_nr = pn_Mod_res; + rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp); + set_entity_ld_ident(rt_iMod.ent, ID("__modsi3")); + rt_iMod.mode = mode_T; + rt_iMod.res_mode = mode_Is; + rt_iMod.mem_proj_nr = pn_Mod_M; + rt_iMod.regular_proj_nr = pn_Mod_X_regular; + rt_iMod.exc_proj_nr = pn_Mod_X_except; + rt_iMod.exc_mem_proj_nr = pn_Mod_M; + rt_iMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_Mod.ent, visibility_external_allocated); + set_entity_visibility(rt_iMod.ent, visibility_external_allocated); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Mod->ctx = &rt_Mod; + map_Mod->ctx = &rt_iMod; } /* ... nor an unsigned mod. */ { - runtime_rt rt_Mod; i_instr_record *map_Mod = &records[n_records++].i_instr; tp = new_type_method(ID("rt_uMod"), 2, 1); @@ -678,25 +730,26 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); - rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp); - rt_Mod.mode = mode_T; - rt_Mod.res_mode = mode_Iu; - rt_Mod.mem_proj_nr = pn_Mod_M; - rt_Mod.regular_proj_nr = pn_Mod_X_regular; - rt_Mod.exc_proj_nr = pn_Mod_X_except; - rt_Mod.exc_mem_proj_nr = pn_Mod_M; - rt_Mod.res_proj_nr = pn_Mod_res; + rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp); + set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3")); + rt_uMod.mode = mode_T; + rt_uMod.res_mode = mode_Iu; + rt_uMod.mem_proj_nr = pn_Mod_M; + rt_uMod.regular_proj_nr = pn_Mod_X_regular; + rt_uMod.exc_proj_nr = pn_Mod_X_except; + rt_uMod.exc_mem_proj_nr = pn_Mod_M; + rt_uMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_Mod.ent, visibility_external_allocated); + set_entity_visibility(rt_uMod.ent, visibility_external_allocated); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Mod->ctx = &rt_Mod; + map_Mod->ctx = &rt_uMod; } if (n_records > 0) - lower_intrinsics(records, n_records); + lower_intrinsics(records, n_records, /*part_block_used=*/0); } /***************************************************************** @@ -722,7 +775,6 @@ static arm_isa_t arm_isa_template = { 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ NULL, /* current code generator */ - { NULL, }, /* emitter environment */ }; /** @@ -738,10 +790,10 @@ static void *arm_init(FILE *file_handle) { isa = xmalloc(sizeof(*isa)); memcpy(isa, &arm_isa_template, sizeof(*isa)); - arm_register_init(isa); + arm_register_init(); isa->cg = NULL; - be_emit_init_env(&isa->emit, file_handle); + be_emit_init(file_handle); arm_create_opcodes(); arm_handle_intrinsics(); @@ -764,9 +816,9 @@ static void *arm_init(FILE *file_handle) { static void arm_done(void *self) { arm_isa_t *isa = self; - be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_isa.main_env, 1); - be_emit_destroy_env(&isa->emit); + be_emit_exit(); free(self); } @@ -777,19 +829,19 @@ static void arm_done(void *self) { * here to speed up register allocation (and makes dumps * smaller and more readable). */ -static int arm_get_n_reg_class(const void *self) { - const arm_isa_t *isa = self; - - /* ARGH! is called BEFORE transform */ - return 2; - return isa->cg->have_fp ? 2 : 1; +static unsigned arm_get_n_reg_class(const void *self) { + (void) self; + return N_CLASSES; } /** * Return the register class with requested index. */ -static const arch_register_class_t *arm_get_reg_class(const void *self, int i) { - return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa]; +static const arch_register_class_t *arm_get_reg_class(const void *self, + unsigned i) { + (void) self; + assert(i < N_CLASSES); + return &arm_reg_classes[i]; } /** @@ -799,6 +851,7 @@ static const arch_register_class_t *arm_get_reg_class(const void *self, int i) { * @return A register class which can hold values of the given mode. */ const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) { + (void) self; if (mode_is_float(mode)) return &arm_reg_classes[CLASS_arm_fpa]; else @@ -808,13 +861,14 @@ const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const /** * Produces the type which sits between the stack args and the locals on the stack. * it will contain the return address and space to store the old base pointer. - * @return The Firm type modelling the ABI between type. + * @return The Firm type modeling the ABI between type. */ static ir_type *arm_get_between_type(void *self) { static ir_type *between_type = NULL; static ir_entity *old_bp_ent = NULL; + (void) self; - if(!between_type) { + if (between_type == NULL) { ir_entity *ret_addr_ent; ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P); @@ -867,8 +921,6 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap * arm_abi_env_t *env = self; ir_graph *irg = env->irg; ir_node *block = get_irg_start_block(irg); -// ir_node *regs[16]; -// int n_regs = 0; arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp]; ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp); @@ -876,29 +928,15 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap * ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp); ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); -// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]); -// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]); -// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]); -// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]); - if(env->flags.try_omit_fp) + if (env->flags.try_omit_fp) return env->isa->sp; - ip = be_new_Copy(gp, irg, block, sp ); + ip = be_new_Copy(gp, irg, block, sp); arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]); be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); -// if (r0) regs[n_regs++] = r0; -// if (r1) regs[n_regs++] = r1; -// if (r2) regs[n_regs++] = r2; -// if (r3) regs[n_regs++] = r3; -// sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp)); -// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0); -// arch_set_irn_register(env->arch_env, sp, env->isa->sp); store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem); - // TODO - // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0); - // arch_set_irn_register(env->arch_env, store, env->isa->sp); sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr); arch_set_irn_register(env->arch_env, sp, env->isa->sp); @@ -911,15 +949,8 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap * fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), new_tarval_from_long(4, get_irn_mode(fp))); - // TODO... - //set_arm_req_out_all(fp, fp_req); - //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0); arch_set_irn_register(env->arch_env, fp, env->isa->bp); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3); be_abi_reg_map_set(reg_map, env->isa->bp, fp); be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep); be_abi_reg_map_set(reg_map, env->isa->sp, sp); @@ -929,6 +960,9 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap * return env->isa->bp; } +/** + * Builds the ARM epilogue + */ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) { arm_abi_env_t *env = self; ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); @@ -937,7 +971,7 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); // TODO: Activate Omit fp in epilogue - if(env->flags.try_omit_fp) { + if (env->flags.try_omit_fp) { curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK); add_irn_dep(curr_sp, *mem); @@ -1004,9 +1038,12 @@ void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi 0, /* store arguments sequential */ 1, /* try to omit the frame pointer */ 1, /* the function can use any register as frame pointer */ - 1 /* a call can take the callee's address as an immediate */ + 1, /* a call can take the callee's address as an immediate */ + 0, /* IRG is a leaf function */ + 0 /* Set to one, if there is already enough room on the stack for call args. */ } }; + (void) self; /* set stack parameter passing style */ be_abi_call_set_flags(abi, flags, &arm_abi_callbacks); @@ -1014,25 +1051,49 @@ void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi for (i = 0; i < n; i++) { /* reg = get reg for param i; */ /* be_abi_call_param_reg(abi, i, reg); */ - if (i < 4) - + if (i < 4) { be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i)); - else - be_abi_call_param_stack(abi, i, 4, 0, 0); + } else { + tp = get_method_param_type(method_type, i); + mode = get_type_mode(tp); + be_abi_call_param_stack(abi, i, mode, 4, 0, 0); + } } - /* default: return value is in R0 resp. F0 */ - assert(get_method_n_ress(method_type) < 2); - if (get_method_n_ress(method_type) > 0) { + /* set return registers */ + n = get_method_n_ress(method_type); + + assert(n <= 2 && "more than two results not supported"); + + /* In case of 64bit returns, we will have two 32bit values */ + if (n == 2) { + tp = get_method_res_type(method_type, 0); + mode = get_type_mode(tp); + + assert(!mode_is_float(mode) && "two FP results not supported"); + + tp = get_method_res_type(method_type, 1); + mode = get_type_mode(tp); + + assert(!mode_is_float(mode) && "mixed INT, FP results not supported"); + + be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]); + be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]); + } else if (n == 1) { + const arch_register_t *reg; + tp = get_method_res_type(method_type, 0); + assert(is_atomic_type(tp)); mode = get_type_mode(tp); - be_abi_call_res_reg(abi, 0, - mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]); + reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]; + be_abi_call_res_reg(abi, 0, reg); } } static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) { + (void) self; + (void) irn; return &arm_irn_ops; } @@ -1041,10 +1102,12 @@ const arch_irn_handler_t arm_irn_handler = { }; const arch_irn_handler_t *arm_get_irn_handler(const void *self) { + (void) self; return &arm_irn_handler; } int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { + (void) block_env; if(!is_arm_irn(irn)) return -1; @@ -1055,6 +1118,7 @@ int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { * Initializes the code generator interface. */ static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) { + (void) self; return &arm_code_gen_if; } @@ -1064,12 +1128,16 @@ list_sched_selector_t arm_sched_selector; * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded */ static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { - memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t)); + (void) self; + memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector)); + /* arm_sched_selector.exectime = arm_sched_exectime; */ arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule; return &arm_sched_selector; + } static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) { + (void) self; return NULL; } @@ -1077,17 +1145,22 @@ static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) * Returns the necessary byte alignment for storing a register of given class. */ static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { + (void) self; + (void) cls; /* ARM is a 32 bit CPU, no need for other alignment */ return 4; } static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) { + (void) self; + (void) irn; /* TODO */ assert(0); return NULL; } static const be_machine_t *arm_get_machine(const void *self) { + (void) self; /* TODO */ assert(0); return NULL; @@ -1097,33 +1170,81 @@ static const be_machine_t *arm_get_machine(const void *self) { * Return irp irgs in the desired order. */ static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) { + (void) self; + (void) irg_list; return NULL; } +/** + * Allows or disallows the creation of Psi nodes for the given Phi nodes. + * @return 1 if allowed, 0 otherwise + */ +static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { + ir_node *cmp, *cmp_a, *phi; + ir_mode *mode; + + + /* currently Psi support is not implemented */ + return 0; + +/* we don't want long long Psi */ +#define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32) + + if (get_irn_mode(sel) != mode_b) + return 0; + + cmp = get_Proj_pred(sel); + cmp_a = get_Cmp_left(cmp); + mode = get_irn_mode(cmp_a); + + if (IS_BAD_PSI_MODE(mode)) + return 0; + + /* check the Phi nodes */ + for (phi = phi_list; phi; phi = get_irn_link(phi)) { + ir_node *pred_i = get_irn_n(phi, i); + ir_node *pred_j = get_irn_n(phi, j); + ir_mode *mode_i = get_irn_mode(pred_i); + ir_mode *mode_j = get_irn_mode(pred_j); + + if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j)) + return 0; + } + +#undef IS_BAD_PSI_MODE + + return 1; +} + /** * Returns the libFirm configuration parameter for this backend. */ static const backend_params *arm_get_libfirm_params(void) { - static arch_dep_params_t ad = { - 1, /* allow subs */ - 1, /* Muls are fast enough on ARM but ... */ - 1, /* ... one shift would be possible better */ - 0, /* SMUL is needed, only in Arch M*/ - 0, /* UMUL is needed, only in Arch M */ - 32, /* SMUL & UMUL available for 32 bit */ + static const ir_settings_if_conv_t ifconv = { + 4, /* maxdepth, doesn't matter for Psi-conversion */ + arm_is_psi_allowed /* allows or disallows Psi creation for given selector */ + }; + static ir_settings_arch_dep_t ad = { + 1, /* allow subs */ + 1, /* Muls are fast enough on ARM but ... */ + 31, /* ... one shift would be possible better */ + NULL, /* no evaluator function */ + 0, /* SMUL is needed, only in Arch M */ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ }; static backend_params p = { 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - 0, /* no different calling conventions */ NULL, /* no additional opcodes */ NULL, /* will be set later */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ - NULL, /* no if conversion settings */ + NULL, /* will be set below */ }; - p.dep_param = &ad; + p.dep_param = &ad; + p.if_conv_info = &ifconv; return &p; } @@ -1145,7 +1266,7 @@ static lc_opt_enum_int_var_t arch_fpu_var = { static const lc_opt_table_entry_t arm_options[] = { LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var), LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names), - { NULL } + LC_OPT_LAST }; const arch_isa_if_t arm_isa_if = { @@ -1174,6 +1295,9 @@ void be_init_arch_arm(void) lc_opt_add_table(arm_grp, arm_options); be_register_isa_if("arm", &arm_isa_if); + + arm_init_transform(); + arm_init_emitter(); } BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);