X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=a5c05b832d7b746734af825a81e3a5bb03f6b4bd;hb=536ef282dbc04bbd6033aaab60801981d0eb5dd7;hp=324c4385a105e982106449652f4794e8c307531b;hpb=42e1e7e95975e3bfb6b1dd17e9772f2ab23f39e1;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index 324c4385a..a5c05b832 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -27,8 +27,8 @@ #include "config.h" #endif -#include -#include +#include "lc_opts.h" +#include "lc_opts_enum.h" #include "pseudo_irg.h" #include "irgwalk.h" @@ -37,6 +37,7 @@ #include "ircons.h" #include "irgmod.h" #include "irgopt.h" +#include "iroptimize.h" #include "lowering.h" #include "bitset.h" @@ -203,17 +204,26 @@ static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) { + arch_irn_flags_t flags = arch_irn_flags_none; (void) self; - irn = skip_Proj_const(irn); - if (is_arm_irn(irn)) { - return get_arm_flags(irn); - } - else if (is_Unknown(irn)) { + if(is_Unknown(irn)) { return arch_irn_flags_ignore; } - return 0; + if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) { + ir_node *pred = get_Proj_pred(irn); + if (is_arm_irn(pred)) { + flags = get_arm_out_flags(pred, get_Proj_proj(irn)); + } + irn = pred; + } + + if (is_arm_irn(irn)) { + flags |= get_arm_flags(irn); + } + + return flags; } static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) @@ -739,7 +749,7 @@ static void arm_handle_intrinsics(void) { } if (n_records > 0) - lower_intrinsics(records, n_records); + lower_intrinsics(records, n_records, /*part_block_used=*/0); } /***************************************************************** @@ -765,7 +775,6 @@ static arm_isa_t arm_isa_template = { 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ NULL, /* current code generator */ - NULL_EMITTER, /* emitter environment */ }; /** @@ -784,7 +793,7 @@ static void *arm_init(FILE *file_handle) { arm_register_init(); isa->cg = NULL; - be_emit_init_env(&isa->emit, file_handle); + be_emit_init(file_handle); arm_create_opcodes(); arm_handle_intrinsics(); @@ -807,9 +816,9 @@ static void *arm_init(FILE *file_handle) { static void arm_done(void *self) { arm_isa_t *isa = self; - be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_isa.main_env, 1); - be_emit_destroy_env(&isa->emit); + be_emit_exit(); free(self); } @@ -820,19 +829,18 @@ static void arm_done(void *self) { * here to speed up register allocation (and makes dumps * smaller and more readable). */ -static int arm_get_n_reg_class(const void *self) { - const arm_isa_t *isa = self; - - /* ARGH! is called BEFORE transform */ +static unsigned arm_get_n_reg_class(const void *self) { + (void) self; return N_CLASSES; - return isa->cg->have_fp_insn ? 2 : 1; } /** * Return the register class with requested index. */ -static const arch_register_class_t *arm_get_reg_class(const void *self, int i) { +static const arch_register_class_t *arm_get_reg_class(const void *self, + unsigned i) { (void) self; + assert(i < N_CLASSES); return &arm_reg_classes[i]; } @@ -1043,11 +1051,13 @@ void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi for (i = 0; i < n; i++) { /* reg = get reg for param i; */ /* be_abi_call_param_reg(abi, i, reg); */ - if (i < 4) - + if (i < 4) { be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i)); - else - be_abi_call_param_stack(abi, i, 4, 0, 0); + } else { + tp = get_method_param_type(method_type, i); + mode = get_type_mode(tp); + be_abi_call_param_stack(abi, i, mode, 4, 0, 0); + } } /* set return registers */ @@ -1119,10 +1129,11 @@ list_sched_selector_t arm_sched_selector; */ static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { (void) self; - (void) selector; - memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t)); + memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector)); + /* arm_sched_selector.exectime = arm_sched_exectime; */ arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule; return &arm_sched_selector; + } static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) { @@ -1209,17 +1220,18 @@ static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { * Returns the libFirm configuration parameter for this backend. */ static const backend_params *arm_get_libfirm_params(void) { - static const opt_if_conv_info_t ifconv = { + static const ir_settings_if_conv_t ifconv = { 4, /* maxdepth, doesn't matter for Psi-conversion */ arm_is_psi_allowed /* allows or disallows Psi creation for given selector */ }; - static arch_dep_params_t ad = { - 1, /* allow subs */ - 1, /* Muls are fast enough on ARM but ... */ - 31, /* ... one shift would be possible better */ - 0, /* SMUL is needed, only in Arch M */ - 0, /* UMUL is needed, only in Arch M */ - 32, /* SMUL & UMUL available for 32 bit */ + static ir_settings_arch_dep_t ad = { + 1, /* allow subs */ + 1, /* Muls are fast enough on ARM but ... */ + 31, /* ... one shift would be possible better */ + NULL, /* no evaluator function */ + 0, /* SMUL is needed, only in Arch M */ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ }; static backend_params p = { 1, /* need dword lowering */ @@ -1285,6 +1297,7 @@ void be_init_arch_arm(void) be_register_isa_if("arm", &arm_isa_if); arm_init_transform(); + arm_init_emitter(); } BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);