X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=89e01fa1aa29247780bc026e55b1c0b96bb4d524;hb=3f1d2fb001738ccea94f601a71a21d6dbf8ad8a9;hp=3ed7ce57fc0cd9d06718ad8019774c6207120a03;hpb=fd5331da46a1c09e53d010f7594a17c08c7a1e41;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index 3ed7ce57f..89e01fa1a 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -21,14 +21,12 @@ * @file * @brief The main arm backend driver file. * @author Matthias Braun, Oliver Richter, Tobias Gneist - * @version $Id$ */ #include "config.h" #include "lc_opts.h" #include "lc_opts_enum.h" -#include "pseudo_irg.h" #include "irgwalk.h" #include "irprog.h" #include "irprintf.h" @@ -37,7 +35,7 @@ #include "irgopt.h" #include "iroptimize.h" #include "irdump.h" -#include "lowering.h" +#include "lower_calls.h" #include "error.h" #include "bitset.h" @@ -45,19 +43,19 @@ #include "array_t.h" #include "irtools.h" -#include "../bearch.h" -#include "../benode.h" -#include "../belower.h" -#include "../besched.h" +#include "bearch.h" +#include "benode.h" +#include "belower.h" +#include "besched.h" #include "be.h" -#include "../bemachine.h" -#include "../beilpsched.h" -#include "../bemodule.h" -#include "../beirg.h" -#include "../bespillslots.h" -#include "../begnuas.h" -#include "../belistsched.h" -#include "../beflags.h" +#include "bemodule.h" +#include "beirg.h" +#include "bespillslots.h" +#include "bespillutil.h" +#include "begnuas.h" +#include "belistsched.h" +#include "beflags.h" +#include "bestack.h" #include "bearch_arm_t.h" @@ -72,7 +70,7 @@ static arch_irn_class_t arm_classify(const ir_node *irn) { (void) irn; /* TODO: we should mark reload/spill instructions and classify them here */ - return 0; + return arch_irn_class_none; } static ir_entity *arm_get_frame_entity(const ir_node *irn) @@ -80,8 +78,8 @@ static ir_entity *arm_get_frame_entity(const ir_node *irn) const arm_attr_t *attr = get_arm_attr_const(irn); if (is_arm_FrameAddr(irn)) { - const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn); - return attr->entity; + const arm_SymConst_attr_t *frame_attr = get_arm_SymConst_attr_const(irn); + return frame_attr->entity; } if (attr->is_load_store) { const arm_load_store_attr_t *load_store_attr @@ -100,7 +98,7 @@ static ir_entity *arm_get_frame_entity(const ir_node *irn) static void arm_set_stack_bias(ir_node *irn, int bias) { if (is_arm_FrameAddr(irn)) { - arm_SymConst_attr_t *attr = get_irn_generic_attr(irn); + arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn); attr->fp_offset += bias; } else { arm_load_store_attr_t *attr = get_arm_load_store_attr(irn); @@ -120,7 +118,6 @@ static int arm_get_sp_bias(const ir_node *irn) /* fill register allocator interface */ static const arch_irn_ops_t arm_irn_ops = { - get_arm_in_req, arm_classify, arm_get_frame_entity, arm_set_stack_bias, @@ -135,67 +132,68 @@ static const arch_irn_ops_t arm_irn_ops = { * Transforms the standard Firm graph into * a ARM firm graph. */ -static void arm_prepare_graph(void *self) +static void arm_prepare_graph(ir_graph *irg) { - arm_code_gen_t *cg = self; - /* transform nodes into assembler instructions */ - arm_transform_graph(cg); + arm_transform_graph(irg); /* do local optimizations (mainly CSE) */ - local_optimize_graph(cg->irg); - - if (cg->dump) - dump_ir_graph(cg->irg, "transformed"); + local_optimize_graph(irg); /* do code placement, to optimize the position of constants */ - place_code(cg->irg); - - if (cg->dump) - dump_ir_graph(cg->irg, "place"); + place_code(irg); } -/** - * Called immediately before emit phase. - */ -static void arm_finish_irg(void *self) +static void arm_collect_frame_entity_nodes(ir_node *node, void *data) { - arm_code_gen_t *cg = self; - - /* do peephole optimizations and fix stack offsets */ - arm_peephole_optimization(cg); -} + be_fec_env_t *env = (be_fec_env_t*)data; + const ir_mode *mode; + int align; + ir_entity *entity; + const arm_load_store_attr_t *attr; -static ir_node *arm_flags_remat(ir_node *node, ir_node *after) -{ - ir_node *block; - ir_node *copy; + if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { + mode = get_irn_mode(node); + align = get_mode_size_bytes(mode); + be_node_needs_frame_entity(env, node, mode, align); + return; + } - if (is_Block(after)) { - block = after; - } else { - block = get_nodes_block(after); + switch (get_arm_irn_opcode(node)) { + case iro_arm_Ldf: + case iro_arm_Ldr: + break; + default: + return; } - copy = exact_copy(node); - set_nodes_block(copy, block); - sched_add_after(after, copy); - return copy; + + attr = get_arm_load_store_attr_const(node); + entity = attr->entity; + mode = attr->load_store_mode; + align = get_mode_size_bytes(mode); + if (entity != NULL) + return; + if (!attr->is_frame_entity) + return; + be_node_needs_frame_entity(env, node, mode, align); } -static void arm_before_ra(void *self) +static void arm_set_frame_entity(ir_node *node, ir_entity *entity) { - arm_code_gen_t *cg = self; - - be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags], - &arm_flags_remat); + if (is_be_node(node)) { + be_node_set_frame_entity(node, entity); + } else { + arm_load_store_attr_t *attr = get_arm_load_store_attr(node); + attr->entity = entity; + } } static void transform_Reload(ir_node *node) { ir_node *block = get_nodes_block(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *ptr = get_irn_n(node, be_pos_Reload_frame); - ir_node *mem = get_irn_n(node, be_pos_Reload_mem); + ir_node *ptr = get_irn_n(node, n_be_Reload_frame); + ir_node *mem = get_irn_n(node, n_be_Reload_mem); ir_mode *mode = get_irn_mode(node); ir_entity *entity = be_get_frame_entity(node); const arch_register_t *reg; @@ -220,9 +218,10 @@ static void transform_Spill(ir_node *node) { ir_node *block = get_nodes_block(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *ptr = get_irn_n(node, be_pos_Spill_frame); - ir_node *mem = new_NoMem(); - ir_node *val = get_irn_n(node, be_pos_Spill_val); + ir_node *ptr = get_irn_n(node, n_be_Spill_frame); + ir_graph *irg = get_irn_irg(node); + ir_node *mem = get_irg_no_mem(irg); + ir_node *val = get_irn_n(node, n_be_Spill_val); ir_mode *mode = get_irn_mode(val); ir_entity *entity = be_get_frame_entity(node); ir_node *sched_point; @@ -254,123 +253,40 @@ static void arm_after_ra_walker(ir_node *block, void *data) } } -static void arm_collect_frame_entity_nodes(ir_node *node, void *data) -{ - be_fec_env_t *env = data; - const ir_mode *mode; - int align; - ir_entity *entity; - const arm_load_store_attr_t *attr; - - if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { - mode = get_irn_mode(node); - align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - return; - } - - switch (get_arm_irn_opcode(node)) { - case iro_arm_Ldf: - case iro_arm_Ldr: - break; - default: - return; - } - - attr = get_arm_load_store_attr_const(node); - entity = attr->entity; - mode = attr->load_store_mode; - align = get_mode_size_bytes(mode); - if (entity != NULL) - return; - if (!attr->is_frame_entity) - return; - be_node_needs_frame_entity(env, node, mode, align); -} - -static void arm_set_frame_entity(ir_node *node, ir_entity *entity) -{ - if (is_be_node(node)) { - be_node_set_frame_entity(node, entity); - } else { - arm_load_store_attr_t *attr = get_arm_load_store_attr(node); - attr->entity = entity; - } -} - -static void arm_after_ra(void *self) +/** + * Called immediately before emit phase. + */ +static void arm_finish_irg(ir_graph *irg) { - arm_code_gen_t *cg = self; - ir_graph *irg = cg->irg; - - be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg); + be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg); + bool at_begin = stack_layout->sp_relative ? true : false; + be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg); irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env); - be_assign_entities(fec_env, arm_set_frame_entity); + be_assign_entities(fec_env, arm_set_frame_entity, at_begin); be_free_frame_entity_coalescer(fec_env); - irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL); -} - -/** - * Emits the code, closes the output file and frees - * the code generator interface. - */ -static void arm_emit_and_done(void *self) -{ - arm_code_gen_t *cg = self; - ir_graph *irg = cg->irg; + irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL); - arm_gen_routine(cg, irg); + /* fix stack entity offsets */ + be_abi_fix_stack_nodes(irg); + be_abi_fix_stack_bias(irg); - /* de-allocate code generator */ - del_set(cg->reg_set); - free(self); + /* do peephole optimizations and fix stack offsets */ + arm_peephole_optimization(irg); } -/* forward */ -static void *arm_cg_init(ir_graph *irg); - -static const arch_code_generator_if_t arm_code_gen_if = { - arm_cg_init, - NULL, /* get_pic_base */ - NULL, /* before abi introduce */ - arm_prepare_graph, - NULL, /* spill */ - arm_before_ra, /* before register allocation hook */ - arm_after_ra, - arm_finish_irg, - arm_emit_and_done, -}; +static void arm_before_ra(ir_graph *irg) +{ + be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL); +} /** * Initializes the code generator. */ -static void *arm_cg_init(ir_graph *irg) +static void arm_init_graph(ir_graph *irg) { - static ir_type *int_tp = NULL; - arm_isa_t *isa = (arm_isa_t *) be_get_irg_arch_env(irg); - arm_code_gen_t *cg; - - if (! int_tp) { - /* create an integer type with machine size */ - int_tp = new_type_primitive(mode_Is); - } - - cg = XMALLOC(arm_code_gen_t); - cg->impl = &arm_code_gen_if; - cg->irg = irg; - cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); - cg->isa = isa; - cg->int_tp = int_tp; - cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0; - - FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg"); - - /* enter the current code generator */ - isa->cg = cg; - - return (arch_code_generator_t *)cg; + (void) irg; } @@ -389,8 +305,8 @@ static void arm_handle_intrinsics(void) #define ID(x) new_id_from_chars(x, sizeof(x)-1) - int_tp = new_type_primitive(mode_Is); - uint_tp = new_type_primitive(mode_Iu); + int_tp = get_type_for_mode(mode_Is); + uint_tp = get_type_for_mode(mode_Iu); /* ARM has neither a signed div instruction ... */ { @@ -408,7 +324,6 @@ static void arm_handle_intrinsics(void) rt_iDiv.mem_proj_nr = pn_Div_M; rt_iDiv.regular_proj_nr = pn_Div_X_regular; rt_iDiv.exc_proj_nr = pn_Div_X_except; - rt_iDiv.exc_mem_proj_nr = pn_Div_M; rt_iDiv.res_proj_nr = pn_Div_res; add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT); @@ -435,7 +350,6 @@ static void arm_handle_intrinsics(void) rt_uDiv.mem_proj_nr = pn_Div_M; rt_uDiv.regular_proj_nr = pn_Div_X_regular; rt_uDiv.exc_proj_nr = pn_Div_X_except; - rt_uDiv.exc_mem_proj_nr = pn_Div_M; rt_uDiv.res_proj_nr = pn_Div_res; set_entity_visibility(rt_uDiv.ent, ir_visibility_external); @@ -461,7 +375,6 @@ static void arm_handle_intrinsics(void) rt_iMod.mem_proj_nr = pn_Mod_M; rt_iMod.regular_proj_nr = pn_Mod_X_regular; rt_iMod.exc_proj_nr = pn_Mod_X_except; - rt_iMod.exc_mem_proj_nr = pn_Mod_M; rt_iMod.res_proj_nr = pn_Mod_res; set_entity_visibility(rt_iMod.ent, ir_visibility_external); @@ -487,7 +400,6 @@ static void arm_handle_intrinsics(void) rt_uMod.mem_proj_nr = pn_Mod_M; rt_uMod.regular_proj_nr = pn_Mod_X_regular; rt_uMod.exc_proj_nr = pn_Mod_X_except; - rt_uMod.exc_mem_proj_nr = pn_Mod_M; rt_uMod.res_proj_nr = pn_Mod_res; set_entity_visibility(rt_uMod.ent, ir_visibility_external); @@ -502,56 +414,45 @@ static void arm_handle_intrinsics(void) lower_intrinsics(records, n_records, /*part_block_used=*/0); } - +extern const arch_isa_if_t arm_isa_if; static arm_isa_t arm_isa_template = { { &arm_isa_if, /* isa interface */ - &arm_gp_regs[REG_SP], /* stack pointer */ - &arm_gp_regs[REG_R11], /* base pointer */ + N_ARM_REGISTERS, + arm_registers, + N_ARM_CLASSES, + arm_reg_classes, + &arm_registers[REG_SP], /* stack pointer */ + &arm_registers[REG_R11], /* base pointer */ &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */ - -1, /* stack direction */ 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ 7, /* spill costs */ 5, /* reload costs */ true, /* we do have custom abi handling */ }, - 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ - NULL, /* current code generator */ }; /** * Initializes the backend ISA and opens the output file. */ -static arch_env_t *arm_init(FILE *file_handle) +static arch_env_t *arm_init(const be_main_env_t *env) { - static int inited = 0; - arm_isa_t *isa; - - if (inited) - return NULL; - - isa = XMALLOC(arm_isa_t); - memcpy(isa, &arm_isa_template, sizeof(*isa)); + arm_isa_t *isa = XMALLOC(arm_isa_t); + *isa = arm_isa_template; arm_register_init(); - isa->cg = NULL; - be_emit_init(file_handle); - arm_create_opcodes(&arm_irn_ops); arm_handle_intrinsics(); be_gas_emit_types = false; - /* needed for the debug support */ - be_gas_emit_switch_section(GAS_SECTION_TEXT); - be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix()); - be_emit_write_line(); + be_emit_init(env->file_handle); + be_gas_begin_compilation_unit(env); - inited = 1; - return &isa->arch_env; + return &isa->base; } @@ -561,122 +462,14 @@ static arch_env_t *arm_init(FILE *file_handle) */ static void arm_done(void *self) { - arm_isa_t *isa = self; + arm_isa_t *isa = (arm_isa_t*)self; - be_gas_emit_decls(isa->arch_env.main_env); + be_gas_end_compilation_unit(isa->base.main_env); be_emit_exit(); free(self); } - -/** - * Report the number of register classes. - * If we don't have fp instructions, report only GP - * here to speed up register allocation (and makes dumps - * smaller and more readable). - */ -static unsigned arm_get_n_reg_class(void) -{ - return N_CLASSES; -} - -/** - * Return the register class with requested index. - */ -static const arch_register_class_t *arm_get_reg_class(unsigned i) -{ - assert(i < N_CLASSES); - return &arm_reg_classes[i]; -} - -/** - * Get the register class which shall be used to store a value of a given mode. - * @param self The this pointer. - * @param mode The mode in question. - * @return A register class which can hold values of the given mode. - */ -static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode) -{ - if (mode_is_float(mode)) - return &arm_reg_classes[CLASS_arm_fpa]; - else - return &arm_reg_classes[CLASS_arm_gp]; -} - -static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) -{ - (void) block_env; - if (!is_arm_irn(irn)) - return -1; - - return 1; -} - -/** - * Initializes the code generator interface. - */ -static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) -{ - (void) self; - return &arm_code_gen_if; -} - -list_sched_selector_t arm_sched_selector; - -/** - * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded - */ -static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) -{ - (void) self; - memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector)); - /* arm_sched_selector.exectime = arm_sched_exectime; */ - arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule; - return &arm_sched_selector; - -} - -static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) -{ - (void) self; - return NULL; -} - -/** - * Returns the necessary byte alignment for storing a register of given class. - */ -static int arm_get_reg_class_alignment(const arch_register_class_t *cls) -{ - (void) cls; - /* ARM is a 32 bit CPU, no need for other alignment */ - return 4; -} - -static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn) -{ - (void) irn; - /* TODO */ - panic("Unimplemented arm_get_allowed_execution_units()"); -} - -static const be_machine_t *arm_get_machine(const void *self) -{ - (void) self; - /* TODO */ - panic("Unimplemented arm_get_machine()"); -} - -/** - * Return irp irgs in the desired order. - */ -static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) -{ - (void) self; - (void) irg_list; - return NULL; -} - /** * Allows or disallows the creation of Psi nodes for the given Phi nodes. * @return 1 if allowed, 0 otherwise @@ -687,8 +480,7 @@ static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false, (void) sel; (void) mux_false; (void) mux_true; - - return 0; + return false; } static asm_constraint_flags_t arm_parse_asm_constraint(const char **c) @@ -704,18 +496,35 @@ static int arm_is_valid_clobber(const char *clobber) return 0; } +static void arm_lower_for_target(void) +{ + size_t i, n_irgs = get_irp_n_irgs(); + + /* lower compound param handling */ + lower_calls_with_compounds(LF_RETURN_HIDDEN); + + for (i = 0; i < n_irgs; ++i) { + ir_graph *irg = get_irp_irg(i); + lower_switch(irg, 4, 256, false); + } + + for (i = 0; i < n_irgs; ++i) { + ir_graph *irg = get_irp_irg(i); + /* Turn all small CopyBs into loads/stores and all bigger CopyBs into + * memcpy calls. + * TODO: These constants need arm-specific tuning. */ + lower_CopyB(irg, 31, 32, false); + } +} + /** * Returns the libFirm configuration parameter for this backend. */ static const backend_params *arm_get_libfirm_params(void) { - static const ir_settings_if_conv_t ifconv = { - 4, /* maxdepth, doesn't matter for Psi-conversion */ - arm_is_mux_allowed /* allows or disallows Mux creation for given selector */ - }; static ir_settings_arch_dep_t ad = { 1, /* allow subs */ - 1, /* Muls are fast enough on ARM but ... */ + 1, /* Muls are fast enough on ARM but ... */ 31, /* ... one shift would be possible better */ NULL, /* no evaluator function */ 0, /* SMUL is needed, only in Arch M */ @@ -723,21 +532,24 @@ static const backend_params *arm_get_libfirm_params(void) 32, /* SMUL & UMUL available for 32 bit */ }; static backend_params p = { - 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - NULL, /* will be set later */ - NULL, /* but yet no creator function */ - NULL, /* context for create_intrinsic_fkt */ - NULL, /* ifconv_info will be set below */ + 1, /* support Rotl nodes */ + 1, /* big endian */ + 1, /* modulo shift efficient */ + 0, /* non-modulo shift not efficient */ + &ad, /* will be set later */ + arm_is_mux_allowed, /* allow_ifconv function */ + 32, /* machine size */ NULL, /* float arithmetic mode (TODO) */ + NULL, /* long long type */ + NULL, /* unsigned long long type */ + NULL, /* long double type */ 0, /* no trampoline support: size 0 */ 0, /* no trampoline support: align 0 */ NULL, /* no trampoline support: no trampoline builder */ 4 /* alignment of stack parameter */ }; - p.dep_param = &ad; - p.if_conv_info = &ifconv; return &p; } @@ -758,32 +570,33 @@ static lc_opt_enum_int_var_t arch_fpu_var = { static const lc_opt_table_entry_t arm_options[] = { LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var), - LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names), LC_OPT_LAST }; const arch_isa_if_t arm_isa_if = { arm_init, + arm_lower_for_target, arm_done, NULL, /* handle_intrinsics */ - arm_get_n_reg_class, - arm_get_reg_class, - arm_get_reg_class_for_mode, NULL, - arm_get_code_generator_if, - arm_get_list_sched_selector, - arm_get_ilp_sched_selector, - arm_get_reg_class_alignment, arm_get_libfirm_params, - arm_get_allowed_execution_units, - arm_get_machine, - arm_get_irg_list, NULL, /* mark remat */ arm_parse_asm_constraint, - arm_is_valid_clobber + arm_is_valid_clobber, + + arm_init_graph, + NULL, /* get_pic_base */ + NULL, /* before_abi */ + arm_prepare_graph, + arm_before_ra, + arm_finish_irg, + arm_gen_routine, + NULL, /* register_saved_by */ + be_new_spill, + be_new_reload, }; -BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm); +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm) void be_init_arch_arm(void) { lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");