X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=49f02261be25695d28169d0569e9ec5ec83cb38f;hb=e1397b01aceb38b6bb62c319007146af3b922f39;hp=15adde9077ac5c1ba68cd406ed17d344e79e572c;hpb=5d79fe73922ccec0217bad72eca772e0487b7c49;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index 15adde907..49f02261b 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -23,12 +23,10 @@ * @author Oliver Richter, Tobias Gneist * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif -#include -#include +#include "lc_opts.h" +#include "lc_opts_enum.h" #include "pseudo_irg.h" #include "irgwalk.h" @@ -37,10 +35,14 @@ #include "ircons.h" #include "irgmod.h" #include "irgopt.h" +#include "iroptimize.h" #include "lowering.h" +#include "error.h" #include "bitset.h" #include "debug.h" +#include "array_t.h" +#include "irtools.h" #include "../bearch_t.h" /* the general register allocator interface */ #include "../benode_t.h" @@ -60,6 +62,7 @@ #include "arm_new_nodes.h" /* arm nodes interface */ #include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */ #include "arm_transform.h" +#include "arm_optimize.h" #include "arm_emitter.h" #include "arm_map_regs.h" @@ -84,14 +87,13 @@ static set *cur_reg_set = NULL; * If the node returns a tuple (mode_T) then the proj's * will be asked for this information. */ -static const -arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node, - int pos) { +static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node, + int pos) +{ long node_pos = pos == -1 ? 0 : pos; ir_mode *mode = get_irn_mode(node); - FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); - if (is_Block(node) || mode == mode_X || mode == mode_M) { + if (is_Block(node) || mode == mode_X) { return arch_no_register_req; } @@ -100,8 +102,9 @@ arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node, } if (is_Proj(node)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ + if(mode == mode_M) + return arch_no_register_req; + if(pos >= 0) { return arch_no_register_req; } @@ -127,111 +130,52 @@ arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node, return arch_no_register_req; } -static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { - int pos = 0; - - if (get_irn_mode(irn) == mode_X) { - return; - } - - if (is_Proj(irn)) { - pos = get_Proj_proj(irn); - irn = skip_Proj(irn); - } - - if (is_arm_irn(irn)) { - const arch_register_t **slots; - - slots = get_arm_slots(irn); - slots[pos] = reg; - } - else { - /* here we set the registers for the Phi nodes */ - arm_set_firm_reg(irn, reg, cur_reg_set); - } -} - -static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) { - int pos = 0; - const arch_register_t *reg = NULL; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return NULL; - } - - pos = get_Proj_proj(irn); - irn = skip_Proj_const(irn); - } - - if (is_arm_irn(irn)) { - const arch_register_t **slots; - slots = get_arm_slots(irn); - reg = slots[pos]; - } - else { - reg = arm_get_firm_reg(irn, cur_reg_set); - } - - return reg; -} - -static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) { +static arch_irn_class_t arm_classify(const ir_node *irn) +{ irn = skip_Proj_const(irn); if (is_cfop(irn)) { return arch_irn_class_branch; } - else if (is_arm_irn(irn)) { - return arch_irn_class_normal; - } return 0; } -static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) { - irn = skip_Proj_const(irn); - - if (is_arm_irn(irn)) { - return get_arm_flags(irn); - } - else if (is_Unknown(irn)) { - return arch_irn_flags_ignore; - } - - return 0; -} - -static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) { - /* TODO: return the entity assigned to the frame */ +static ir_entity *arm_get_frame_entity(const ir_node *irn) { + /* we do NOT transform be_Spill or be_Reload nodes, so we never + have frame access using ARM nodes. */ + (void) irn; return NULL; } -static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { - /* TODO: set the entity assigned to the frame */ +static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) { + (void) irn; + (void) ent; + panic("arm_set_frame_entity() called. This should not happen."); } /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ -static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) { +static void arm_set_stack_bias(ir_node *irn, int bias) +{ + (void) irn; + (void) bias; /* TODO: correct offset if irn accesses the stack */ } -static int arm_get_sp_bias(const void *self, const ir_node *irn) { +static int arm_get_sp_bias(const ir_node *irn) +{ + (void) irn; return 0; } /* fill register allocator interface */ -static const arch_irn_ops_if_t arm_irn_ops_if = { +static const arch_irn_ops_t arm_irn_ops = { arm_get_irn_reg_req, - arm_set_irn_reg, - arm_get_irn_reg, arm_classify, - arm_get_flags, arm_get_frame_entity, arm_set_frame_entity, arm_set_stack_bias, @@ -242,13 +186,6 @@ static const arch_irn_ops_if_t arm_irn_ops_if = { NULL, /* perform_memory_operand */ }; -arm_irn_ops_t arm_irn_ops = { - &arm_irn_ops_if, - NULL -}; - - - /************************************************** * _ _ __ * | | (_)/ _| @@ -286,21 +223,18 @@ static void arm_prepare_graph(void *self) { /** * Called immediately before emit phase. */ -static void arm_finish_irg(void *self) { - /* TODO: - fix offsets for nodes accessing stack - - ... - */ -} - +static void arm_finish_irg(void *self) +{ + arm_code_gen_t *cg = self; -/** - * These are some hooks which must be filled but are probably not needed. - */ -static void arm_before_sched(void *self) { - /* Some stuff you need to do after scheduling but before register allocation */ + /* do peephole optimizations and fix stack offsets */ + arm_peephole_optimization(cg); } -static void arm_before_ra(void *self) { + +static void arm_before_ra(void *self) +{ + (void) self; /* Some stuff you need to do immediately after register allocation */ } @@ -308,7 +242,8 @@ static void arm_before_ra(void *self) { * We transform Spill and Reload here. This needs to be done before * stack biasing otherwise we would miss the corrected offset for these nodes. */ -static void arm_after_ra(void *self) { +static void arm_after_ra(void *self) +{ arm_code_gen_t *cg = self; be_coalesce_spillslots(cg->birg); } @@ -357,20 +292,19 @@ static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem, v = (v << 8) | get_tarval_sub_bits(tv, 1); v = (v << 8) | get_tarval_sub_bits(tv, 0); *resL = new_Const_long(mode_Is, v); - } - else if (get_irn_op(skip_Proj(arg)) == op_Load) { + } else if (is_Load(skip_Proj(arg))) { /* FIXME: handling of low/high depends on LE/BE here */ - assert(0); + panic("Unimplemented convert_dbl_to_int() case"); } else { ir_graph *irg = current_ir_graph; ir_node *conv; - conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem); + conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem); /* move high/low */ - *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low); - *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high); - mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M); + *resL = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_low); + *resH = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_high); + mem = new_r_Proj(bl, conv, mode_M, pn_arm_fpaDbl2GP_M); } return mem; } @@ -383,7 +317,10 @@ static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem, * 1.) A constant: simply move * 2.) A load: simply load */ -static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) { +static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) +{ + (void) bl; + if (is_Const(arg)) { tarval *tv = get_Const_tarval(arg); unsigned v; @@ -394,14 +331,12 @@ static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) { v = (v << 8) | get_tarval_sub_bits(tv, 1); v = (v << 8) | get_tarval_sub_bits(tv, 0); return new_Const_long(mode_Is, v); - } - else if (get_irn_op(skip_Proj(arg)) == op_Load) { + } else if (is_Load(skip_Proj(arg))) { ir_node *load; load = skip_Proj(arg); } - assert(0); - return NULL; + panic("Unimplemented convert_sng_to_int() case"); } /** @@ -412,7 +347,7 @@ static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) { static void handle_calls(ir_node *call, void *env) { arm_code_gen_t *cg = env; - int i, j, n, size, idx, flag, n_param, n_res; + int i, j, n, size, idx, flag, n_param, n_res, first_variadic; ir_type *mtp, *new_mtd, *new_tp[5]; ir_node *new_in[5], **in; ir_node *bl; @@ -491,7 +426,9 @@ static void handle_calls(ir_node *call, void *env) set_method_res_type(new_mtd, i, get_method_res_type(mtp, i)); set_method_calling_convention(new_mtd, get_method_calling_convention(mtp)); - set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp)); + first_variadic = get_method_first_variadic_param_index(mtp); + if (first_variadic >= 0) + set_method_first_variadic_param_index(new_mtd, first_variadic); if (is_lowered_type(mtp)) { mtp = get_associated_type(mtp); @@ -528,10 +465,10 @@ static void *arm_cg_init(be_irg_t *birg); static const arch_code_generator_if_t arm_code_gen_if = { arm_cg_init, + NULL, /* get_pic_base */ arm_before_abi, /* before abi introduce */ arm_prepare_graph, NULL, /* spill */ - arm_before_sched, /* before scheduling hook */ arm_before_ra, /* before register allocation hook */ arm_after_ra, arm_finish_irg, @@ -543,7 +480,7 @@ static const arch_code_generator_if_t arm_code_gen_if = { */ static void *arm_cg_init(be_irg_t *birg) { static ir_type *int_tp = NULL; - arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa; + arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env; arm_code_gen_t *cg; if (! int_tp) { @@ -551,23 +488,22 @@ static void *arm_cg_init(be_irg_t *birg) { int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is); } - cg = xmalloc(sizeof(*cg)); + cg = XMALLOC(arm_code_gen_t); cg->impl = &arm_code_gen_if; cg->irg = birg->irg; cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); - cg->arch_env = birg->main_env->arch_env; cg->isa = isa; cg->birg = birg; cg->int_tp = int_tp; cg->have_fp_insn = 0; + cg->unknown_gp = NULL; + cg->unknown_fpa = NULL; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg"); cur_reg_set = cg->reg_set; - arm_irn_ops.cg = cg; - /* enter the current code generator */ isa->cg = cg; @@ -585,6 +521,8 @@ static void arm_handle_intrinsics(void) { i_record records[8]; int n_records = 0; + runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod; + #define ID(x) new_id_from_chars(x, sizeof(x)-1) int_tp = new_type_primitive(ID("int"), mode_Is); @@ -592,7 +530,6 @@ static void arm_handle_intrinsics(void) { /* ARM has neither a signed div instruction ... */ { - runtime_rt rt_Div; i_instr_record *map_Div = &records[n_records++].i_instr; tp = new_type_method(ID("rt_iDiv"), 2, 1); @@ -600,25 +537,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); - rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp); - rt_Div.mode = mode_T; - rt_Div.res_mode = mode_Is; - rt_Div.mem_proj_nr = pn_Div_M; - rt_Div.regular_proj_nr = pn_Div_X_regular; - rt_Div.exc_proj_nr = pn_Div_X_except; - rt_Div.exc_mem_proj_nr = pn_Div_M; - rt_Div.res_proj_nr = pn_Div_res; + rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp); + set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3")); + rt_iDiv.mode = mode_T; + rt_iDiv.res_mode = mode_Is; + rt_iDiv.mem_proj_nr = pn_Div_M; + rt_iDiv.regular_proj_nr = pn_Div_X_regular; + rt_iDiv.exc_proj_nr = pn_Div_X_except; + rt_iDiv.exc_mem_proj_nr = pn_Div_M; + rt_iDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_Div.ent, visibility_external_allocated); + set_entity_visibility(rt_iDiv.ent, visibility_external_allocated); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Div->ctx = &rt_Div; + map_Div->ctx = &rt_iDiv; } /* ... nor an unsigned div instruction ... */ { - runtime_rt rt_Div; i_instr_record *map_Div = &records[n_records++].i_instr; tp = new_type_method(ID("rt_uDiv"), 2, 1); @@ -626,25 +563,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); - rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp); - rt_Div.mode = mode_T; - rt_Div.res_mode = mode_Iu; - rt_Div.mem_proj_nr = pn_Div_M; - rt_Div.regular_proj_nr = pn_Div_X_regular; - rt_Div.exc_proj_nr = pn_Div_X_except; - rt_Div.exc_mem_proj_nr = pn_Div_M; - rt_Div.res_proj_nr = pn_Div_res; + rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp); + set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3")); + rt_uDiv.mode = mode_T; + rt_uDiv.res_mode = mode_Iu; + rt_uDiv.mem_proj_nr = pn_Div_M; + rt_uDiv.regular_proj_nr = pn_Div_X_regular; + rt_uDiv.exc_proj_nr = pn_Div_X_except; + rt_uDiv.exc_mem_proj_nr = pn_Div_M; + rt_uDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_Div.ent, visibility_external_allocated); + set_entity_visibility(rt_uDiv.ent, visibility_external_allocated); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Div->ctx = &rt_Div; + map_Div->ctx = &rt_uDiv; } /* ... nor a signed mod instruction ... */ { - runtime_rt rt_Mod; i_instr_record *map_Mod = &records[n_records++].i_instr; tp = new_type_method(ID("rt_iMod"), 2, 1); @@ -652,25 +589,25 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); - rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp); - rt_Mod.mode = mode_T; - rt_Mod.res_mode = mode_Is; - rt_Mod.mem_proj_nr = pn_Mod_M; - rt_Mod.regular_proj_nr = pn_Mod_X_regular; - rt_Mod.exc_proj_nr = pn_Mod_X_except; - rt_Mod.exc_mem_proj_nr = pn_Mod_M; - rt_Mod.res_proj_nr = pn_Mod_res; + rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp); + set_entity_ld_ident(rt_iMod.ent, ID("__modsi3")); + rt_iMod.mode = mode_T; + rt_iMod.res_mode = mode_Is; + rt_iMod.mem_proj_nr = pn_Mod_M; + rt_iMod.regular_proj_nr = pn_Mod_X_regular; + rt_iMod.exc_proj_nr = pn_Mod_X_except; + rt_iMod.exc_mem_proj_nr = pn_Mod_M; + rt_iMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_Mod.ent, visibility_external_allocated); + set_entity_visibility(rt_iMod.ent, visibility_external_allocated); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Mod->ctx = &rt_Mod; + map_Mod->ctx = &rt_iMod; } /* ... nor an unsigned mod. */ { - runtime_rt rt_Mod; i_instr_record *map_Mod = &records[n_records++].i_instr; tp = new_type_method(ID("rt_uMod"), 2, 1); @@ -678,25 +615,26 @@ static void arm_handle_intrinsics(void) { set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); - rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp); - rt_Mod.mode = mode_T; - rt_Mod.res_mode = mode_Iu; - rt_Mod.mem_proj_nr = pn_Mod_M; - rt_Mod.regular_proj_nr = pn_Mod_X_regular; - rt_Mod.exc_proj_nr = pn_Mod_X_except; - rt_Mod.exc_mem_proj_nr = pn_Mod_M; - rt_Mod.res_proj_nr = pn_Mod_res; + rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp); + set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3")); + rt_uMod.mode = mode_T; + rt_uMod.res_mode = mode_Iu; + rt_uMod.mem_proj_nr = pn_Mod_M; + rt_uMod.regular_proj_nr = pn_Mod_X_regular; + rt_uMod.exc_proj_nr = pn_Mod_X_except; + rt_uMod.exc_mem_proj_nr = pn_Mod_M; + rt_uMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_Mod.ent, visibility_external_allocated); + set_entity_visibility(rt_uMod.ent, visibility_external_allocated); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall; - map_Mod->ctx = &rt_Mod; + map_Mod->ctx = &rt_uMod; } if (n_records > 0) - lower_intrinsics(records, n_records); + lower_intrinsics(records, n_records, /*part_block_used=*/0); } /***************************************************************** @@ -714,7 +652,9 @@ static arm_isa_t arm_isa_template = { &arm_isa_if, /* isa interface */ &arm_gp_regs[REG_SP], /* stack pointer */ &arm_gp_regs[REG_R11], /* base pointer */ + &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */ -1, /* stack direction */ + 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ 7, /* spill costs */ 5, /* reload costs */ @@ -722,31 +662,34 @@ static arm_isa_t arm_isa_template = { 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ NULL, /* current code generator */ - { NULL, }, /* emitter environment */ }; /** * Initializes the backend ISA and opens the output file. */ -static void *arm_init(FILE *file_handle) { +static arch_env_t *arm_init(FILE *file_handle) { static int inited = 0; arm_isa_t *isa; - if(inited) + if (inited) return NULL; - isa = xmalloc(sizeof(*isa)); + isa = XMALLOC(arm_isa_t); memcpy(isa, &arm_isa_template, sizeof(*isa)); - arm_register_init(isa); + arm_register_init(); isa->cg = NULL; - be_emit_init_env(&isa->emit, file_handle); + be_emit_init(file_handle); - arm_create_opcodes(); - arm_register_copy_attr_func(); + arm_create_opcodes(&arm_irn_ops); arm_handle_intrinsics(); + /* needed for the debug support */ + be_gas_emit_switch_section(GAS_SECTION_TEXT); + be_emit_cstring(".Ltext0:\n"); + be_emit_write_line(); + /* we mark referenced global entities, so we can only emit those which * are actually referenced. (Note: you mustn't use the type visited flag * elsewhere in the backend) @@ -754,7 +697,7 @@ static void *arm_init(FILE *file_handle) { inc_master_type_visited(); inited = 1; - return isa; + return &isa->arch_env; } @@ -765,9 +708,9 @@ static void *arm_init(FILE *file_handle) { static void arm_done(void *self) { arm_isa_t *isa = self; - be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_env.main_env, 1); - be_emit_destroy_env(&isa->emit); + be_emit_exit(); free(self); } @@ -778,19 +721,19 @@ static void arm_done(void *self) { * here to speed up register allocation (and makes dumps * smaller and more readable). */ -static int arm_get_n_reg_class(const void *self) { - const arm_isa_t *isa = self; - - /* ARGH! is called BEFORE transform */ - return 2; - return isa->cg->have_fp_insn ? 2 : 1; +static unsigned arm_get_n_reg_class(const void *self) { + (void) self; + return N_CLASSES; } /** * Return the register class with requested index. */ -static const arch_register_class_t *arm_get_reg_class(const void *self, int i) { - return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa]; +static const arch_register_class_t *arm_get_reg_class(const void *self, + unsigned i) { + (void) self; + assert(i < N_CLASSES); + return &arm_reg_classes[i]; } /** @@ -800,6 +743,7 @@ static const arch_register_class_t *arm_get_reg_class(const void *self, int i) { * @return A register class which can hold values of the given mode. */ const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) { + (void) self; if (mode_is_float(mode)) return &arm_reg_classes[CLASS_arm_fpa]; else @@ -809,13 +753,14 @@ const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const /** * Produces the type which sits between the stack args and the locals on the stack. * it will contain the return address and space to store the old base pointer. - * @return The Firm type modelling the ABI between type. + * @return The Firm type modeling the ABI between type. */ static ir_type *arm_get_between_type(void *self) { static ir_type *between_type = NULL; static ir_entity *old_bp_ent = NULL; + (void) self; - if(!between_type) { + if (between_type == NULL) { ir_entity *ret_addr_ent; ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P); @@ -836,144 +781,129 @@ static ir_type *arm_get_between_type(void *self) { typedef struct { be_abi_call_flags_bits_t flags; const arch_env_t *arch_env; - const arch_isa_t *isa; ir_graph *irg; } arm_abi_env_t; static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg) { - arm_abi_env_t *env = xmalloc(sizeof(env[0])); - be_abi_call_flags_t fl = be_abi_call_get_flags(call); + arm_abi_env_t *env = XMALLOC(arm_abi_env_t); + be_abi_call_flags_t fl = be_abi_call_get_flags(call); env->flags = fl.bits; env->irg = irg; env->arch_env = arch_env; - env->isa = arch_env->isa; return env; } -static void arm_abi_dont_save_regs(void *self, pset *s) -{ - arm_abi_env_t *env = self; - if (env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->bp); -} +/** + * Generate the routine prologue. + * + * @param self The callback object. + * @param mem A pointer to the mem node. Update this if you define new memory. + * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. + * @param stack_bias Points to the current stack bias, can be modified if needed. + * + * @return The register which shall be used as a stack frame base. + * + * All nodes which define registers in @p reg_map must keep @p reg_map current. + */ +static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) { + arm_abi_env_t *env = self; + ir_node *store; + ir_graph *irg; + ir_node *block; + arch_register_class_t *gp; + ir_node *fp, *ip, *lr, *pc; + ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp); + (void) stack_bias; -/** - * Build the ARM prolog - */ -static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) { - ir_node *keep, *store; - arm_abi_env_t *env = self; - ir_graph *irg = env->irg; - ir_node *block = get_irg_start_block(irg); -// ir_node *regs[16]; -// int n_regs = 0; - arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp]; - - ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]); - ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); - ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); -// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]); -// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]); -// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]); -// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]); - - if(env->flags.try_omit_fp) - return env->isa->sp; - - ip = be_new_Copy(gp, irg, block, sp ); - arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]); - be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); - -// if (r0) regs[n_regs++] = r0; -// if (r1) regs[n_regs++] = r1; -// if (r2) regs[n_regs++] = r2; -// if (r3) regs[n_regs++] = r3; -// sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp)); -// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0); -// arch_set_irn_register(env->arch_env, sp, env->isa->sp); - store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem); - // TODO - // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0); - // arch_set_irn_register(env->arch_env, store, env->isa->sp); - - sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr); - arch_set_irn_register(env->arch_env, sp, env->isa->sp); - *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M); - - keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip)); - be_node_set_reg_class(keep, 1, gp); - arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]); - be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); - - fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), - new_tarval_from_long(4, get_irn_mode(fp))); - // TODO... - //set_arm_req_out_all(fp, fp_req); - //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0); - arch_set_irn_register(env->arch_env, fp, env->isa->bp); - -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2); -// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3); - be_abi_reg_map_set(reg_map, env->isa->bp, fp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep); - be_abi_reg_map_set(reg_map, env->isa->sp, sp); + if (env->flags.try_omit_fp) + return env->arch_env->sp; + + fp = be_abi_reg_map_get(reg_map, env->arch_env->bp); + ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]); + lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); + pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); + + gp = &arm_reg_classes[CLASS_arm_gp]; + irg = env->irg; + block = get_irg_start_block(irg); + + /* mark bp register as ignore */ + be_set_constr_single_reg_out(get_Proj_pred(fp), + get_Proj_proj(fp), env->arch_env->bp, + arch_register_req_type_ignore); + + /* copy SP to IP (so we can spill it */ + ip = be_new_Copy(gp, block, sp); + be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0); + + /* spill stuff */ + store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem); + + sp = new_r_Proj(block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr); + arch_set_irn_register(sp, env->arch_env->sp); + *mem = new_r_Proj(block, store, mode_M, pn_arm_StoreStackM4Inc_M); + + /* frame pointer is ip-4 (because ip is our old sp value) */ + fp = new_bd_arm_Sub_i(NULL, block, ip, get_irn_mode(fp), 4); + arch_set_irn_register(fp, env->arch_env->bp); + + /* beware: we change the fp but the StoreStackM4Inc above wants the old + * fp value. We are not allowed to spill or anything in the prolog, so we + * have to enforce some order here. (scheduler/regalloc are too stupid + * to extract this order from register requirements) */ + add_irn_dep(fp, store); + + fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements + be_set_constr_single_reg_out(fp, 0, env->arch_env->bp, + arch_register_req_type_ignore); + arch_set_irn_register(fp, env->arch_env->bp); + + be_abi_reg_map_set(reg_map, env->arch_env->bp, fp); + be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip); + be_abi_reg_map_set(reg_map, env->arch_env->sp, sp); be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr); be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc); - return env->isa->bp; + return env->arch_env->bp; } +/** + * Builds the ARM epilogue + */ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) { arm_abi_env_t *env = self; - ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); + ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp); + ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp); ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); // TODO: Activate Omit fp in epilogue - if(env->flags.try_omit_fp) { - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK); - add_irn_dep(curr_sp, *mem); - - curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr)); - be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]); - arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]); - be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] ); - - curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr ); - arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]); - be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] ); - be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore); + if (env->flags.try_omit_fp) { + curr_sp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); + + curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], bl, curr_lr, curr_sp, get_irn_mode(curr_lr)); + be_set_constr_single_reg_out(curr_lr, 0, &arm_gp_regs[REG_LR], 0); + + curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], bl, curr_lr ); + be_set_constr_single_reg_out(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC], 0); } else { - ir_node *sub12_node; ir_node *load_node; - tarval *tv = new_tarval_from_long(12,mode_Iu); - sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv); - // FIXME - //set_arm_req_out_all(sub12_node, sub12_req); - arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp); - load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem ); - // FIXME - //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0); - //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1); - //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2); - curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0); - curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1); - curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2); - *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M); - arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp); - arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp); - arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]); + + load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem); + + curr_bp = new_r_Proj(bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0); + curr_sp = new_r_Proj(bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1); + curr_pc = new_r_Proj(bl, load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2); + *mem = new_r_Proj(bl, load_node, mode_M, pn_arm_LoadStackM3Epilogue_M); + arch_set_irn_register(curr_bp, env->arch_env->bp); + arch_set_irn_register(curr_sp, env->arch_env->sp); + arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]); } - be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp); - be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp); + be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp); + be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp); be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr); be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc); } @@ -982,7 +912,6 @@ static const be_abi_callbacks_t arm_abi_callbacks = { arm_abi_init, free, arm_get_between_type, - arm_abi_dont_save_regs, arm_abi_prologue, arm_abi_epilogue, }; @@ -999,53 +928,64 @@ void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi ir_mode *mode; int i; int n = get_method_n_params(method_type); - be_abi_call_flags_t flags = { - { - 0, /* store from left to right */ - 0, /* store arguments sequential */ - 1, /* try to omit the frame pointer */ - 1, /* the function can use any register as frame pointer */ - 1 /* a call can take the callee's address as an immediate */ - } - }; + be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi); + (void) self; + + /* set abi flags for calls */ + call_flags.bits.left_to_right = 0; + call_flags.bits.store_args_sequential = 0; + /* call_flags.bits.try_omit_fp don't change this we can handle both */ + call_flags.bits.fp_free = 0; + call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */ /* set stack parameter passing style */ - be_abi_call_set_flags(abi, flags, &arm_abi_callbacks); + be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks); for (i = 0; i < n; i++) { /* reg = get reg for param i; */ /* be_abi_call_param_reg(abi, i, reg); */ - if (i < 4) - + if (i < 4) { be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i)); - else - be_abi_call_param_stack(abi, i, 4, 0, 0); + } else { + tp = get_method_param_type(method_type, i); + mode = get_type_mode(tp); + be_abi_call_param_stack(abi, i, mode, 4, 0, 0); + } } - /* default: return value is in R0 resp. F0 */ - assert(get_method_n_ress(method_type) < 2); - if (get_method_n_ress(method_type) > 0) { + /* set return registers */ + n = get_method_n_ress(method_type); + + assert(n <= 2 && "more than two results not supported"); + + /* In case of 64bit returns, we will have two 32bit values */ + if (n == 2) { tp = get_method_res_type(method_type, 0); mode = get_type_mode(tp); - be_abi_call_res_reg(abi, 0, - mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]); - } -} + assert(!mode_is_float(mode) && "two FP results not supported"); -static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) { - return &arm_irn_ops; -} + tp = get_method_res_type(method_type, 1); + mode = get_type_mode(tp); -const arch_irn_handler_t arm_irn_handler = { - arm_get_irn_ops -}; + assert(!mode_is_float(mode) && "mixed INT, FP results not supported"); -const arch_irn_handler_t *arm_get_irn_handler(const void *self) { - return &arm_irn_handler; + be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]); + be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]); + } else if (n == 1) { + const arch_register_t *reg; + + tp = get_method_res_type(method_type, 0); + assert(is_atomic_type(tp)); + mode = get_type_mode(tp); + + reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]; + be_abi_call_res_reg(abi, 0, reg); + } } int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { + (void) block_env; if(!is_arm_irn(irn)) return -1; @@ -1056,6 +996,7 @@ int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { * Initializes the code generator interface. */ static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) { + (void) self; return &arm_code_gen_if; } @@ -1065,12 +1006,16 @@ list_sched_selector_t arm_sched_selector; * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded */ static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { - memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t)); + (void) self; + memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector)); + /* arm_sched_selector.exectime = arm_sched_exectime; */ arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule; return &arm_sched_selector; + } static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) { + (void) self; return NULL; } @@ -1078,53 +1023,123 @@ static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) * Returns the necessary byte alignment for storing a register of given class. */ static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { + (void) self; + (void) cls; /* ARM is a 32 bit CPU, no need for other alignment */ return 4; } static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) { + (void) self; + (void) irn; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented arm_get_allowed_execution_units()"); } static const be_machine_t *arm_get_machine(const void *self) { + (void) self; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented arm_get_machine()"); } /** * Return irp irgs in the desired order. */ static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) { + (void) self; + (void) irg_list; return NULL; } +/** + * Allows or disallows the creation of Psi nodes for the given Phi nodes. + * @return 1 if allowed, 0 otherwise + */ +static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { + ir_node *cmp, *cmp_a, *phi; + ir_mode *mode; + + + /* currently Psi support is not implemented */ + return 0; + +/* we don't want long long Psi */ +#define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32) + + if (get_irn_mode(sel) != mode_b) + return 0; + + cmp = get_Proj_pred(sel); + cmp_a = get_Cmp_left(cmp); + mode = get_irn_mode(cmp_a); + + if (IS_BAD_PSI_MODE(mode)) + return 0; + + /* check the Phi nodes */ + for (phi = phi_list; phi; phi = get_irn_link(phi)) { + ir_node *pred_i = get_irn_n(phi, i); + ir_node *pred_j = get_irn_n(phi, j); + ir_mode *mode_i = get_irn_mode(pred_i); + ir_mode *mode_j = get_irn_mode(pred_j); + + if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j)) + return 0; + } + +#undef IS_BAD_PSI_MODE + + return 1; +} + +static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c) +{ + /* asm not supported */ + (void) self; + (void) c; + return ASM_CONSTRAINT_FLAG_INVALID; +} + +static int arm_is_valid_clobber(const void *self, const char *clobber) +{ + (void) self; + (void) clobber; + return 0; +} + /** * Returns the libFirm configuration parameter for this backend. */ static const backend_params *arm_get_libfirm_params(void) { - static arch_dep_params_t ad = { - 1, /* allow subs */ - 1, /* Muls are fast enough on ARM but ... */ - 1, /* ... one shift would be possible better */ - 0, /* SMUL is needed, only in Arch M*/ - 0, /* UMUL is needed, only in Arch M */ - 32, /* SMUL & UMUL available for 32 bit */ + static const ir_settings_if_conv_t ifconv = { + 4, /* maxdepth, doesn't matter for Psi-conversion */ + arm_is_psi_allowed /* allows or disallows Psi creation for given selector */ + }; + static ir_settings_arch_dep_t ad = { + 1, /* allow subs */ + 1, /* Muls are fast enough on ARM but ... */ + 31, /* ... one shift would be possible better */ + NULL, /* no evaluator function */ + 0, /* SMUL is needed, only in Arch M */ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ }; static backend_params p = { 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - 0, /* no different calling conventions */ - NULL, /* no additional opcodes */ NULL, /* will be set later */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ - NULL, /* no if conversion settings */ + NULL, /* ifconv_info will be set below */ + NULL, /* float arithmetic mode (TODO) */ + 0, /* no trampoline support: size 0 */ + 0, /* no trampoline support: align 0 */ + NULL, /* no trampoline support: no trampoline builder */ + 4 /* alignment of stack parameter */ }; - p.dep_param = &ad; + p.dep_param = &ad; + p.if_conv_info = &ifconv; return &p; } @@ -1146,17 +1161,17 @@ static lc_opt_enum_int_var_t arch_fpu_var = { static const lc_opt_table_entry_t arm_options[] = { LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var), LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names), - { NULL } + LC_OPT_LAST }; const arch_isa_if_t arm_isa_if = { arm_init, arm_done, + NULL, /* handle_intrinsics */ arm_get_n_reg_class, arm_get_reg_class, arm_get_reg_class_for_mode, arm_get_call_abi, - arm_get_irn_handler, arm_get_code_generator_if, arm_get_list_sched_selector, arm_get_ilp_sched_selector, @@ -1165,6 +1180,9 @@ const arch_isa_if_t arm_isa_if = { arm_get_allowed_execution_units, arm_get_machine, arm_get_irg_list, + NULL, /* mark remat */ + arm_parse_asm_constraint, + arm_is_valid_clobber }; void be_init_arch_arm(void) @@ -1177,6 +1195,7 @@ void be_init_arch_arm(void) be_register_isa_if("arm", &arm_isa_if); arm_init_transform(); + arm_init_emitter(); } BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);