X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=2ba456b8f860373d5dff42375b9944e947c09886;hb=abba32f7ea7e0362d2fbbad9b18b39bbd5e2b57d;hp=13eda4056f16fb8d35e6d9f18ce72708b4d3e514;hpb=823d86c10d1196aeb5a1687defa9b15f927bc0df;p=libfirm

diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c
index 13eda4056..2ba456b8f 100644
--- a/ir/be/arm/bearch_arm.c
+++ b/ir/be/arm/bearch_arm.c
@@ -231,6 +231,10 @@ static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
 	return NULL;
 }
 
+static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
+	/* TODO: set the entity assigned to the frame */
+}
+
 /**
  * This function is called by the generic backend to correct offsets for
  * nodes accessing the stack.
@@ -239,6 +243,10 @@ static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
 	/* TODO: correct offset if irn accesses the stack */
 }
 
+static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+	return 0;
+}
+
 /* fill register allocator interface */
 
 static const arch_irn_ops_if_t arm_irn_ops_if = {
@@ -248,8 +256,13 @@ static const arch_irn_ops_if_t arm_irn_ops_if = {
 	arm_classify,
 	arm_get_flags,
 	arm_get_frame_entity,
+	arm_set_frame_entity,
 	arm_set_stack_bias,
-	NULL
+	arm_get_sp_bias,
+	NULL,    /* get_inverse             */
+	NULL,    /* get_op_estimated_cost   */
+	NULL,    /* possible_memory_operand */
+	NULL,    /* perform_memory_operand  */
 };
 
 arm_irn_ops_t arm_irn_ops = {
@@ -286,7 +299,7 @@ static void arm_prepare_graph(void *self) {
 /**
  * Called immediately before emit phase.
  */
-static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
+static void arm_finish_irg(void *self) {
 	/* TODO: - fix offsets for nodes accessing stack
 			 - ...
 	*/
@@ -319,7 +332,6 @@ static void arm_emit_and_done(void *self) {
 		cg->emit_decls = 0;
 	}
 
-	arm_finish_irg(irg, cg);
 	dump_ir_block_graph_sched(irg, "-arm-finished");
 	arm_gen_routine(out, irg, cg);
 
@@ -532,6 +544,7 @@ static const arch_code_generator_if_t arm_code_gen_if = {
 	arm_before_sched,   /* before scheduling hook */
 	arm_before_ra,      /* before register allocation hook */
 	NULL,               /* after register allocation */
+	arm_finish_irg,
 	arm_emit_and_done,
 };
 
@@ -583,7 +596,7 @@ static void *arm_cg_init(const be_irg_t *birg) {
  * and map all instructions the backend did not support
  * to runtime calls.
  */
-static void arm_global_init(void) {
+static void arm_handle_intrinsics(void) {
   ir_type *tp, *int_tp, *uint_tp;
   i_record records[8];
   int n_records = 0;
@@ -742,7 +755,7 @@ static void *arm_init(FILE *file_handle) {
 	isa->out = file_handle;
 
 	arm_create_opcodes();
-	arm_global_init();
+	arm_handle_intrinsics();
 	arm_switch_section(NULL, NO_SECTION);
 
 	inited = 1;
@@ -874,8 +887,8 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
 		return env->isa->sp;
 
 	ip = be_new_Copy(gp, irg, block, sp );
-		arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
-		be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+	arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
+	be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
 
 //	if (r0) regs[n_regs++] = r0;
 //	if (r1) regs[n_regs++] = r1;
@@ -928,7 +941,8 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
 
 //	TODO: Activate Omit fp in epilogue
 	if(env->flags.try_omit_fp) {
-		curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
+		curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
+		add_irn_dep(curr_sp, *mem);
 
 		curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
 		be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
@@ -1046,7 +1060,7 @@ list_sched_selector_t arm_sched_selector;
 /**
  * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
  */
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
 	memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
 	arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
 	return &arm_sched_selector;
@@ -1060,6 +1074,30 @@ static int arm_get_reg_class_alignment(const void *self, const arch_register_cla
 	return get_mode_size_bytes(mode);
 }
 
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *arm_get_libfirm_params(void) {
+	static arch_dep_params_t ad = {
+		1,  /* allow subs */
+		0,	/* Muls are fast enough on ARM */
+		31, /* shift would be ok */
+		0,  /* SMUL is needed, only in Arch M*/
+		0,  /* UMUL is needed, only in Arch M */
+		32, /* SMUL & UMUL available for 32 bit */
+	};
+	static backend_params p = {
+		NULL,  /* no additional opcodes */
+		NULL,  /* will be set later */
+		1,     /* need dword lowering */
+		NULL,  /* but yet no creator function */
+		NULL,  /* context for create_intrinsic_fkt */
+	};
+
+	p.dep_param = &ad;
+	return &p;
+}
+
 #ifdef WITH_LIBCORE
 
 /* fpu set architectures. */
@@ -1109,6 +1147,7 @@ const arch_isa_if_t arm_isa_if = {
 	arm_get_code_generator_if,
 	arm_get_list_sched_selector,
 	arm_get_reg_class_alignment,
+	arm_get_libfirm_params,
 #ifdef WITH_LIBCORE
 	arm_register_options
 #endif