X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_transform.c;h=ec1bcfde3a47bc042367d7d8c07a04b275302069;hb=ad7bf85c4c61ebcd417ce5ce81cbb314bac4b697;hp=a3eaac5880a9a1826c7fc9e7c53937a9ce06facb;hpb=5da0fab6d0c10e01c19ecf6fdc3cc83d982dc8a5;p=libfirm

diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c
index a3eaac588..ec1bcfde3 100644
--- a/ir/be/arm/arm_transform.c
+++ b/ir/be/arm/arm_transform.c
@@ -1,6 +1,28 @@
-/* The codegenrator (transform FIRM into arm FIRM */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
 
+/**
+ * @file
+ * @brief   The codegenerator (transform FIRM into arm FIRM)
+ * @author  Oliver Richter, Tobias Gneist, Michael Beck
+ * @version $Id$
+ */
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -16,12 +38,16 @@
 #include "dbginfo.h"
 #include "iropt_t.h"
 #include "debug.h"
+#include "error.h"
 
 #include "../benode_t.h"
+#include "../beirg_t.h"
+#include "../beutil.h"
+#include "../betranshlp.h"
 #include "bearch_arm_t.h"
 
 #include "arm_nodes_attr.h"
-#include "../arch/archop.h"     /* we need this for Min and Max nodes */
+#include "archop.h"
 #include "arm_transform.h"
 #include "arm_new_nodes.h"
 #include "arm_map_regs.h"
@@ -31,8 +57,10 @@
 #include <limits.h>
 
 
-extern ir_op *get_op_Mulh(void);
+/** hold the current code generator during transformation */
+static arm_code_gen_t *env_cg;
 
+extern ir_op *get_op_Mulh(void);
 
 
 /****************************************************************************************************
@@ -45,10 +73,8 @@ extern ir_op *get_op_Mulh(void);
  *
  ****************************************************************************************************/
 
-/** Execute ROL. */
-static unsigned do_rol(unsigned v, unsigned rol)
-{
-	return (v << rol) | (v >> (32 - rol));
+static INLINE int mode_needs_gp_reg(ir_mode *mode) {
+	return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
 }
 
 typedef struct vals_ {
@@ -57,6 +83,14 @@ typedef struct vals_ {
 	unsigned char shifts[4];
 } vals;
 
+/** Execute ROL. */
+static unsigned do_rol(unsigned v, unsigned rol) {
+	return (v << rol) | (v >> (32 - rol));
+}
+
+/**
+ * construct 8bit values and rot amounts for a value
+ */
 static void gen_vals_from_word(unsigned int value, vals *result)
 {
 	int initial = 0;
@@ -98,20 +132,36 @@ static void gen_vals_from_word(unsigned int value, vals *result)
 /**
  * Creates a arm_Const node.
  */
-static ir_node *create_const_node(arm_transform_env_t *env, long value) {
-    tarval *tv = new_tarval_from_long(value, mode_Iu);
-	return new_rd_arm_Mov_i(env->dbg, env->irg, env->block, env->mode, tv);
+static ir_node *create_const_node(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, long value) {
+	ir_mode *mode  = mode_Iu;
+	tarval   *tv   = new_tarval_from_long(value, mode);
+	ir_node *res;
+
+	if (mode_needs_gp_reg(mode))
+		mode = mode_Iu;
+	res = new_rd_arm_Mov_i(dbg, current_ir_graph, block, mode, tv);
+	/* ensure the const is schedules AFTER the barrier */
+	add_irn_dep(res, be_abi_get_start_barrier(abi));
+	return res;
 }
 
 /**
  * Creates a arm_Const_Neg node.
  */
-static ir_node *create_const_neg_node(arm_transform_env_t *env, long value) {
-    tarval *tv = new_tarval_from_long(value, mode_Iu);
-	return new_rd_arm_Mvn_i(env->dbg, env->irg, env->block, env->mode, tv);
+static ir_node *create_const_neg_node(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, long value) {
+	ir_mode *mode = mode_Iu;
+	tarval  *tv   = new_tarval_from_long(value, mode);
+	ir_node *res;
+
+	if (mode_needs_gp_reg(mode))
+		mode = mode_Iu;
+	res = new_rd_arm_Mvn_i(dbg, current_ir_graph, block, mode, tv);
+	add_irn_dep(res, be_abi_get_start_barrier(abi));
+	/* ensure the const is schedules AFTER the barrier */
+	return res;
 }
 
-#define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, env->irg, env->block, op1, op2, env->mode)
+#define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
 
 /**
  * Encodes an immediate with shifter operand
@@ -133,174 +183,159 @@ unsigned int arm_decode_imm_w_shift(tarval *tv) {
 /**
  * Creates a possible DAG for an constant.
  */
-static ir_node *create_const_graph_value(arm_transform_env_t *env, unsigned int value) {
+static ir_node *create_const_graph_value(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, unsigned int value) {
 	ir_node *result;
-	int negate = 0;
 	vals v, vn;
 	int cnt;
+	ir_mode *mode = mode_Iu;
 
 	gen_vals_from_word(value, &v);
 	gen_vals_from_word(~value, &vn);
 
 	if (vn.ops < v.ops) {
 		/* remove bits */
-		result = create_const_neg_node(env, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
+		result = create_const_neg_node(abi, dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
 
 		for (cnt = 1; cnt < vn.ops; ++cnt) {
-			tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
-			ir_node *bic_i_node = new_rd_arm_Bic_i(env->dbg, env->irg, env->block, result, env->mode, tv);
+			tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode);
+			ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
 			result = bic_i_node;
 		}
 	}
 	else {
 		/* add bits */
-		result = create_const_node(env, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
+		result = create_const_node(abi, dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
 
 		for (cnt = 1; cnt < v.ops; ++cnt) {
-			tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
-			ir_node *orr_i_node = new_rd_arm_Or_i(env->dbg, env->irg, env->block, result, env->mode, tv);
+			tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode);
+			ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
 			result = orr_i_node;
 		}
 	}
 	return result;
 }
 
-static ir_node *create_const_graph(arm_transform_env_t *env) {
-	int value = get_tarval_long(get_Const_tarval(env->irn));
-	return create_const_graph_value(env, value);
-}
-
-
+/**
+ * Create a DAG constructing a given Const.
+ *
+ * @param irn  a Firm const
+ */
+static ir_node *create_const_graph(be_abi_irg_t *abi, ir_node *irn, ir_node *block) {
+	tarval  *tv = get_Const_tarval(irn);
+	ir_mode *mode = get_tarval_mode(tv);
+	int     value;
 
-static ir_node *gen_Const(arm_transform_env_t *env) {
-	ir_node *result;
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
-	if (env->mode == mode_F) {
-		result = new_rd_arm_fConst(env->dbg, env->irg, env->block, env->mode);
-		get_arm_attr(result)->value = get_Const_tarval(env->irn);
-	} else if (env->mode == mode_D) {
-		result = new_rd_arm_fConst(env->dbg, env->irg, env->block, env->mode);
-		get_arm_attr(result)->value = get_Const_tarval(env->irn);
-	} else if (env->mode == mode_P) {
-		return env->irn;
-	} else {
-		result = create_const_graph(env);
+	if (mode_is_reference(mode)) {
+		/* ARM is 32bit, so we can safely convert a reference tarval into Iu */
+		assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
+		tv = tarval_convert_to(tv, mode_Iu);
 	}
-	return result;
+	value = get_tarval_long(tv);
+	return create_const_graph_value(abi, get_irn_dbg_info(irn), block, value);
 }
 
-static ir_node *gen_mask(arm_transform_env_t *env, ir_node *op, int result_bits) {
+/**
+ * Create an And that will mask all upper bits
+ */
+static ir_node *gen_zero_extension(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
 	unsigned mask_bits = (1 << result_bits) - 1;
-	ir_node *mask_node = create_const_graph_value(env, mask_bits);
-	return new_rd_arm_And(env->dbg, env->irg, env->block, op, mask_node, get_irn_mode(env->irn), ARM_SHF_NONE, NULL);
+	ir_node *mask_node = create_const_graph_value(abi, dbg, block, mask_bits);
+	return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, NULL);
 }
 
-static ir_node *gen_sign_extension(arm_transform_env_t *env, ir_node *op, int result_bits) {
+/**
+ * Generate code for a sign extension.
+ */
+static ir_node *gen_sign_extension(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
+	ir_graph *irg   = current_ir_graph;
 	int shift_width = 32 - result_bits;
-	ir_node *shift_const_node = create_const_graph_value(env, shift_width);
-	ir_node *lshift_node = new_rd_arm_Shl(env->dbg, env->irg, env->block, op, shift_const_node, get_irn_mode(op));
-	ir_node *rshift_node = new_rd_arm_Shrs(env->dbg, env->irg, env->block, lshift_node, shift_const_node, get_irn_mode(env->irn));
+	ir_node *shift_const_node = create_const_graph_value(abi, dbg, block, shift_width);
+	ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu);
+	ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu);
 	return rshift_node;
 }
 
 /**
  * Transforms a Conv node.
  *
- * @param env   The transformation environment
- * @return the created arm Conv node
+ * @return The created ia32 Conv node
  */
-static ir_node *gen_Conv(arm_transform_env_t *env) {
-	ir_node *op      = get_Conv_op(env->irn);
-	ir_mode *in_mode = get_irn_mode(op);
-	ir_mode *out_mode = env->mode;
-
-	assert( in_mode != mode_E && "");
-	assert( in_mode != mode_Ls && "");
-	assert( in_mode != mode_Lu && "");
-	assert( out_mode != mode_E && "");
-	assert( out_mode != mode_Ls && "");
-	assert( out_mode != mode_Lu && "");
-
-	if (in_mode == out_mode)
-		return op;
-
-	if ((mode_is_int(in_mode) || mode_is_reference(in_mode))
-		&& (mode_is_reference(out_mode) || mode_is_int(out_mode))) {
-		int in_bits = get_mode_size_bits(in_mode);
-		int out_bits = get_mode_size_bits(out_mode);
-		int in_sign = get_mode_sign(in_mode);
-		int out_sign = get_mode_sign(out_mode);
-
-		// 32 -> 32
-			// NOPpen
-		if (in_bits == out_bits && in_bits == 32)
-			return op;
-
-		// 16 -> 16
-			// unsigned -> unsigned
-				// NOP
-			// unsigned -> signed
-				// sign extension (31:16)=(15)
-			// signed -> unsigned
-				// maskieren (31:16)=0
-			// signed -> signed
-				// NOP
-		if (in_bits == out_bits && out_bits < 32) {
-			if (in_sign && !out_sign) {
-				return gen_mask(env, op, out_bits);
-			} else {
-				return gen_sign_extension(env, op, out_bits);
+static ir_node *gen_Conv(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *op       = get_Conv_op(node);
+	ir_node  *new_op   = be_transform_node(op);
+	ir_graph *irg      = current_ir_graph;
+	ir_mode  *src_mode = get_irn_mode(op);
+	ir_mode  *dst_mode = get_irn_mode(node);
+	dbg_info *dbg      = get_irn_dbg_info(node);
+
+	if (src_mode == dst_mode)
+		return new_op;
+
+	if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
+		env_cg->have_fp_insn = 1;
+
+		if (USE_FPA(env_cg->isa)) {
+			if (mode_is_float(src_mode)) {
+				if (mode_is_float(dst_mode)) {
+					/* from float to float */
+					return new_rd_arm_fpaMov(dbg, irg, block, new_op, dst_mode);
+				}
+				else {
+					/* from float to int */
+					return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode);
+				}
+			}
+			else {
+				/* from int to float */
+				return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode);
 			}
 		}
-
-		// 16 -> 32
-			// unsigned -> unsigned
-				// NOP
-			// unsigned -> signed
-				// NOP
-			// signed -> unsigned
-				// sign extension (31:16)=(15)
-			// signed -> signed
-				// sign extension (31:16)=(15)
-		if (in_bits < out_bits) {
-			if (in_sign) {
-				return gen_sign_extension(env, op, out_bits);
-			} else {
-				return op;
+		else if (USE_VFP(env_cg->isa)) {
+			panic("VFP not supported yet\n");
+			return NULL;
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+			return NULL;
+		}
+	}
+	else { /* complete in gp registers */
+		int src_bits = get_mode_size_bits(src_mode);
+		int dst_bits = get_mode_size_bits(dst_mode);
+		int min_bits;
+		ir_mode *min_mode;
+
+		if (is_Load(skip_Proj(op))) {
+			if (src_bits == dst_bits) {
+				/* kill unneccessary conv */
+				return new_op;
 			}
+			/* after a load, the bit size is already converted */
+			src_bits = 32;
 		}
 
-		// 32 -> 16
-			// unsigned -> unsigned
-				// maskieren (31:16)=0
-			// unsigned -> signed
-				// maskieren (31:16)=0
-			// signed -> unsigned
-				// maskieren (31:16)=0
-			// signed -> signed
-				// sign extension (erledigt auch maskieren) (31:16)=(15)
-		if (in_bits > out_bits) {
-			if (in_sign && out_sign) {
-				return gen_sign_extension(env, op, out_bits);
+		if (src_bits == dst_bits) {
+			/* kill unneccessary conv */
+			return new_op;
+		} else if (dst_bits <= 32 && src_bits <= 32) {
+			if (src_bits < dst_bits) {
+				min_bits = src_bits;
+				min_mode = src_mode;
 			} else {
-				return gen_mask(env, op, out_bits);
+				min_bits = dst_bits;
+				min_mode = dst_mode;
 			}
+			if (mode_is_signed(min_mode)) {
+				return gen_sign_extension(env_cg->birg->abi, dbg, block, new_op, min_bits);
+			} else {
+				return gen_zero_extension(env_cg->birg->abi, dbg, block, new_op, min_bits);
+			}
+		} else {
+			panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode,
+				src_bits, dst_bits);
+			return NULL;
 		}
-		assert(0 && "recheck integer conversion logic!");
-		return env->irn;
-	} else if (in_mode == mode_D && out_mode == mode_F) {
-		return new_rd_arm_fConvD2S(env->dbg, env->irg, env->block, op, env->mode);
-	} else if (in_mode == mode_F && out_mode == mode_D) {
-		return new_rd_arm_fConvS2D(env->dbg, env->irg, env->block, op, env->mode);
-	} else if (mode_is_int(in_mode) && mode_is_float(out_mode)) {
-		env->cg->have_fp = 1;
-		return env->irn; /* TODO: implement int->float conversion*/
-	} else if (mode_is_float(in_mode) && mode_is_int(out_mode)) {
-		env->cg->have_fp = 1;
-		return env->irn; /* TODO: implement float->int conversion*/
-	} else {
-		assert(0 && "not implemented conversion");
-		return env->irn;
 	}
 }
 
@@ -323,438 +358,554 @@ static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
 }
 
 /**
- * Creates an arm Add.
+ * Creates an ARM Add.
  *
- * @param env   The transformation environment
  * @return the created arm Add node
  */
-static ir_node *gen_Add(arm_transform_env_t *env) {
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Add_left(irn);
-	ir_node *op2 = get_Add_right(irn);
-	ir_node *op3;
+static ir_node *gen_Add(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Add_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Add_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = get_irn_mode(node);
+	ir_graph *irg     = current_ir_graph;
+	ir_node  *new_op3;
 	int v;
 	arm_shift_modifier mod;
+	dbg_info *dbg = get_irn_dbg_info(node);
 
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			return new_rd_arm_fpaAdd(dbg, irg, block, new_op1, new_op2, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+			return NULL;
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+			return NULL;
+		}
+	} else {
+		assert(mode_is_numP(mode));
+		mode = mode_Iu;
 
-	if (mode_is_float(env->mode)) {
-		env->cg->have_fp = 1;
-		return new_rd_arm_fAdd(env->dbg, env->irg, env->block, op1, op2, env->mode);
-	}
-	if (mode_is_numP(env->mode)) {
-		if (is_arm_Mov_i(op1))
-			return new_rd_arm_Add_i(env->dbg, env->irg, env->block, op2, env->mode,
-			                        get_arm_value(op1));
-		if (is_arm_Mov_i(op2))
-			return new_rd_arm_Add_i(env->dbg, env->irg, env->block, op1, env->mode,
-			                        get_arm_value(op2));
+		if (is_arm_Mov_i(new_op1))
+			return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1));
+		if (is_arm_Mov_i(new_op2))
+			return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2));
 
 		/* check for MLA */
-		if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
-			op3 = op2;
-			op2 = get_irn_n(op1, 1);
-			op1 = get_irn_n(op1, 0);
+		if (is_arm_Mul(new_op1) && get_irn_n_edges(new_op1) == 1) {
+			new_op3 = new_op2;
+			op2 = get_irn_n(new_op1, 1);
+			op1 = get_irn_n(new_op1, 0);
 
-			return new_rd_arm_Mla(env->dbg, env->irg, env->block, op1, op2, op3, env->mode);
+			return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
 		}
-		if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
-			op3 = op1;
-			op1 = get_irn_n(op2, 0);
-			op2 = get_irn_n(op2, 1);
+		if (is_arm_Mul(new_op2) && get_irn_n_edges(new_op2) == 1) {
+			new_op3 = new_op1;
+			new_op1 = get_irn_n(new_op2, 0);
+			new_op2 = get_irn_n(new_op2, 1);
 
-			return new_rd_arm_Mla(env->dbg, env->irg, env->block, op1, op2, op3, env->mode);
+			return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
 		}
 
 		/* is the first a shifter */
-		v = is_shifter_operand(op1, &mod);
+		v = is_shifter_operand(new_op1, &mod);
 		if (v) {
-			op1 = get_irn_n(op1, 0);
-			return new_rd_arm_Add(env->dbg, env->irg, env->block, op2, op1, env->mode,
-			                      mod, new_tarval_from_long(v, mode_Iu));
+			new_op1 = get_irn_n(new_op1, 0);
+			return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu));
 		}
 		/* is the second a shifter */
-		v = is_shifter_operand(op2, &mod);
+		v = is_shifter_operand(new_op2, &mod);
 		if (v) {
-			op2 = get_irn_n(op2, 0);
-			return new_rd_arm_Add(env->dbg, env->irg, env->block, op1, op2, env->mode,
-			                      mod, new_tarval_from_long(v, mode_Iu));
+			new_op2 = get_irn_n(new_op2, 0);
+			return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu));
 		}
 
 		/* normal ADD */
-		return new_rd_arm_Add(env->dbg, env->irg, env->block, op1, op2, env->mode, ARM_SHF_NONE, NULL);
+		return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL);
 	}
-
-	assert(0 && "unknown mode for add");
-	return NULL;
 }
 
 /**
- * Creates an arm Mul.
+ * Creates an ARM Mul.
  *
- * @param env   The transformation environment
  * @return the created arm Mul node
  */
-static ir_node *gen_Mul(arm_transform_env_t *env) {
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Mul_left(irn);
-	ir_node *op2 = get_Mul_right(irn);
-
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Mul(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Mul_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Mul_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = get_irn_mode(node);
+	ir_graph *irg     = current_ir_graph;
+	dbg_info *dbg     = get_irn_dbg_info(node);
 
-	if (mode_is_float(env->mode)) {
-		env->cg->have_fp = 1;
-		return new_rd_arm_fMul(env->dbg, env->irg, env->block, op1, op2, env->mode);
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			return new_rd_arm_fpaMul(dbg, irg, block, new_op1, new_op2, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+			return NULL;
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+			return NULL;
+		}
 	}
-	return new_rd_arm_Mul(env->dbg, env->irg, env->block, op1, op2, env->mode);
+	assert(mode_is_numP(mode));
+	mode = mode_Iu;
+	return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode);
 }
 
 /**
- * Creates an arm floating point Div.
+ * Creates an ARM floating point Div.
  *
  * @param env   The transformation environment
  * @return the created arm fDiv node
  */
-static ir_node *gen_Quot(arm_transform_env_t *env) {
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Quot_left(irn);
-	ir_node *op2 = get_Quot_right(irn);
-
-	assert(mode_is_float(get_irn_mode(op1)));
-	assert(get_irn_mode(op1) != mode_E && "IEEE Extended FP not supported");
-
-	return new_rd_arm_fDiv(env->dbg, env->irg, env->block, op1, op2, env->mode);
+static ir_node *gen_Quot(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Quot_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Quot_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = get_irn_mode(node);
+	dbg_info *dbg     = get_irn_dbg_info(node);
+
+	assert(mode != mode_E && "IEEE Extended FP not supported");
+
+	env_cg->have_fp_insn = 1;
+	if (USE_FPA(env_cg->isa))
+		return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, new_op1, new_op2, mode);
+	else if (USE_VFP(env_cg->isa)) {
+		assert(mode != mode_E && "IEEE Extended FP not supported");
+		panic("VFP not supported yet\n");
+	}
+	else {
+		panic("Softfloat not supported yet\n");
+		return NULL;
+	}
 }
 
 #define GEN_INT_OP(op) \
-static ir_node *gen_ ## op(arm_transform_env_t *env) { \
-	ir_node *irn = env->irn; \
-	ir_node *op1 = get_ ## op ## _left(irn); \
-	ir_node *op2 = get_ ## op ## _right(irn); \
-	int v; \
+	ir_node  *block   = be_transform_node(get_nodes_block(node)); \
+	ir_node  *op1     = get_ ## op ## _left(node); \
+	ir_node  *new_op1 = be_transform_node(op1); \
+	ir_node  *op2     = get_ ## op ## _right(node); \
+	ir_node  *new_op2 = be_transform_node(op2); \
+	ir_graph *irg     = current_ir_graph; \
+	ir_mode  *mode    = mode_Iu; \
+	dbg_info *dbg     = get_irn_dbg_info(node); \
+	int      v; \
 	arm_shift_modifier mod; \
  \
-	if (is_arm_Mov_i(op1)) \
-		return new_rd_arm_ ## op ## _i(env->dbg, env->irg, env->block, op2, env->mode, \
-		                        get_arm_value(op1)); \
-	if (is_arm_Mov_i(op2)) \
-		return new_rd_arm_ ## op ## _i(env->dbg, env->irg, env->block, op1, env->mode, \
-		                        get_arm_value(op2)); \
+	if (is_arm_Mov_i(new_op1)) \
+		return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); \
+	if (is_arm_Mov_i(new_op2)) \
+		return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); \
 	/* is the first a shifter */ \
-	v = is_shifter_operand(op1, &mod); \
+	v = is_shifter_operand(new_op1, &mod); \
 	if (v) { \
-		op1 = get_irn_n(op1, 0); \
-		return new_rd_arm_ ## op(env->dbg, env->irg, env->block, op2, op1, env->mode, \
-			                    mod, new_tarval_from_long(v, mode_Iu)); \
+		new_op1 = get_irn_n(new_op1, 0); \
+		return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
 	} \
 	/* is the second a shifter */ \
-	v = is_shifter_operand(op2, &mod); \
+	v = is_shifter_operand(new_op2, &mod); \
 	if (v) { \
-		op2 = get_irn_n(op2, 0); \
-		return new_rd_arm_ ## op(env->dbg, env->irg, env->block, op1, op2, env->mode, \
-			                    mod, new_tarval_from_long(v, mode_Iu)); \
+		new_op2 = get_irn_n(new_op2, 0); \
+		return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
 	} \
 	/* Normal op */ \
-	return new_rd_arm_ ## op(env->dbg, env->irg, env->block, op1, op2, env->mode, ARM_SHF_NONE, NULL); \
-}
-
+	return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL) \
 
 /**
- * Creates an arm And.
+ * Creates an ARM And.
  *
- * @param env   The transformation environment
  * @return the created arm And node
  */
-static ir_node *gen_And(arm_transform_env_t *env);
-GEN_INT_OP(And)
+static ir_node *gen_And(ir_node *node) {
+	GEN_INT_OP(And);
+}
 
 /**
- * Creates an arm Orr.
+ * Creates an ARM Orr.
  *
  * @param env   The transformation environment
  * @return the created arm Or node
  */
-static ir_node *gen_Or(arm_transform_env_t *env);
-GEN_INT_OP(Or)
+static ir_node *gen_Or(ir_node *node) {
+	GEN_INT_OP(Or);
+}
 
 /**
- * Creates an arm Eor.
+ * Creates an ARM Eor.
  *
- * @param env   The transformation environment
  * @return the created arm Eor node
  */
-static ir_node *gen_Eor(arm_transform_env_t *env);
-GEN_INT_OP(Eor)
+static ir_node *gen_Eor(ir_node *node) {
+	GEN_INT_OP(Eor);
+}
 
 /**
- * Creates an arm Sub.
+ * Creates an ARM Sub.
  *
- * @param env   The transformation environment
  * @return the created arm Sub node
  */
-static ir_node *gen_Sub(arm_transform_env_t *env) {
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Sub_left(irn);
-	ir_node *op2 = get_Sub_right(irn);
-	int v;
+static ir_node *gen_Sub(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Sub_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Sub_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = get_irn_mode(node);
+	ir_graph *irg     = current_ir_graph;
+	dbg_info *dbg     = get_irn_dbg_info(node);
+	int      v;
 	arm_shift_modifier mod;
 
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
-
-	if (mode_is_float(env->mode)) {
-		env->cg->have_fp = 1;
-		return new_rd_arm_fSub(env->dbg, env->irg, env->block, op1, op2, env->mode);
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			return new_rd_arm_fpaSub(dbg, irg, block, new_op1, new_op2, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+			return NULL;
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+			return NULL;
+		}
 	}
-	if (mode_is_numP(env->mode)) {
-		if (is_arm_Mov_i(op1))
-			return new_rd_arm_Rsb_i(env->dbg, env->irg, env->block, op2, env->mode,
-			                        get_arm_value(op1));
-		if (is_arm_Mov_i(op2))
-			return new_rd_arm_Sub_i(env->dbg, env->irg, env->block, op1, env->mode,
-			                        get_arm_value(op2));
+	else {
+		assert(mode_is_numP(mode) && "unknown mode for Sub");
+		mode = mode_Iu;
+
+		if (is_arm_Mov_i(new_op1))
+			return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1));
+		if (is_arm_Mov_i(new_op2))
+			return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2));
 
 		/* is the first a shifter */
-		v = is_shifter_operand(op1, &mod);
+		v = is_shifter_operand(new_op1, &mod);
 		if (v) {
-			op1 = get_irn_n(op1, 0);
-			return new_rd_arm_Rsb(env->dbg, env->irg, env->block, op2, op1, env->mode,
-			                      mod, new_tarval_from_long(v, mode_Iu));
+			new_op1 = get_irn_n(new_op1, 0);
+			return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu));
 		}
 		/* is the second a shifter */
-		v = is_shifter_operand(op2, &mod);
+		v = is_shifter_operand(new_op2, &mod);
 		if (v) {
-			op2 = get_irn_n(op2, 0);
-			return new_rd_arm_Sub(env->dbg, env->irg, env->block, op1, op2, env->mode,
-			                      mod, new_tarval_from_long(v, mode_Iu));
+			new_op2 = get_irn_n(new_op2, 0);
+			return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu));
 		}
 		/* normal sub */
-		return new_rd_arm_Sub(env->dbg, env->irg, env->block, op1, op2, env->mode, ARM_SHF_NONE, NULL);
+		return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL);
 	}
-	assert(0 && "unknown mode for sub");
-	return NULL;
 }
 
 /**
- * Creates an arm Shl.
+ * Creates an ARM Shl.
  *
- * @param env   The transformation environment
- * @return the created arm Shl node
+ * @return the created ARM Shl node
  */
-static ir_node *gen_Shl(arm_transform_env_t *env) {
-	ir_node *result;
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Shl_left(irn);
-	ir_node *op2 = get_Shl_right(irn);
-
-	if (is_arm_Mov_i(op2)) {
-		result = new_rd_arm_Mov(env->dbg, env->irg, env->block, op1, env->mode,
-		                        ARM_SHF_LSL, get_arm_value(op2));
-	} else {
-		result = new_rd_arm_Shl(env->dbg, env->irg, env->block, op1, op2, env->mode);
+static ir_node *gen_Shl(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Shl_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Shl_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = mode_Iu;
+	dbg_info *dbg     = get_irn_dbg_info(node);
+
+	if (is_arm_Mov_i(new_op2)) {
+		return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_value(new_op2));
 	}
-	return result;
+	return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode);
 }
 
 /**
- * Creates an arm Shr.
+ * Creates an ARM Shr.
  *
- * @param env   The transformation environment
- * @return the created arm Shr node
+ * @return the created ARM Shr node
  */
-static ir_node *gen_Shr(arm_transform_env_t *env) {
-	ir_node *result;
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Shr_left(irn);
-	ir_node *op2 = get_Shr_right(irn);
-
-	if (is_arm_Mov_i(op2)) {
-		result = new_rd_arm_Mov(env->dbg, env->irg, env->block, op1, env->mode,
-		                        ARM_SHF_LSR, get_arm_value(op2));
-	} else {
-		result = new_rd_arm_Shr(env->dbg, env->irg, env->block, op1, op2, env->mode);
+static ir_node *gen_Shr(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Shr_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Shr_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = mode_Iu;
+	dbg_info *dbg     = get_irn_dbg_info(node);
+
+	if (is_arm_Mov_i(new_op2)) {
+		return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_value(new_op2));
 	}
-	return result;
+	return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode);
 }
 
 /**
- * Creates an arm Shrs.
+ * Creates an ARM Shrs.
  *
- * @param env   The transformation environment
- * @return the created arm Shrs node
+ * @return the created ARM Shrs node
  */
-static ir_node *gen_Shrs(arm_transform_env_t *env) {
-	ir_node *result;
-	ir_node *irn = env->irn;
-	ir_node *op1 = get_Shrs_left(irn);
-	ir_node *op2 = get_Shrs_right(irn);
-
-	if (is_arm_Mov_i(op2)) {
-		result = new_rd_arm_Mov(env->dbg, env->irg, env->block, op1, env->mode,
-		                        ARM_SHF_ASR, get_arm_value(op2));
-	} else {
-		result = new_rd_arm_Shrs(env->dbg, env->irg, env->block, op1, op2, env->mode);
+static ir_node *gen_Shrs(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op1     = get_Shrs_left(node);
+	ir_node  *new_op1 = be_transform_node(op1);
+	ir_node  *op2     = get_Shrs_right(node);
+	ir_node  *new_op2 = be_transform_node(op2);
+	ir_mode  *mode    = mode_Iu;
+	dbg_info *dbg     = get_irn_dbg_info(node);
+
+	if (is_arm_Mov_i(new_op2)) {
+		return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_value(new_op2));
 	}
-	return result;
+	return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode);
 }
 
 /**
  * Transforms a Not node.
  *
- * @param env   The transformation environment
- * @return the created arm Not node
+ * @return the created ARM Not node
  */
-static ir_node *gen_Not(arm_transform_env_t *env) {
-	ir_node *op = get_Not_op(env->irn);
-	int v;
+static ir_node *gen_Not(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op      = get_Not_op(node);
+	ir_node  *new_op  = be_transform_node(op);
+	dbg_info *dbg     = get_irn_dbg_info(node);
+	tarval   *tv      = NULL;
+	ir_mode  *mode    = mode_Iu;
 	arm_shift_modifier mod = ARM_SHF_NONE;
-	tarval  *tv = NULL;
+	int      v        = is_shifter_operand(new_op, &mod);
 
-	v = is_shifter_operand(op, &mod);
 	if (v) {
-		op = get_irn_n(op, 0);
+		new_op = get_irn_n(new_op, 0);
 		tv = new_tarval_from_long(v, mode_Iu);
 	}
-	return new_rd_arm_Mvn(env->dbg, env->irg, env->block, op, env->mode, mod, tv);
+	return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, tv);
 }
 
 /**
  * Transforms an Abs node.
  *
  * @param env   The transformation environment
- * @return the created arm Abs node
+ * @return the created ARM Abs node
  */
-static ir_node *gen_Abs(arm_transform_env_t *env) {
-	ir_node *op = get_Abs_op(env->irn);
+static ir_node *gen_Abs(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op      = get_Abs_op(node);
+	ir_node  *new_op  = be_transform_node(op);
+	dbg_info *dbg     = get_irn_dbg_info(node);
+	ir_mode  *mode    = get_irn_mode(node);
 
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
-
-	if (mode_is_float(env->mode)) {
-		env->cg->have_fp = 1;
-		return new_rd_arm_fAbs(env->dbg, env->irg, env->block, op, env->mode);
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+		}
 	}
-
-	return new_rd_arm_Abs(env->dbg, env->irg, env->block, op, env->mode);
+	assert(mode_is_numP(mode));
+	mode = mode_Iu;
+	return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode);
 }
 
 /**
  * Transforms a Minus node.
  *
- * @param env   The transformation environment
- * @return the created arm Minus node
+ * @return the created ARM Minus node
  */
-static ir_node *gen_Minus(arm_transform_env_t *env) {
-	ir_node *op = get_Minus_op(env->irn);
+static ir_node *gen_Minus(ir_node *node) {
+	ir_node  *block   = be_transform_node(get_nodes_block(node));
+	ir_node  *op      = get_Minus_op(node);
+	ir_node  *new_op  = be_transform_node(op);
+	dbg_info *dbg     = get_irn_dbg_info(node);
+	ir_mode  *mode    = get_irn_mode(node);
 
-	if (mode_is_float(env->mode)) {
-		return new_rd_arm_fMinus(env->dbg, env->irg, env->block, op, env->mode);
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			return new_rd_arm_fpaMnv(dbg, current_ir_graph, block, op, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+		}
 	}
-	return new_rd_arm_Rsb_i(env->dbg, env->irg, env->block, op, env->mode, get_mode_null(env->mode));
+	assert(mode_is_numP(mode));
+	mode = mode_Iu;
+	return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, get_mode_null(mode));
 }
 
 /**
  * Transforms a Load.
  *
- * @param mod     the debug module
- * @param block   the block the new node should belong to
- * @param node    the ir Load node
- * @param mode    node mode
- * @return the created arm Load node
+ * @return the created ARM Load node
  */
-static ir_node *gen_Load(arm_transform_env_t *env) {
-	ir_node *node = env->irn;
-	ir_mode *mode = get_Load_mode(node);
+static ir_node *gen_Load(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *ptr      = get_Load_ptr(node);
+	ir_node  *new_ptr  = be_transform_node(ptr);
+	ir_node  *mem      = get_Load_mem(node);
+	ir_node  *new_mem  = be_transform_node(mem);
+	ir_mode  *mode     = get_Load_mode(node);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbg      = get_irn_dbg_info(node);
+	ir_node  *new_load = NULL;
 
 	if (mode_is_float(mode)) {
-		env->cg->have_fp = 1;
-		/* FIXME: set the load mode */
-		return new_rd_arm_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
-	}
-	if (mode == mode_Bu) {
-		return new_rd_arm_Loadb(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
-	}
-	if (mode == mode_Bs) {
-		return new_rd_arm_Loadbs(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
-	}
-	if (mode == mode_Hu) {
-		return new_rd_arm_Loadh(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+		}
 	}
-	if (mode == mode_Hs) {
-		return new_rd_arm_Loadhs(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
+	else {
+		assert(mode_is_numP(mode) && "unsupported mode for Load");
+
+		if (mode_is_signed(mode)) {
+			/* sign extended loads */
+			switch (get_mode_size_bits(mode)) {
+			case 8:
+				new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem);
+				break;
+			case 16:
+				new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem);
+				break;
+			case 32:
+				new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
+				break;
+			default:
+				panic("mode size not supported\n");
+			}
+		} else {
+			/* zero extended loads */
+			switch (get_mode_size_bits(mode)) {
+			case 8:
+				new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem);
+				break;
+			case 16:
+				new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem);
+				break;
+			case 32:
+				new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
+				break;
+			default:
+				panic("mode size not supported\n");
+			}
+		}
 	}
-	if (mode_is_reference(mode)) {
-		return new_rd_arm_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
+	set_irn_pinned(new_load, get_irn_pinned(node));
+
+	/* check for special case: the loaded value might not be used */
+	if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
+		/* add a result proj and a Keep to produce a pseudo use */
+		ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res);
+		be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
 	}
-	return new_rd_arm_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
+
+	return new_load;
 }
 
 /**
  * Transforms a Store.
  *
- * @param mod     the debug module
- * @param block   the block the new node should belong to
- * @param node    the ir Store node
- * @param mode    node mode
- * @return the created arm Store node
+ * @return the created ARM Store node
  */
-static ir_node *gen_Store(arm_transform_env_t *env) {
-	ir_node *node = env->irn;
-	ir_mode *mode = get_irn_mode(get_Store_value(node));
-	assert(env->mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Store(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *ptr      = get_Store_ptr(node);
+	ir_node  *new_ptr  = be_transform_node(ptr);
+	ir_node  *mem      = get_Store_mem(node);
+	ir_node  *new_mem  = be_transform_node(mem);
+	ir_node  *val      = get_Store_value(node);
+	ir_node  *new_val  = be_transform_node(val);
+	ir_mode  *mode     = get_irn_mode(val);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbg      = get_irn_dbg_info(node);
+	ir_node *new_store = NULL;
 
 	if (mode_is_float(mode)) {
-		env->cg->have_fp = 1;
-		/* FIXME: set the store mode */
-		return new_rd_arm_fStore(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
-	}
-	if (mode == mode_Bu) {
-		return new_rd_arm_Storeb(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
-	}
-	if (mode == mode_Bs) {
-		return new_rd_arm_Storebs(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
-	}
-	if (mode == mode_Hu) {
-		return new_rd_arm_Storeh(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
-	}
-	if (mode == mode_Hs) {
-		return new_rd_arm_Storehs(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa))
+			new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+		} else {
+			panic("Softfloat not supported yet\n");
+		}
+	} else {
+		assert(mode_is_numP(mode) && "unsupported mode for Store");
+		switch (get_mode_size_bits(mode)) {
+		case 8:
+			new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem);
+		case 16:
+			new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem);
+		default:
+			new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem);
+		}
 	}
-	return new_rd_arm_Store(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
+	set_irn_pinned(new_store, get_irn_pinned(node));
+	return new_store;
 }
 
-
-static ir_node *gen_Cond(arm_transform_env_t *env) {
-	ir_node *result   = NULL;
-	ir_node *selector = get_Cond_selector(env->irn);
-	ir_node *irn      = env->irn;
-
-	if ( get_irn_mode(selector) == mode_b ) {
-		//CondJmp
-		ir_node *proj_node = get_Cond_selector(irn);
-		ir_node *cmp_node = get_Proj_pred(proj_node);
-		ir_node *op1 = get_Cmp_left(cmp_node);
-		ir_node *op2 = get_Cmp_right(cmp_node);
-		result = new_rd_arm_CondJmp(env->dbg, env->irg, env->block, op1, op2, mode_T);
-		set_arm_proj_num(result, get_Proj_proj(proj_node));
+/**
+ * Transforms a Cond.
+ *
+ * @return the created ARM Cond node
+ */
+static ir_node *gen_Cond(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *selector = get_Cond_selector(node);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbg      = get_irn_dbg_info(node);
+	ir_mode  *mode     = get_irn_mode(selector);
+
+	if (mode == mode_b) {
+		/* CondJmp */
+		ir_node *cmp_node = get_Proj_pred(selector);
+		ir_node *op1      = get_Cmp_left(cmp_node);
+		ir_node *new_op1  = be_transform_node(op1);
+		ir_node *op2      = get_Cmp_right(cmp_node);
+		ir_node *new_op2  = be_transform_node(op2);
+
+		return new_rd_arm_CondJmp(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector));
 	} else {
-		//SwitchJmp
-		ir_node *op = get_irn_n(env->irn, 0);
+		/* SwitchJmp */
+		ir_node *new_op = be_transform_node(selector);
 		ir_node *const_graph;
 		ir_node *sub;
-		ir_node *const_node;
 
 		ir_node *proj;
 		const ir_edge_t *edge;
 		int min = INT_MAX;
 		int max = INT_MIN;
 		int translation;
-		int norm_max;
-		int norm_min;
 		int pn;
-		arm_transform_env_t const_env;
 		int n_projs;
-		ir_node **projs;
 
-		foreach_out_edge(irn, edge) {
+		foreach_out_edge(node, edge) {
 			proj = get_edge_src_irn(edge);
 			assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
 
@@ -764,14 +915,9 @@ static ir_node *gen_Cond(arm_transform_env_t *env) {
 			max = pn>max ? pn : max;
 		}
 		translation = min;
-		norm_max = max - translation;
-		norm_min = min - translation;
-
-		n_projs = norm_max + 1;
-		projs = xcalloc(n_projs , sizeof(ir_node*));
+		n_projs = max - translation + 1;
 
-
-		foreach_out_edge(irn, edge) {
+		foreach_out_edge(node, edge) {
 			proj = get_edge_src_irn(edge);
 			assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
 
@@ -780,17 +926,10 @@ static ir_node *gen_Cond(arm_transform_env_t *env) {
 		}
 
 
-		const_node = new_rd_Const(env->dbg, env->irg, env->block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
-		const_env = *env;
-		const_env.mode = mode_Is;
-		const_env.irn = const_node;
-		const_graph = gen_Const(&const_env);
-		sub = new_rd_arm_Sub(env->dbg, env->irg, env->block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
-		result = new_rd_arm_SwitchJmp(env->dbg, env->irg, env->block, sub, mode_T);
-		set_arm_n_projs(result, n_projs);
-		set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation);
+		const_graph = create_const_graph_value(env_cg->birg->abi, dbg, block, translation);
+		sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, NULL);
+		return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
 	}
-	return result;
 }
 
 /**
@@ -798,16 +937,17 @@ static ir_node *gen_Cond(arm_transform_env_t *env) {
  * @param symc  the SymConst
  * @return name of the SymConst
  */
-const char *get_sc_name(ir_node *symc) {
-	if (get_irn_opcode(symc) != iro_SymConst)
-		return "NONE";
+static ident *get_sc_ident(ir_node *symc) {
+	ir_entity *ent;
 
 	switch (get_SymConst_kind(symc)) {
 		case symconst_addr_name:
-			return get_id_str(get_SymConst_name(symc));
+			return get_SymConst_name(symc);
 
 		case symconst_addr_ent:
-			return get_entity_ld_name(get_SymConst_entity(symc));
+			ent = get_SymConst_entity(symc);
+			mark_entity_visited(ent);
+			return get_entity_ld_ident(ent);
 
 		default:
 			assert(0 && "Unsupported SymConst");
@@ -816,52 +956,81 @@ const char *get_sc_name(ir_node *symc) {
 	return NULL;
 }
 
-static ir_node *gen_SymConst(arm_transform_env_t *env) {
-	return new_rd_arm_SymConst(env->dbg, env->irg, env->block,
-	                           env->mode, get_sc_name(env->irn));
-}
-
+/**
+ * Transforms a Const node.
+ *
+ * @return The transformed ARM node.
+ */
+static ir_node *gen_Const(ir_node *node) {
+	ir_node  *block = be_transform_node(get_nodes_block(node));
+	ir_graph *irg = current_ir_graph;
+	ir_mode *mode = get_irn_mode(node);
+	dbg_info *dbg = get_irn_dbg_info(node);
 
+	if (mode_is_float(mode)) {
+		env_cg->have_fp_insn = 1;
+		if (USE_FPA(env_cg->isa)) {
+			node = new_rd_arm_fpaConst(dbg, irg, block, get_Const_tarval(node));
+			/* ensure the const is schedules AFTER the barrier */
+			add_irn_dep(node, be_abi_get_start_barrier(env_cg->birg->abi));
+			return node;
+		}
+		else if (USE_VFP(env_cg->isa)) {
+			assert(mode != mode_E && "IEEE Extended FP not supported");
+			panic("VFP not supported yet\n");
+		}
+		else {
+			panic("Softfloat not supported yet\n");
+		}
+	}
+	return create_const_graph(env_cg->birg->abi, node, block);
+}
 
 /**
- * Transforms a CopyB node.
+ * Transforms a SymConst node.
  *
- * @param env   The transformation environment
- * @return The transformed node.
+ * @return The transformed ARM node.
  */
-static ir_node *gen_CopyB(arm_transform_env_t *env) {
-	ir_node  *res   = NULL;
-	dbg_info *dbg   = env->dbg;
-	ir_graph *irg   = env->irg;
-	ir_mode  *mode  = env->mode;
-	ir_node  *block = env->block;
-	ir_node  *node  = env->irn;
-	ir_node  *src   = get_CopyB_src(node);
-	ir_node  *dst   = get_CopyB_dst(node);
-	ir_node  *mem   = get_CopyB_mem(node);
-	int       size  = get_type_size_bytes(get_CopyB_type(node));
-	ir_node *src_copy;
-	ir_node *dst_copy;
-
-	arm_transform_env_t const_env;
-	const_env.block    = block;
-	const_env.dbg      = dbg;
-	const_env.irg      = irg;
-	const_env.irn      = node;
-	DEBUG_ONLY(const_env.mod      = env->mod;)
-	const_env.mode     = mode_Iu;
-
-	src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
-	dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
-
- 	res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
-	set_arm_value(res, new_tarval_from_long(size, mode_Iu));
-
+static ir_node *gen_SymConst(ir_node *node) {
+	ir_node  *block = be_transform_node(get_nodes_block(node));
+	ir_mode  *mode  = mode_Iu;
+	dbg_info *dbg   = get_irn_dbg_info(node);
+	ir_node  *res;
+
+	res = new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_ident(node));
+	add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
+	/* ensure the const is schedules AFTER the barrier */
 	return res;
 }
 
-
-
+/**
+ * Transforms a CopyB node.
+ *
+ * @return The transformed ARM node.
+ */
+static ir_node *gen_CopyB(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *src      = get_CopyB_src(node);
+	ir_node  *new_src  = be_transform_node(src);
+	ir_node  *dst      = get_CopyB_dst(node);
+	ir_node  *new_dst  = be_transform_node(dst);
+	ir_node  *mem      = get_CopyB_mem(node);
+	ir_node  *new_mem  = be_transform_node(mem);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbg      = get_irn_dbg_info(node);
+	int      size      = get_type_size_bytes(get_CopyB_type(node));
+	ir_node  *src_copy;
+	ir_node  *dst_copy;
+
+	src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
+	dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
+
+ 	return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy,
+			new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
+			new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
+			new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
+			new_mem, new_tarval_from_long(size, mode_Iu));
+}
 
 
 /********************************************
@@ -883,23 +1052,23 @@ static ir_node *gen_CopyB(arm_transform_env_t *env) {
  * access must be done relative the the fist IncSP ...
  */
 static int get_sp_expand_offset(ir_node *inc_sp) {
-	unsigned offset    = be_get_IncSP_offset(inc_sp);
-	be_stack_dir_t dir = be_get_IncSP_direction(inc_sp);
+	int offset = be_get_IncSP_offset(inc_sp);
 
-	if (offset == BE_STACK_FRAME_SIZE)
+	if (offset == BE_STACK_FRAME_SIZE_EXPAND)
 		return 0;
-	return dir == be_stack_dir_expand ? (int)offset : -(int)offset;
+
+	return offset;
 }
 
-static ir_node *gen_StackParam(arm_transform_env_t *env) {
 #if 0
-	ir_node *new_op = NULL;
-	ir_node *node   = env->irn;
-	ir_node *noreg  = ia32_new_NoReg_gp(env->cg);
-	ir_node *mem    = new_rd_NoMem(env->irg);
-	ir_node *ptr    = get_irn_n(node, 0);
-	entity  *ent    = be_get_frame_entity(node);
-	ir_mode *mode   = env->mode;
+static ir_node *gen_StackParam(ir_node *irn) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node   *new_op = NULL;
+	ir_node   *noreg  = ia32_new_NoReg_gp(env->cg);
+	ir_node   *mem    = new_rd_NoMem(env->irg);
+	ir_node   *ptr    = get_irn_n(irn, 0);
+	ir_entity *ent    = be_get_frame_entity(irn);
+	ir_mode   *mode   = env->mode;
 
 //	/* If the StackParam has only one user ->     */
 //	/* put it in the Block where the user resides */
@@ -909,14 +1078,14 @@ static ir_node *gen_StackParam(arm_transform_env_t *env) {
 
 	if (mode_is_float(mode)) {
 		if (USE_SSE2(env->cg))
-			new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
 		else {
 			env->cg->used_x87 = 1;
-			new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
 		}
 	}
 	else {
-		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+		new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
 	}
 
 	set_ia32_frame_ent(new_op, ent);
@@ -929,56 +1098,56 @@ static ir_node *gen_StackParam(arm_transform_env_t *env) {
 
 	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
 
-	return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
-#endif
+	return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
 }
+#endif
 
 /**
- * Transforms a FrameAddr into an ia32 Add.
+ * Transforms a FrameAddr into an ARM Add.
  */
-static ir_node *gen_be_FrameAddr(arm_transform_env_t *env) {
-	ir_node *node   = env->irn;
-	entity  *ent    = be_get_frame_entity(node);
-	int     offset  = get_entity_offset_bytes(ent);
-	ir_node *op     = get_irn_n(node, 0);
-	ir_node *cnst;
+static ir_node *gen_be_FrameAddr(ir_node *node) {
+	ir_node   *block  = be_transform_node(get_nodes_block(node));
+	ir_entity *ent    = be_get_frame_entity(node);
+	int       offset  = get_entity_offset(ent);
+	ir_node   *op     = be_get_FrameAddr_frame(node);
+	ir_node   *new_op = be_transform_node(op);
+	dbg_info  *dbg    = get_irn_dbg_info(node);
+	ir_mode   *mode   = mode_Iu;
+	ir_node   *cnst;
 
 	if (be_is_IncSP(op)) {
 		/* BEWARE: we get an offset which is absolute from an offset that
 		   is relative. Both must be merged */
 		offset += get_sp_expand_offset(op);
 	}
-	cnst = create_const_graph_value(env, (unsigned)offset);
-	if (is_arm_Mov_i(cnst)) {
-		return new_rd_arm_Add_i(env->dbg, env->irg, env->block, op, env->mode,
-		                        get_arm_value(cnst));
-	}
-	return new_rd_arm_Add(env->dbg, env->irg, env->block, op, cnst, env->mode, ARM_SHF_NONE, NULL);
+	cnst = create_const_graph_value(env_cg->birg->abi, dbg, block, (unsigned)offset);
+	if (is_arm_Mov_i(cnst))
+		return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_value(cnst));
+	return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, NULL);
 }
 
+#if 0
 /**
- * Transforms a FrameLoad into an ia32 Load.
+ * Transforms a FrameLoad into an ARM Load.
  */
-static ir_node *gen_FrameLoad(arm_transform_env_t *env) {
-#if 0
-	ir_node *new_op = NULL;
-	ir_node *node   = env->irn;
-	ir_node *noreg  = ia32_new_NoReg_gp(env->cg);
-	ir_node *mem    = get_irn_n(node, 0);
-	ir_node *ptr    = get_irn_n(node, 1);
-	entity  *ent    = be_get_frame_entity(node);
-	ir_mode *mode   = get_type_mode(get_entity_type(ent));
+static ir_node *gen_FrameLoad(ir_node *irn) {
+	ir_node   *new_op = NULL;
+	ir_node   *noreg  = ia32_new_NoReg_gp(env->cg);
+	ir_node   *mem    = get_irn_n(irn, 0);
+	ir_node   *ptr    = get_irn_n(irn, 1);
+	ir_entity *ent    = be_get_frame_entity(irn);
+	ir_mode   *mode   = get_type_mode(get_entity_type(ent));
 
 	if (mode_is_float(mode)) {
 		if (USE_SSE2(env->cg))
-			new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
 		else {
 			env->cg->used_x87 = 1;
-			new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
 		}
 	}
 	else {
-		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+		new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
 	}
 
 	set_ia32_frame_ent(new_op, ent);
@@ -992,226 +1161,426 @@ static ir_node *gen_FrameLoad(arm_transform_env_t *env) {
 	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
 
 	return new_op;
+}
 #endif
+
+/**
+ * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
+ */
+static ir_node *gen_be_AddSP(ir_node *node) {
+	ir_node  *block  = be_transform_node(get_nodes_block(node));
+	ir_node  *sz     = get_irn_n(node, be_pos_AddSP_size);
+	ir_node  *new_sz = be_transform_node(sz);
+	ir_node  *sp     = get_irn_n(node, be_pos_AddSP_old_sp);
+	ir_node  *new_sp = be_transform_node(sp);
+	ir_graph *irg    = current_ir_graph;
+	dbg_info *dbgi   = get_irn_dbg_info(node);
+	ir_node  *nomem  = new_NoMem();
+	ir_node  *new_op;
+
+	/* ARM stack grows in reverse direction, make a SubSP */
+	new_op = new_rd_arm_SubSP(dbgi, irg, block, new_sp, new_sz, nomem);
+
+	return new_op;
 }
 
+/**
+ * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
+ */
+static ir_node *gen_be_SubSP(ir_node *node) {
+	ir_node  *block  = be_transform_node(get_nodes_block(node));
+	ir_node  *sz     = get_irn_n(node, be_pos_SubSP_size);
+	ir_node  *new_sz = be_transform_node(sz);
+	ir_node  *sp     = get_irn_n(node, be_pos_SubSP_old_sp);
+	ir_node  *new_sp = be_transform_node(sp);
+	ir_graph *irg    = current_ir_graph;
+	dbg_info *dbgi   = get_irn_dbg_info(node);
+	ir_node  *nomem  = new_NoMem();
+	ir_node  *new_op;
+
+	/* ARM stack grows in reverse direction, make an AddSP */
+	new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem);
+
+	return new_op;
+}
 
 /**
- * Transforms a FrameStore into an ia32 Store.
+ * Transform a be_Copy.
  */
-static ir_node *gen_FrameStore(arm_transform_env_t *env) {
-#if 0
-	ir_node *new_op = NULL;
-	ir_node *node   = env->irn;
-	ir_node *noreg  = ia32_new_NoReg_gp(env->cg);
-	ir_node *mem    = get_irn_n(node, 0);
-	ir_node *ptr    = get_irn_n(node, 1);
-	ir_node *val    = get_irn_n(node, 2);
-	entity  *ent    = be_get_frame_entity(node);
-	ir_mode *mode   = get_irn_mode(val);
+static ir_node *gen_be_Copy(ir_node *node) {
+	ir_node *result = be_duplicate_node(node);
+	ir_mode *mode   = get_irn_mode(result);
 
-	if (mode_is_float(mode)) {
-		if (USE_SSE2(env->cg))
-			new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
-		else {
-			env->cg->used_x87 = 1;
-			new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+	if (mode_needs_gp_reg(mode)) {
+		set_irn_mode(node, mode_Iu);
+	}
+
+	return result;
+}
+
+/**
+ * Transform a Proj from a Load.
+ */
+static ir_node *gen_Proj_Load(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *load     = get_Proj_pred(node);
+	ir_node  *new_load = be_transform_node(load);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbgi     = get_irn_dbg_info(node);
+	long     proj      = get_Proj_proj(node);
+
+	/* renumber the proj */
+	switch (get_arm_irn_opcode(new_load)) {
+	case iro_arm_Load:
+	case iro_arm_Loadb:
+	case iro_arm_Loadbs:
+	case iro_arm_Loadh:
+	case iro_arm_Loadhs:
+		/* handle all gp loads equal: they have the same proj numbers. */
+		if (proj == pn_Load_res) {
+			return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
+		} else if (proj == pn_Load_M) {
+			return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
+		}
+		break;
+	case iro_arm_fpaLdf:
+		if (proj == pn_Load_res) {
+			ir_mode *mode = get_Load_mode(load);
+			return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
+		} else if (proj == pn_Load_M) {
+			return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
 		}
+		break;
+	default:
+		break;
 	}
-	else if (get_mode_size_bits(mode) == 8) {
-		new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+	assert(0);
+	return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+/**
+ * Transform and renumber the Projs from a CopyB.
+ */
+static ir_node *gen_Proj_CopyB(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *pred     = get_Proj_pred(node);
+	ir_node  *new_pred = be_transform_node(pred);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbgi     = get_irn_dbg_info(node);
+	ir_mode  *mode     = get_irn_mode(node);
+	long     proj      = get_Proj_proj(node);
+
+	switch(proj) {
+	case pn_CopyB_M_regular:
+		if (is_arm_CopyB(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
+		}
+		break;
+	default:
+		break;
 	}
-	else {
-		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+	assert(0);
+	return new_rd_Unknown(irg, mode);
+}
+
+/**
+ * Transform and renumber the Projs from a Quot.
+ */
+static ir_node *gen_Proj_Quot(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *pred     = get_Proj_pred(node);
+	ir_node  *new_pred = be_transform_node(pred);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbgi     = get_irn_dbg_info(node);
+	ir_mode  *mode     = get_irn_mode(node);
+	long     proj      = get_Proj_proj(node);
+
+	switch (proj) {
+	case pn_Quot_M:
+		if (is_arm_fpaDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDiv_M);
+		} else if (is_arm_fpaRdv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdv_M);
+		} else if (is_arm_fpaFDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFDiv_M);
+		} else if (is_arm_fpaFRdv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFRdv_M);
+		}
+		break;
+	case pn_Quot_res:
+		if (is_arm_fpaDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDiv_res);
+		} else if (is_arm_fpaFDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdv_res);
+		} else if (is_arm_fpaFDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFDiv_res);
+		} else if (is_arm_fpaFDiv(new_pred)) {
+			return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFRdv_res);
+		}
+		break;
+	default:
+		break;
 	}
+	assert(0);
+	return new_rd_Unknown(irg, mode);
+}
 
-	set_ia32_frame_ent(new_op, ent);
-	set_ia32_use_frame(new_op);
+/**
+ * Transform the Projs of an AddSP.
+ */
+static ir_node *gen_Proj_be_AddSP(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *pred     = get_Proj_pred(node);
+	ir_node  *new_pred = be_transform_node(pred);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbgi     = get_irn_dbg_info(node);
+	long     proj      = get_Proj_proj(node);
+
+	if (proj == pn_be_AddSP_res) {
+		ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_arm_AddSP_stack);
+		arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
+		return res;
+	} else if (proj == pn_be_AddSP_M) {
+		return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
+	}
 
-	set_ia32_am_support(new_op, ia32_am_Dest);
-	set_ia32_op_type(new_op, ia32_AddrModeD);
-	set_ia32_am_flavour(new_op, ia32_B);
-	set_ia32_ls_mode(new_op, mode);
+	assert(0);
+	return new_rd_Unknown(irg, get_irn_mode(node));
+}
 
-	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+/**
+ * Transform the Projs of a SubSP.
+ */
+static ir_node *gen_Proj_be_SubSP(ir_node *node) {
+	ir_node  *block    = be_transform_node(get_nodes_block(node));
+	ir_node  *pred     = get_Proj_pred(node);
+	ir_node  *new_pred = be_transform_node(pred);
+	ir_graph *irg      = current_ir_graph;
+	dbg_info *dbgi     = get_irn_dbg_info(node);
+	long     proj      = get_Proj_proj(node);
+
+	if (proj == pn_be_SubSP_res) {
+		ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_arm_SubSP_stack);
+		arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
+		return res;
+	} else if (proj == pn_be_SubSP_M) {
+		return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSP_M);
+	}
 
-	return new_op;
-#endif
+	assert(0);
+	return new_rd_Unknown(irg, get_irn_mode(node));
 }
 
+/**
+ * Transform the Projs from a Cmp.
+ */
+static ir_node *gen_Proj_Cmp(ir_node *node) {
+	(void) node;
+	panic("Psi NYI\n");
+}
 
-// static ir_node *gen_be_Copy(arm_transform_env_t *env, ir_node *op) {
-// 	return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
-// }
-
-/*********************************************************
- *                  _             _      _
- *                 (_)           | |    (_)
- *  _ __ ___   __ _ _ _ __     __| |_ __ ___   _____ _ __
- * | '_ ` _ \ / _` | | '_ \   / _` | '__| \ \ / / _ \ '__|
- * | | | | | | (_| | | | | | | (_| | |  | |\ V /  __/ |
- * |_| |_| |_|\__,_|_|_| |_|  \__,_|_|  |_| \_/ \___|_|
- *
- *********************************************************/
 
-/************************************************************************/
-/* move constants out of startblock                                       */
-/************************************************************************/
-void arm_move_consts(ir_node *node, void *env) {
-	arm_code_gen_t *cgenv = (arm_code_gen_t *)env;
-	arm_transform_env_t tenv;
-	int i;
+/**
+ * Transform the Thread Local Storage Proj.
+ */
+static ir_node *gen_Proj_tls(ir_node *node) {
+	ir_node  *block = be_transform_node(get_nodes_block(node));
+	ir_graph *irg   = current_ir_graph;
+	dbg_info *dbgi  = NULL;
 
-	if (is_Block(node))
-		return;
+	return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu);
+}
 
-	tenv.irg = current_ir_graph;
-	DEBUG_ONLY(tenv.mod = cgenv->mod);
-
-	if (is_Phi(node)) {
-		for (i = 0; i < get_irn_arity(node); i++) {
-			ir_node *pred = get_irn_n(node,i);
-			opcode pred_code = get_irn_opcode(pred);
-			if (pred_code == iro_Const) {
-				ir_node *const_graph;
-				tenv.block    = get_nodes_block(get_irn_n(get_nodes_block(node),i));
-				tenv.dbg      = get_irn_dbg_info(pred);
-				tenv.irn      = pred;
-				tenv.mode     = get_irn_mode(pred);
-				const_graph = create_const_graph(&tenv);
-				set_irn_n(node, i, const_graph);
-			} else if (pred_code == iro_SymConst) {
-				const char *str = get_sc_name(pred);
-				ir_node *symconst_node;
-				symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
-					current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
-					get_irn_mode(pred), str);
-				set_irn_n(node, i, symconst_node);
-			}
+/**
+ * Transform a Proj node.
+ */
+static ir_node *gen_Proj(ir_node *node) {
+	ir_graph *irg  = current_ir_graph;
+	dbg_info *dbgi = get_irn_dbg_info(node);
+	ir_node  *pred = get_Proj_pred(node);
+	long     proj  = get_Proj_proj(node);
+
+	if (is_Store(pred) || be_is_FrameStore(pred)) {
+		if (proj == pn_Store_M) {
+			return be_transform_node(pred);
+		} else {
+			assert(0);
+			return new_r_Bad(irg);
 		}
-		return;
-	}
-	for (i = 0; i < get_irn_arity(node); i++) {
-		ir_node *pred = get_irn_n(node,i);
-		opcode pred_code = get_irn_opcode(pred);
-		if (pred_code == iro_Const) {
-			ir_node *const_graph;
-			tenv.block  = get_nodes_block(node);
-			tenv.dbg    = get_irn_dbg_info(pred);
-			tenv.irn    = pred;
-			tenv.mode   = get_irn_mode(pred);
-			const_graph = create_const_graph(&tenv);
-			set_irn_n(node, i, const_graph);
-		} else if (pred_code == iro_SymConst) {
-			const char *str = get_sc_name(pred);
-			ir_node *symconst_node;
-			symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
-				current_ir_graph, get_nodes_block(node),
-				get_irn_mode(pred), str);
-			set_irn_n(node, i, symconst_node);
+	} else if (is_Load(pred) || be_is_FrameLoad(pred)) {
+		return gen_Proj_Load(node);
+	} else if (is_CopyB(pred)) {
+		return gen_Proj_CopyB(node);
+	} else if (is_Quot(pred)) {
+		return gen_Proj_Quot(node);
+	} else if (be_is_SubSP(pred)) {
+		return gen_Proj_be_SubSP(node);
+	} else if (be_is_AddSP(pred)) {
+		return gen_Proj_be_AddSP(node);
+	} else if (is_Cmp(pred)) {
+		return gen_Proj_Cmp(node);
+	} else if (get_irn_op(pred) == op_Start) {
+		if (proj == pn_Start_X_initial_exec) {
+			ir_node *block = get_nodes_block(pred);
+			ir_node *jump;
+
+			/* we exchange the ProjX with a jump */
+			block = be_transform_node(block);
+			jump  = new_rd_Jmp(dbgi, irg, block);
+			ir_fprintf(stderr, "created jump: %+F\n", jump);
+			return jump;
+		}
+		if (node == be_get_old_anchor(anchor_tls)) {
+			return gen_Proj_tls(node);
+		}
+	} else {
+		ir_node *new_pred = be_transform_node(pred);
+		ir_mode *mode     = get_irn_mode(node);
+		if (mode_needs_gp_reg(mode)) {
+			ir_node *block    = be_transform_node(get_nodes_block(node));
+			ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
+			                               get_Proj_proj(node));
+#ifdef DEBUG_libfirm
+			new_proj->node_nr = node->node_nr;
+#endif
+			return new_proj;
 		}
 	}
-}
 
+	return be_duplicate_node(node);
+}
 
-/************************************************************************/
-/* move symbolic constants out of startblock                            */
-/************************************************************************/
-void arm_move_symconsts(ir_node *node, void *env) {
-	int i;
+/**
+ * This function just sets the register for the Unknown node
+ * as this is not done during register allocation because Unknown
+ * is an "ignore" node.
+ */
+static ir_node *gen_Unknown(ir_node *node) {
+	(void) node;
+	/*
+	ir_mode *mode = get_irn_mode(node);
+	if (mode_is_float(mode)) {
+		if (USE_FPA(env_cg->isa))
+			return arm_new_Unknown_fpa(env_cg);
+		else if (USE_VFP(env_cg->isa))
+			return arm_new_Unknown_vfp(env_cg);
+		else
+			panic("Softfloat not supported yet");
+	} else if (mode_needs_gp_reg(mode)) {
+		return ia32_new_Unknown_gp(env_cg);
+	} else {
+		assert(0 && "unsupported Unknown-Mode");
+	}
+*/
+	panic("Unknown NYI\n");
+	return NULL;
+}
 
-	if (is_Block(node))
-		return;
+/**
+ * Change some phi modes
+ */
+static ir_node *gen_Phi(ir_node *node) {
+	ir_node  *block = be_transform_node(get_nodes_block(node));
+	ir_graph *irg   = current_ir_graph;
+	dbg_info *dbgi  = get_irn_dbg_info(node);
+	ir_mode  *mode  = get_irn_mode(node);
+	ir_node  *phi;
+
+	if (mode_needs_gp_reg(mode)) {
+		/* we shouldn't have any 64bit stuff around anymore */
+		assert(get_mode_size_bits(mode) <= 32);
+		/* all integer operations are on 32bit registers now */
+		mode = mode_Iu;
+	}
 
-	for (i = 0; i < get_irn_arity(node); i++) {
-		ir_node *pred      = get_irn_n(node,i);
-		opcode   pred_code = get_irn_opcode(pred);
+	/* phi nodes allow loops, so we use the old arguments for now
+	 * and fix this later */
+	phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
+	copy_node_attr(node, phi);
+	be_duplicate_deps(node, phi);
 
-		if (pred_code == iro_SymConst) {
-			const char *str = get_sc_name(pred);
-			ir_node    *symconst_node;
+	be_set_transformed_node(node, phi);
+	be_enqueue_preds(node);
 
-			symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
-				current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str);
-			set_irn_n(node, i, symconst_node);
-		}
-	}
+	return phi;
 }
 
+/*********************************************************
+ *                  _             _      _
+ *                 (_)           | |    (_)
+ *  _ __ ___   __ _ _ _ __     __| |_ __ ___   _____ _ __
+ * | '_ ` _ \ / _` | | '_ \   / _` | '__| \ \ / / _ \ '__|
+ * | | | | | | (_| | | | | | | (_| | |  | |\ V /  __/ |
+ * |_| |_| |_|\__,_|_|_| |_|  \__,_|_|  |_| \_/ \___|_|
+ *
+ *********************************************************/
+
 /**
  * the BAD transformer.
  */
-static ir_node *bad_transform(arm_transform_env_t *env) {
-	ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
-	assert(0);
-	return NULL;
+static ir_node *bad_transform(ir_node *irn) {
+	panic("ARM backend: Not implemented: %+F\n", irn);
+	return irn;
+}
+
+/**
+ * Set a node emitter. Make it a bit more type safe.
+ */
+static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
+	op->ops.generic = (op_func)arm_transform_func;
 }
 
 /**
  * Enters all transform functions into the generic pointer
  */
-void arm_register_transformers(void) {
+static void arm_register_transformers(void) {
 	ir_op *op_Max, *op_Min, *op_Mulh;
 
 	/* first clear the generic function pointer for all ops */
 	clear_irp_opcodes_generic_func();
 
-#define FIRM_OP(a)     op_##a->ops.generic = (op_func)gen_##a
-#define BAD(a)         op_##a->ops.generic = (op_func)bad_transform
-#define IGN(a)
-
-	FIRM_OP(Add);  // done
-	FIRM_OP(Mul);  // done
-	FIRM_OP(Quot); // done
-	FIRM_OP(And);  // done
-	FIRM_OP(Or);   // done
-	FIRM_OP(Eor);  // done
-
-	FIRM_OP(Sub);  // done
-	FIRM_OP(Shl);  // done
-	FIRM_OP(Shr);  // done
-	FIRM_OP(Shrs); // done
+#define GEN(a)     set_transformer(op_##a, gen_##a)
+#define BAD(a)     set_transformer(op_##a, bad_transform)
 
-	FIRM_OP(Minus); // done
-	FIRM_OP(Not);   // done
-	FIRM_OP(Abs);   // done
+	GEN(Add);
+	GEN(Sub);
+	GEN(Mul);
+	GEN(And);
+	GEN(Or);
+	GEN(Eor);
 
-	FIRM_OP(CopyB); // done
-	FIRM_OP(Const); // TODO: floating point consts
-	FIRM_OP(Conv); // TODO: floating point conversions
+	GEN(Shl);
+	GEN(Shr);
+	GEN(Shrs);
+	BAD(Rot);	/* unsupported yet */
 
-	FIRM_OP(Load);   // done
-	FIRM_OP(Store);  // done
+	GEN(Quot);
 
-	FIRM_OP(SymConst);
-	FIRM_OP(Cond);	  // integer done
+	/* should be lowered */
+	BAD(Div);
+	BAD(Mod);
+	BAD(DivMod);
 
-	/* TODO: implement these nodes */
+	GEN(Minus);
+	GEN(Conv);
+	GEN(Abs);
+	GEN(Not);
 
-	IGN(Div);    // intrinsic lowering
-	IGN(Mod);    // intrinsic lowering
-	IGN(DivMod); // TODO: implement DivMod
+	GEN(Load);
+	GEN(Store);
+	GEN(Cond);
 
-	IGN(Mux);
-	IGN(Unknown);
-	IGN(Cmp);     // done, implemented in cond
+	BAD(ASM);	/* unsupported yet */
+	GEN(CopyB);
+	BAD(Mux);
+	BAD(Psi);	/* unsupported yet */
+	GEN(Proj);
+	GEN(Phi);
 
-	/* You probably don't need to handle the following nodes */
-
-	IGN(Call);
-	IGN(Proj);
-	IGN(Alloc);
-
-	IGN(Block);
-	IGN(Start);
-	IGN(End);
-	IGN(NoMem);
-	IGN(Phi);
-	IGN(IJmp);
-	IGN(Jmp);     // emitter done
-	IGN(Break);
-	IGN(Sync);
+	GEN(Const);
+	GEN(SymConst);
 
+	/* we should never see these nodes */
 	BAD(Raise);
 	BAD(Sel);
 	BAD(InstOf);
@@ -1219,69 +1588,58 @@ void arm_register_transformers(void) {
 	BAD(Free);
 	BAD(Tuple);
 	BAD(Id);
-	BAD(Bad);
+	//BAD(Bad);
 	BAD(Confirm);
 	BAD(Filter);
 	BAD(CallBegin);
 	BAD(EndReg);
 	BAD(EndExcept);
 
-	FIRM_OP(be_FrameAddr);
+	/* handle generic backend nodes */
+	GEN(be_FrameAddr);
+	//GEN(be_Call);
+	//GEN(be_Return);
+	BAD(be_FrameLoad);	/* unsupported yet */
+	BAD(be_FrameStore);	/* unsupported yet */
+	BAD(be_StackParam);	/* unsupported yet */
+	GEN(be_AddSP);
+	GEN(be_SubSP);
+	GEN(be_Copy);
+
+	/* set the register for all Unknown nodes */
+	GEN(Unknown);
 
 	op_Max = get_op_Max();
 	if (op_Max)
-		BAD(Max);
+		BAD(Max);	/* unsupported yet */
 	op_Min = get_op_Min();
 	if (op_Min)
-		BAD(Min);
+		BAD(Min);	/* unsupported yet */
 	op_Mulh = get_op_Mulh();
 	if (op_Mulh)
-		BAD(Mulh);
+		BAD(Mulh);	/* unsupported yet */
 
-#undef IGN
-#undef FIRM_OP
+#undef GEN
 #undef BAD
 }
 
-typedef ir_node *(transform_func)(arm_transform_env_t *env);
-
 /**
- * Transforms the given firm node (and maybe some other related nodes)
- * into one or more assembler nodes.
- *
- * @param node    the firm node
- * @param env     the debug module
+ * Pre-transform all unknown and noreg nodes.
  */
-void arm_transform_node(ir_node *node, void *env) {
-	arm_code_gen_t *cg = (arm_code_gen_t *)env;
-	ir_op *op          = get_irn_op(node);
-	ir_node *asm_node  = NULL;
-
-	if (op == op_Block)
-		return;
-
-	DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
-
-	if (op->ops.generic) {
-		arm_transform_env_t tenv;
-		transform_func *transform = (transform_func *)op->ops.generic;
-
-		tenv.cg       = cg;
-		tenv.block    = get_nodes_block(node);
-		tenv.dbg      = get_irn_dbg_info(node);
-		tenv.irg      = current_ir_graph;
-		tenv.irn      = node;
-		tenv.mode     = get_irn_mode(node);
-		DEBUG_ONLY(tenv.mod = cg->mod);
+static void arm_pretransform_node(void *arch_cg) {
+	arm_code_gen_t *cg = arch_cg;
+	(void) cg;
+}
 
-		asm_node = (*transform)(&tenv);
-	}
+/**
+ * Transform a Firm graph into an ARM graph.
+ */
+void arm_transform_graph(arm_code_gen_t *cg) {
+	arm_register_transformers();
+	env_cg = cg;
+	be_transform_graph(cg->birg, /*arm_pretransform_node*/ NULL, cg);
+}
 
-	if (asm_node) {
-		exchange(node, asm_node);
-		DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
-	}
-	else {
-		DB((cg->mod, LEVEL_1, "ignored\n"));
-	}
+void arm_init_transform(void) {
+	// FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");
 }