X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_transform.c;h=e231cc9fb41fd8e5c96036fdab9be4fa131451ad;hb=26e4122270acb4d7644f91b08b088fe64a864611;hp=e340c07930871d3b3dec1a6e9708eedcb93bdbf9;hpb=1a26f4853c07d1ecd68a097409dd602edfe29eff;p=libfirm diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c index e340c0793..e231cc9fb 100644 --- a/ir/be/arm/arm_transform.c +++ b/ir/be/arm/arm_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -20,8 +20,7 @@ /** * @file * @brief The codegenerator (transform FIRM into arm FIRM) - * @author Oliver Richter, Tobias Gneist, Michael Beck - * @version $Id$ + * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck */ #include "config.h" @@ -30,25 +29,28 @@ #include "irmode_t.h" #include "irgmod.h" #include "iredges.h" -#include "irvrfy.h" #include "ircons.h" #include "irprintf.h" #include "dbginfo.h" #include "iropt_t.h" #include "debug.h" #include "error.h" +#include "util.h" -#include "../benode.h" -#include "../beirg.h" -#include "../beutil.h" -#include "../betranshlp.h" -#include "bearch_arm_t.h" +#include "benode.h" +#include "beirg.h" +#include "beutil.h" +#include "betranshlp.h" +#include "beabihelper.h" +#include "beabi.h" +#include "bearch_arm_t.h" #include "arm_nodes_attr.h" #include "arm_transform.h" #include "arm_optimize.h" #include "arm_new_nodes.h" #include "arm_map_regs.h" +#include "arm_cconv.h" #include "gen_arm_regalloc_if.h" @@ -56,16 +58,52 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -/** hold the current code generator during transformation */ -static arm_code_gen_t *env_cg; - -static inline int mode_needs_gp_reg(ir_mode *mode) +static const arch_register_t *sp_reg = &arm_registers[REG_SP]; +static ir_mode *mode_gp; +static ir_mode *mode_fp; +static beabi_helper_env_t *abihelper; +static be_stackorder_t *stackorder; +static calling_convention_t *cconv = NULL; +static arm_isa_t *isa; + +static pmap *node_to_stack; + +static const arch_register_t *const callee_saves[] = { + &arm_registers[REG_R4], + &arm_registers[REG_R5], + &arm_registers[REG_R6], + &arm_registers[REG_R7], + &arm_registers[REG_R8], + &arm_registers[REG_R9], + &arm_registers[REG_R10], + &arm_registers[REG_R11], + &arm_registers[REG_LR], +}; + +static const arch_register_t *const caller_saves[] = { + &arm_registers[REG_R0], + &arm_registers[REG_R1], + &arm_registers[REG_R2], + &arm_registers[REG_R3], + &arm_registers[REG_LR], + + &arm_registers[REG_F0], + &arm_registers[REG_F1], + &arm_registers[REG_F2], + &arm_registers[REG_F3], + &arm_registers[REG_F4], + &arm_registers[REG_F5], + &arm_registers[REG_F6], + &arm_registers[REG_F7], +}; + +static bool mode_needs_gp_reg(ir_mode *mode) { return mode_is_int(mode) || mode_is_reference(mode); } /** - * Creates a possible DAG for an constant. + * create firm graph for a constant */ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, unsigned int value) @@ -74,13 +112,18 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, arm_vals v, vn; int cnt; + /* We only have 8 bit immediates. So we possibly have to combine several + * operations to construct the desired value. + * + * we can either create the value by adding bits to 0 or by removing bits + * from an register with all bits set. Try which alternative needs fewer + * operations */ arm_gen_vals_from_word(value, &v); arm_gen_vals_from_word(~value, &vn); if (vn.ops < v.ops) { /* remove bits */ result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]); - be_dep_on_frame(result); for (cnt = 1; cnt < vn.ops; ++cnt) { result = new_bd_arm_Bic_imm(dbgi, block, result, @@ -89,7 +132,6 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, } else { /* add bits */ result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]); - be_dep_on_frame(result); for (cnt = 1; cnt < v.ops; ++cnt) { result = new_bd_arm_Or_imm(dbgi, block, result, @@ -106,9 +148,9 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, */ static ir_node *create_const_graph(ir_node *irn, ir_node *block) { - tarval *tv = get_Const_tarval(irn); - ir_mode *mode = get_tarval_mode(tv); - unsigned value; + ir_tarval *tv = get_Const_tarval(irn); + ir_mode *mode = get_tarval_mode(tv); + unsigned value; if (mode_is_reference(mode)) { /* ARM is 32bit, so we can safely convert a reference tarval into Iu */ @@ -199,29 +241,27 @@ static ir_node *gen_Conv(ir_node *node) return new_op; if (mode_is_float(src_mode) || mode_is_float(dst_mode)) { - env_cg->have_fp_insn = 1; - - if (USE_FPA(env_cg->isa)) { + if (USE_FPA(isa)) { if (mode_is_float(src_mode)) { if (mode_is_float(dst_mode)) { /* from float to float */ - return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode); - } - else { + return new_bd_arm_Mvf(dbg, block, new_op, dst_mode); + } else { /* from float to int */ - return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode); + panic("TODO"); } - } - else { + } else { /* from int to float */ - return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode); + if (!mode_is_signed(src_mode)) { + panic("TODO"); + } else { + return new_bd_arm_FltX(dbg, block, new_op, dst_mode); + } } - } else if (USE_VFP(env_cg->isa)) { + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - return NULL; } else { panic("Softfloat not supported yet"); - return NULL; } } else { /* complete in gp registers */ int src_bits = get_mode_size_bits(src_mode); @@ -230,7 +270,7 @@ static ir_node *gen_Conv(ir_node *node) ir_mode *min_mode; if (src_bits == dst_bits) { - /* kill unneccessary conv */ + /* kill unnecessary conv */ return new_op; } @@ -306,19 +346,19 @@ static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res) return false; } -static int is_downconv(const ir_node *node) +static bool is_downconv(const ir_node *node) { ir_mode *src_mode; ir_mode *dest_mode; if (!is_Conv(node)) - return 0; + return false; /* we only want to skip the conv when we're the only user * (not optimal but for now...) */ if (get_irn_n_edges(node) > 1) - return 0; + return false; src_mode = get_irn_mode(get_Conv_op(node)); dest_mode = get_irn_mode(node); @@ -337,15 +377,29 @@ static ir_node *arm_skip_downconv(ir_node *node) typedef enum { MATCH_NONE = 0, - MATCH_COMMUTATIVE = 1 << 0, - MATCH_SIZE_NEUTRAL = 1 << 1, + MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */ + MATCH_REVERSE = 1 << 1, /**< support reverse opcode */ + MATCH_SIZE_NEUTRAL = 1 << 2, + MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */ } match_flags_t; +ENUM_BITSET(match_flags_t) -typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2); -typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot); +/** + * possible binop constructors. + */ +typedef struct arm_binop_factory_t { + /** normal reg op reg operation. */ + ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2); + /** normal reg op imm operation. */ + ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot); + /** barrel shifter reg op (reg shift reg operation. */ + ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier); + /** barrel shifter reg op (reg shift imm operation. */ + ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate); +} arm_binop_factory_t; static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, - new_binop_reg_func new_reg, new_binop_imm_func new_imm) + const arm_binop_factory_t *factory) { ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_binop_left(node); @@ -355,6 +409,14 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, dbg_info *dbgi = get_irn_dbg_info(node); arm_immediate_t imm; + if (flags & MATCH_SKIP_NOT) { + if (is_Not(op1)) + op1 = get_Not_op(op1); + else if (is_Not(op2)) + op2 = get_Not_op(op2); + else + panic("cannot execute MATCH_SKIP_NOT"); + } if (flags & MATCH_SIZE_NEUTRAL) { op1 = arm_skip_downconv(op1); op2 = arm_skip_downconv(op2); @@ -363,16 +425,92 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, } if (try_encode_as_immediate(op2, &imm)) { - ir_node *new_op1 = be_transform_node(op1); - return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot); + new_op1 = be_transform_node(op1); + return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot); } new_op2 = be_transform_node(op2); - if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) { - return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); + if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) { + if (flags & MATCH_REVERSE) + return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); + else + return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); } new_op1 = be_transform_node(op1); - return new_reg(dbgi, block, new_op1, new_op2); + /* check if we can fold in a Mov */ + if (is_arm_Mov(new_op2)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2); + + switch (attr->shift_modifier) { + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + if (factory->new_binop_reg_shift_imm) { + ir_node *mov_op = get_irn_n(new_op2, 0); + return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op, + attr->shift_modifier, attr->shift_immediate); + } + break; + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + if (factory->new_binop_reg_shift_reg) { + ir_node *mov_op = get_irn_n(new_op2, 0); + ir_node *mov_sft = get_irn_n(new_op2, 1); + return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft, + attr->shift_modifier); + } + break; + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); + } + } + if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1); + int idx = flags & MATCH_REVERSE ? 1 : 0; + + switch (attr->shift_modifier) { + ir_node *mov_op, *mov_sft; + + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + if (factory[idx].new_binop_reg_shift_imm) { + mov_op = get_irn_n(new_op1, 0); + return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op, + attr->shift_modifier, attr->shift_immediate); + } + break; + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + if (factory[idx].new_binop_reg_shift_reg) { + mov_op = get_irn_n(new_op1, 0); + mov_sft = get_irn_n(new_op1, 1); + return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft, + attr->shift_modifier); + } + break; + + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); + } + } + return factory->new_binop_reg(dbgi, block, new_op1, new_op2); } /** @@ -382,7 +520,14 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, */ static ir_node *gen_Add(ir_node *node) { - ir_mode *mode = get_irn_mode(node); + static const arm_binop_factory_t add_factory = { + new_bd_arm_Add_reg, + new_bd_arm_Add_imm, + new_bd_arm_Add_reg_shift_reg, + new_bd_arm_Add_reg_shift_imm + }; + + ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -391,23 +536,12 @@ static ir_node *gen_Add(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_op1 = be_transform_node(op1); ir_node *new_op2 = be_transform_node(op2); - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_fpaMvf_i(new_op1)) - return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_fpaMvf_i(new_op2)) - return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - return NULL; - } - else { + } else { panic("Softfloat not supported yet"); - return NULL; } } else { #if 0 @@ -428,8 +562,7 @@ static ir_node *gen_Add(ir_node *node) } #endif - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Add_reg, new_bd_arm_Add_imm); + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory); } } @@ -449,108 +582,108 @@ static ir_node *gen_Mul(ir_node *node) dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode); - } - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - return NULL; - } - else { + } else { panic("Softfloat not supported yet"); - return NULL; } } assert(mode_is_data(mode)); return new_bd_arm_Mul(dbg, block, new_op1, new_op2); } -/** - * Creates an ARM floating point Div. - * - * @param env The transformation environment - * @return the created arm fDiv node - */ -static ir_node *gen_Quot(ir_node *node) +static ir_node *gen_Div(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Quot_left(node); + ir_node *op1 = get_Div_left(node); ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Quot_right(node); + ir_node *op2 = get_Div_right(node); ir_node *new_op2 = be_transform_node(op2); - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_Div_resmode(node); dbg_info *dbg = get_irn_dbg_info(node); - assert(mode != mode_E && "IEEE Extended FP not supported"); + /* integer division should be replaced by builtin call */ + assert(mode_is_float(mode)); - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - } - else { + } else { panic("Softfloat not supported yet"); - return NULL; } } -/** - * Creates an ARM And. - * - * @return the created arm And node - */ static ir_node *gen_And(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_And_reg, new_bd_arm_And_imm); + static const arm_binop_factory_t and_factory = { + new_bd_arm_And_reg, + new_bd_arm_And_imm, + new_bd_arm_And_reg_shift_reg, + new_bd_arm_And_reg_shift_imm + }; + static const arm_binop_factory_t bic_factory = { + new_bd_arm_Bic_reg, + new_bd_arm_Bic_imm, + new_bd_arm_Bic_reg_shift_reg, + new_bd_arm_Bic_reg_shift_imm + }; + + /* check for and not */ + ir_node *left = get_And_left(node); + ir_node *right = get_And_right(node); + + if (is_Not(left) || is_Not(right)) { + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT, + &bic_factory); + } + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory); } -/** - * Creates an ARM Orr. - * - * @param env The transformation environment - * @return the created arm Or node - */ static ir_node *gen_Or(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Or_reg, new_bd_arm_Or_imm); + static const arm_binop_factory_t or_factory = { + new_bd_arm_Or_reg, + new_bd_arm_Or_imm, + new_bd_arm_Or_reg_shift_reg, + new_bd_arm_Or_reg_shift_imm + }; + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory); } -/** - * Creates an ARM Eor. - * - * @return the created arm Eor node - */ static ir_node *gen_Eor(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Eor_reg, new_bd_arm_Eor_imm); + static const arm_binop_factory_t eor_factory = { + new_bd_arm_Eor_reg, + new_bd_arm_Eor_imm, + new_bd_arm_Eor_reg_shift_reg, + new_bd_arm_Eor_reg_shift_imm + }; + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory); } -/** - * Creates an ARM Sub. - * - * @return the created arm Sub node - */ static ir_node *gen_Sub(ir_node *node) { + static const arm_binop_factory_t sub_rsb_factory[2] = { + { + new_bd_arm_Sub_reg, + new_bd_arm_Sub_imm, + new_bd_arm_Sub_reg_shift_reg, + new_bd_arm_Sub_reg_shift_imm + }, + { + new_bd_arm_Rsb_reg, + new_bd_arm_Rsb_imm, + new_bd_arm_Rsb_reg_shift_reg, + new_bd_arm_Rsb_reg_shift_imm + } + }; + ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_Sub_left(node); ir_node *new_op1 = be_transform_node(op1); @@ -560,83 +693,96 @@ static ir_node *gen_Sub(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - return NULL; } else { panic("Softfloat not supported yet"); - return NULL; } } else { - return gen_int_binop(node, MATCH_SIZE_NEUTRAL, - new_bd_arm_Sub_reg, new_bd_arm_Sub_imm); + return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory); } } +/** + * Checks if a given value can be used as an immediate for the given + * ARM shift mode. + */ +static bool can_use_shift_constant(unsigned int val, + arm_shift_modifier_t modifier) +{ + if (val <= 31) + return true; + if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG) + return true; + return false; +} + +/** + * generate an ARM shift instruction. + * + * @param node the node + * @param flags matching flags + * @param shift_modifier initial encoding of the desired shift operation + */ static ir_node *make_shift(ir_node *node, match_flags_t flags, - arm_shift_modifier shift_modifier) + arm_shift_modifier_t shift_modifier) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_binop_left(node); - ir_node *op2 = get_binop_right(node); - dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_binop_left(node); + ir_node *op2 = get_binop_right(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); ir_node *new_op1; ir_node *new_op2; + if (get_mode_modulo_shift(mode) != 32) + panic("modulo shift!=32 not supported"); + if (flags & MATCH_SIZE_NEUTRAL) { op1 = arm_skip_downconv(op1); op2 = arm_skip_downconv(op2); } + new_op1 = be_transform_node(op1); + if (is_Const(op2)) { + ir_tarval *tv = get_Const_tarval(op2); + unsigned int val = get_tarval_long(tv); + assert(tarval_is_long(tv)); + if (can_use_shift_constant(val, shift_modifier)) { + switch (shift_modifier) { + case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break; + case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break; + case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break; + case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break; + default: panic("unexpected shift modifier"); + } + return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, + shift_modifier, val); + } + } + new_op2 = be_transform_node(op2); - return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, shift_modifier); + return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, + shift_modifier); } -/** - * Creates an ARM Shl. - * - * @return the created ARM Shl node - */ static ir_node *gen_Shl(ir_node *node) { return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG); } -/** - * Creates an ARM Shr. - * - * @return the created ARM Shr node - */ static ir_node *gen_Shr(ir_node *node) { return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG); } -/** - * Creates an ARM Shrs. - * - * @return the created ARM Shrs node - */ static ir_node *gen_Shrs(ir_node *node) { return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG); } -/** - * Creates an ARM Ror. - * - * @return the created ARM Ror node - */ static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -648,13 +794,6 @@ static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) ARM_SHF_ROR_REG); } -/** - * Creates an ARM Rol. - * - * @return the created ARM Rol node - * - * Note: there is no Rol on arm, we have to use Ror - */ static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -662,16 +801,12 @@ static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_op2 = be_transform_node(op2); + /* Note: there is no Rol on arm, we have to use Ror */ new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0); return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, ARM_SHF_ROR_REG); } -/** - * Creates an ARM ROR from a Firm Rotl. - * - * @return the created ARM Ror node - */ static ir_node *gen_Rotl(ir_node *node) { ir_node *rotate = NULL; @@ -685,10 +820,10 @@ static ir_node *gen_Rotl(ir_node *node) if (is_Add(op2)) { ir_node *right = get_Add_right(op2); if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); - ir_node *left = get_Add_left(op2); + ir_tarval *tv = get_Const_tarval(right); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *left = get_Add_left(op2); if (is_Minus(left) && tarval_is_long(tv) && @@ -699,10 +834,10 @@ static ir_node *gen_Rotl(ir_node *node) } else if (is_Sub(op2)) { ir_node *left = get_Sub_left(op2); if (is_Const(left)) { - tarval *tv = get_Const_tarval(left); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); - ir_node *right = get_Sub_right(op2); + ir_tarval *tv = get_Const_tarval(left); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *right = get_Sub_right(op2); if (tarval_is_long(tv) && get_tarval_long(tv) == bits && @@ -710,9 +845,9 @@ static ir_node *gen_Rotl(ir_node *node) rotate = gen_Ror(node, op1, right); } } else if (is_Const(op2)) { - tarval *tv = get_Const_tarval(op2); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); + ir_tarval *tv = get_Const_tarval(op2); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); if (tarval_is_long(tv) && bits == 32) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -731,11 +866,6 @@ static ir_node *gen_Rotl(ir_node *node) return rotate; } -/** - * Transforms a Not node. - * - * @return the created ARM Not node - */ static ir_node *gen_Not(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -743,46 +873,42 @@ static ir_node *gen_Not(ir_node *node) ir_node *new_op = be_transform_node(op); dbg_info *dbgi = get_irn_dbg_info(node); - /* TODO: we could do alot more here with all the Mvn variations */ - - return new_bd_arm_Mvn_reg(dbgi, block, new_op); -} - -/** - * Transforms an Abs node. - * - * @param env The transformation environment - * @return the created ARM Abs node - */ -static ir_node *gen_Abs(ir_node *node) -{ - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Abs_op(node); - ir_node *new_op = be_transform_node(op); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - - if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) - return new_bd_arm_fpaAbs(dbgi, block, new_op, mode); - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet"); - } - else { - panic("Softfloat not supported yet"); + /* check if we can fold in a Mov */ + if (is_arm_Mov(new_op)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op); + + switch (attr->shift_modifier) { + ir_node *mov_op, *mov_sft; + + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + mov_op = get_irn_n(new_op, 0); + return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op, + attr->shift_modifier, attr->shift_immediate); + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + mov_op = get_irn_n(new_op, 0); + mov_sft = get_irn_n(new_op, 1); + return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft, + attr->shift_modifier); + + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); } } - assert(mode_is_data(mode)); - return new_bd_arm_Abs(dbgi, block, new_op); + + return new_bd_arm_Mvn_reg(dbgi, block, new_op); } -/** - * Transforms a Minus node. - * - * @return the created ARM Minus node - */ static ir_node *gen_Minus(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -792,14 +918,11 @@ static ir_node *gen_Minus(ir_node *node) ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) - return new_bd_arm_fpaMvf(dbgi, block, op, mode); - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Mvf(dbgi, block, op, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - } - else { + } else { panic("Softfloat not supported yet"); } } @@ -807,11 +930,6 @@ static ir_node *gen_Minus(ir_node *node) return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0); } -/** - * Transforms a Load. - * - * @return the created ARM Load node - */ static ir_node *gen_Load(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -823,12 +941,14 @@ static ir_node *gen_Load(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_load = NULL; + if (get_Load_unaligned(node) == align_non_aligned) + panic("unaligned Loads not supported yet"); + if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) - new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode); - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode, + NULL, 0, 0, false); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -843,18 +963,13 @@ static ir_node *gen_Load(ir_node *node) /* check for special case: the loaded value might not be used */ if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) { /* add a result proj and a Keep to produce a pseudo use */ - ir_node *proj = new_r_Proj(block, new_load, mode_Iu, pn_arm_Ldr_res); + ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res); be_new_Keep(block, 1, &proj); } return new_load; } -/** - * Transforms a Store. - * - * @return the created ARM Store node - */ static ir_node *gen_Store(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -868,13 +983,14 @@ static ir_node *gen_Store(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_store = NULL; + if (get_Store_unaligned(node) == align_non_aligned) + panic("unaligned Stores not supported yet"); + if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) - new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val, - new_mem, mode); - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val, + new_mem, mode, NULL, 0, 0, false); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -897,54 +1013,23 @@ static ir_node *gen_Jmp(ir_node *node) return new_bd_arm_Jmp(dbgi, new_block); } -static ir_node *gen_be_Call(ir_node *node) -{ - ir_node *res = be_duplicate_node(node); - arch_irn_add_flags(res, arch_irn_flags_modify_flags); - - return res; -} - -static ir_node *gen_SwitchJmp(ir_node *node) +static ir_node *gen_Switch(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *selector = get_Cond_selector(node); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_op = be_transform_node(selector); - ir_node *const_graph; - ir_node *sub; + ir_graph *irg = get_irn_irg(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *selector = get_Switch_selector(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op = be_transform_node(selector); + ir_mode *mode = get_irn_mode(selector); + const ir_switch_table *table = get_Switch_table(node); + unsigned n_outs = get_Switch_n_outs(node); - ir_node *proj; - const ir_edge_t *edge; - int min = INT_MAX; - int max = INT_MIN; - int translation; - int pn; - int n_projs; + table = ir_switch_table_duplicate(irg, table); - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); + /* switch with smaller modes not implemented yet */ + assert(get_mode_size_bits(mode) == 32); - pn = get_Proj_proj(proj); - - min = pnmax ? pn : max; - } - translation = min; - n_projs = max - translation + 1; - - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - - pn = get_Proj_proj(proj) - translation; - set_Proj_proj(proj, pn); - } - - const_graph = create_const_graph_value(dbgi, block, translation); - sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph); - return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation); + return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table); } static ir_node *gen_Cmp(ir_node *node) @@ -959,40 +1044,17 @@ static ir_node *gen_Cmp(ir_node *node) bool is_unsigned; if (mode_is_float(cmp_mode)) { - /* TODO: revivie this code */ - panic("FloatCmp NIY"); -#if 0 - ir_node *new_op2 = be_transform_node(op2); - /* floating point compare */ - pn_Cmp pnc = get_Proj_proj(selector); + /* TODO: this is broken... */ + new_op1 = be_transform_node(op1); + new_op2 = be_transform_node(op2); - if (pnc & pn_Cmp_Uo) { - /* check for unordered, need cmf */ - return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc); - } - /* Hmm: use need cmfe */ - return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc); -#endif + return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false); } assert(get_irn_mode(op2) == cmp_mode); is_unsigned = !mode_is_signed(cmp_mode); - /* compare with 0 can be done with Tst */ - if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) { - new_op1 = be_transform_node(op1); - new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); - return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false, - is_unsigned); - } - if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) { - new_op2 = be_transform_node(op2); - new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode); - return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true, - is_unsigned); - } - - /* integer compare, TODO: use shifer_op in all its combinations */ + /* integer compare, TODO: use shifter_op in all its combinations */ new_op1 = be_transform_node(op1); new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); new_op2 = be_transform_node(op2); @@ -1001,32 +1063,31 @@ static ir_node *gen_Cmp(ir_node *node) is_unsigned); } -/** - * Transforms a Cond. - * - * @return the created ARM Cond node - */ static ir_node *gen_Cond(ir_node *node) { - ir_node *selector = get_Cond_selector(node); - ir_mode *mode = get_irn_mode(selector); - ir_node *block; - ir_node *flag_node; - dbg_info *dbgi; + ir_node *selector = get_Cond_selector(node); + ir_relation relation; + ir_node *block; + ir_node *flag_node; + dbg_info *dbgi; - if (mode != mode_b) { - return gen_SwitchJmp(node); - } - assert(is_Proj(selector)); + assert(is_Cmp(selector)); block = be_transform_node(get_nodes_block(node)); dbgi = get_irn_dbg_info(node); - flag_node = be_transform_node(get_Proj_pred(selector)); + flag_node = be_transform_node(selector); + relation = get_Cmp_relation(selector); - return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector)); + return new_bd_arm_B(dbgi, block, flag_node, relation); } -static tarval *fpa_imm[3][fpa_max]; +enum fpa_imm_mode { + FPA_IMM_FLOAT = 0, + FPA_IMM_DOUBLE = 1, + FPA_IMM_MAX = FPA_IMM_DOUBLE +}; + +static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max]; #if 0 /** @@ -1040,16 +1101,14 @@ static int is_fpa_immediate(tarval *tv) switch (get_mode_size_bits(mode)) { case 32: - i = 0; + i = FPA_IMM_FLOAT; break; case 64: - i = 1; + i = FPA_IMM_DOUBLE; break; - default: - i = 2; } - if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) { + if (tarval_is_negative(tv)) { tv = tarval_neg(tv); res = -1; } @@ -1062,11 +1121,6 @@ static int is_fpa_immediate(tarval *tv) } #endif -/** - * Transforms a Const node. - * - * @return The transformed ARM node. - */ static ir_node *gen_Const(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -1074,41 +1128,19 @@ static ir_node *gen_Const(ir_node *node) dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - tarval *tv = get_Const_tarval(node); -#if 0 - int imm = is_fpa_immediate(tv); - - if (imm != fpa_max) { - if (imm > 0) - node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm); - else - node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm); - } else { -#endif - { - node = new_bd_arm_fpaConst(dbg, block, tv); - } - be_dep_on_frame(node); + if (USE_FPA(isa)) { + ir_tarval *tv = get_Const_tarval(node); + node = new_bd_arm_fConst(dbg, block, tv); return node; - } - else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); - } - else { + } else { panic("Softfloat not supported yet"); } } return create_const_graph(node, block); } -/** - * Transforms a SymConst node. - * - * @return The transformed ARM node. - */ static ir_node *gen_SymConst(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -1116,16 +1148,87 @@ static ir_node *gen_SymConst(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_node; - new_node = new_bd_arm_SymConst(dbgi, block, entity); - be_dep_on_frame(new_node); + new_node = new_bd_arm_SymConst(dbgi, block, entity, 0); return new_node; } -/** - * Transforms a CopyB node. - * - * @return The transformed ARM node. - */ +static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0, + ir_node *node1) +{ + /* the good way to do this would be to use the stm (store multiple) + * instructions, since our input is nearly always 2 consecutive 32bit + * registers... */ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp, + NULL, 0, 0, true); + ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp, + NULL, 0, 4, true); + ir_node *in[2] = { str0, str1 }; + ir_node *sync = new_r_Sync(block, 2, in); + ir_node *ldf; + set_irn_pinned(str0, op_pin_state_floats); + set_irn_pinned(str1, op_pin_state_floats); + + ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true); + set_irn_pinned(ldf, op_pin_state_floats); + + return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res); +} + +static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp, + NULL, 0, 0, true); + ir_node *ldf; + set_irn_pinned(str, op_pin_state_floats); + + ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true); + set_irn_pinned(ldf, op_pin_state_floats); + + return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res); +} + +static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F, + NULL, 0, 0, true); + ir_node *ldr; + set_irn_pinned(stf, op_pin_state_floats); + + ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true); + set_irn_pinned(ldr, op_pin_state_floats); + + return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res); +} + +static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node, + ir_node **out_value0, ir_node **out_value1) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D, + NULL, 0, 0, true); + ir_node *ldr0, *ldr1; + set_irn_pinned(stf, op_pin_state_floats); + + ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true); + set_irn_pinned(ldr0, op_pin_state_floats); + ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true); + set_irn_pinned(ldr1, op_pin_state_floats); + + *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res); + *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res); +} + static ir_node *gen_CopyB(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -1140,10 +1243,10 @@ static ir_node *gen_CopyB(ir_node *node) ir_node *src_copy; ir_node *dst_copy; - src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src); - dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst); + src_copy = be_new_Copy(block, new_src); + dst_copy = be_new_Copy(block, new_dst); - return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy, + return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy, new_bd_arm_EmptyReg(dbg, block), new_bd_arm_EmptyReg(dbg, block), new_bd_arm_EmptyReg(dbg, block), @@ -1151,82 +1254,83 @@ static ir_node *gen_CopyB(ir_node *node) } /** - * Transforms a FrameAddr into an ARM Add. + * Transform builtin clz. */ -static ir_node *gen_be_FrameAddr(ir_node *node) -{ - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_entity *ent = be_get_frame_entity(node); - ir_node *fp = be_get_FrameAddr_frame(node); - ir_node *new_fp = be_transform_node(fp); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; - - new_node = new_bd_arm_FrameAddr(dbgi, block, new_fp, ent); - return new_node; -} - -/** - * Transform a be_AddSP into an arm_AddSP. Eat up const sizes. - */ -static ir_node *gen_be_AddSP(ir_node *node) +static ir_node *gen_clz(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_AddSP_size); - ir_node *new_sz = be_transform_node(sz); - ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - ir_node *new_sp = be_transform_node(sp); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *nomem = new_NoMem(); - ir_node *new_op; + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *op = get_irn_n(node, 1); + ir_node *new_op = be_transform_node(op); - /* ARM stack grows in reverse direction, make a SubSPandCopy */ - new_op = new_bd_arm_SubSPandCopy(dbgi, block, new_sp, new_sz, nomem); - - return new_op; + /* TODO armv5 instruction, otherwise create a call */ + return new_bd_arm_Clz(dbg, block, new_op); } /** - * Transform a be_SubSP into an arm_SubSP. Eat up const sizes. + * Transform Builtin node. */ -static ir_node *gen_be_SubSP(ir_node *node) +static ir_node *gen_Builtin(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_SubSP_size); - ir_node *new_sz = be_transform_node(sz); - ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - ir_node *new_sp = be_transform_node(sp); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *nomem = new_NoMem(); - ir_node *new_op; - - /* ARM stack grows in reverse direction, make an AddSP */ - new_op = new_bd_arm_AddSP(dbgi, block, new_sp, new_sz, nomem); - - return new_op; + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_return_address: + case ir_bk_frame_address: + case ir_bk_prefetch: + case ir_bk_ffs: + break; + case ir_bk_clz: + return gen_clz(node); + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + case ir_bk_outport: + case ir_bk_inport: + case ir_bk_inner_trampoline: + break; + } + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); } /** - * Transform a be_Copy. + * Transform Proj(Builtin) node. */ -static ir_node *gen_be_Copy(ir_node *node) +static ir_node *gen_Proj_Builtin(ir_node *proj) { - ir_node *result = be_duplicate_node(node); - ir_mode *mode = get_irn_mode(result); - - if (mode_needs_gp_reg(mode)) { - set_irn_mode(node, mode_Iu); + ir_node *node = get_Proj_pred(proj); + ir_node *new_node = be_transform_node(node); + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_return_address: + case ir_bk_frame_address: + case ir_bk_ffs: + case ir_bk_clz: + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + assert(get_Proj_proj(proj) == pn_Builtin_max+1); + return new_node; + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_prefetch: + case ir_bk_outport: + assert(get_Proj_proj(proj) == pn_Builtin_M); + return new_node; + case ir_bk_inport: + case ir_bk_inner_trampoline: + break; } - - return result; + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); } -/** - * Transform a Proj from a Load. - */ static ir_node *gen_Proj_Load(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *load = get_Proj_pred(node); ir_node *new_load = be_transform_node(load); dbg_info *dbgi = get_irn_dbg_info(node); @@ -1237,17 +1341,17 @@ static ir_node *gen_Proj_Load(ir_node *node) case iro_arm_Ldr: /* handle all gp loads equal: they have the same proj numbers. */ if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, block, new_load, mode_Iu, pn_arm_Ldr_res); + return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, block, new_load, mode_M, pn_arm_Ldr_M); + return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M); } break; - case iro_arm_fpaLdf: + case iro_arm_Ldf: if (proj == pn_Load_res) { ir_mode *mode = get_Load_mode(load); - return new_rd_Proj(dbgi, block, new_load, mode, pn_arm_fpaLdf_res); + return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, block, new_load, mode_M, pn_arm_fpaLdf_M); + return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M); } break; default: @@ -1256,21 +1360,17 @@ static ir_node *gen_Proj_Load(ir_node *node) panic("Unsupported Proj from Load"); } -/** - * Transform and renumber the Projs from a CopyB. - */ static ir_node *gen_Proj_CopyB(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); switch (proj) { - case pn_CopyB_M_regular: + case pn_CopyB_M: if (is_arm_CopyB(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_CopyB_M); + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M); } break; default: @@ -1279,12 +1379,8 @@ static ir_node *gen_Proj_CopyB(ir_node *node) panic("Unsupported Proj from CopyB"); } -/** - * Transform and renumber the Projs from a Quot. - */ -static ir_node *gen_Proj_Quot(ir_node *node) +static ir_node *gen_Proj_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); @@ -1292,99 +1388,163 @@ static ir_node *gen_Proj_Quot(ir_node *node) long proj = get_Proj_proj(node); switch (proj) { - case pn_Quot_M: - if (is_arm_fpaDvf(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaDvf_M); - } else if (is_arm_fpaRdf(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaRdf_M); - } else if (is_arm_fpaFdv(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaFdv_M); - } else if (is_arm_fpaFrd(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaFrd_M); - } - break; - case pn_Quot_res: - if (is_arm_fpaDvf(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaDvf_res); - } else if (is_arm_fpaRdf(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaRdf_res); - } else if (is_arm_fpaFdv(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaFdv_res); - } else if (is_arm_fpaFrd(new_pred)) { - return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaFrd_res); - } - break; + case pn_Div_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M); + case pn_Div_res: + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res); default: break; } - panic("Unsupported Proj from Quot"); + panic("Unsupported Proj from Div"); } -/** - * Transform the Projs of a be_AddSP. - */ -static ir_node *gen_Proj_be_AddSP(ir_node *node) +static ir_node *gen_Proj_Start(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = be_transform_node(pred); - dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); long proj = get_Proj_proj(node); - if (proj == pn_be_AddSP_sp) { - ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, - pn_arm_SubSPandCopy_stack); - arch_set_irn_register(res, &arm_gp_regs[REG_SP]); - return res; - } else if (proj == pn_be_AddSP_res) { - return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_arm_SubSPandCopy_addr); - } else if (proj == pn_be_AddSP_M) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_SubSPandCopy_M); + switch ((pn_Start) proj) { + case pn_Start_X_initial_exec: + /* we exchange the ProjX with a jump */ + return new_bd_arm_Jmp(NULL, new_block); + + case pn_Start_M: + return be_prolog_get_memory(abihelper); + + case pn_Start_T_args: + return new_r_Bad(get_irn_irg(block), mode_T); + + case pn_Start_P_frame_base: + return be_prolog_get_reg_value(abihelper, sp_reg); } - panic("Unsupported Proj from AddSP"); + panic("unexpected start proj: %ld\n", proj); } -/** - * Transform the Projs of a be_SubSP. - */ -static ir_node *gen_Proj_be_SubSP(ir_node *node) +static ir_node *gen_Proj_Proj_Start(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = be_transform_node(pred); - dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + long pn = get_Proj_proj(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_entity *entity = get_irg_entity(current_ir_graph); + ir_type *method_type = get_entity_type(entity); + ir_type *param_type = get_method_param_type(method_type, pn); + const reg_or_stackslot_t *param; + + /* Proj->Proj->Start must be a method argument */ + assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args); + + param = &cconv->parameters[pn]; + + if (param->reg0 != NULL) { + /* argument transmitted in register */ + ir_mode *mode = get_type_mode(param_type); + ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0); + + if (mode_is_float(mode)) { + ir_node *value1 = NULL; + + if (param->reg1 != NULL) { + value1 = be_prolog_get_reg_value(abihelper, param->reg1); + } else if (param->entity != NULL) { + ir_graph *irg = get_irn_irg(node); + ir_node *fp = get_irg_frame(irg); + ir_node *mem = be_prolog_get_memory(abihelper); + ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem, + mode_gp, param->entity, + 0, 0, true); + value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res); + } + + /* convert integer value to float */ + if (value1 == NULL) { + value = int_to_float(NULL, new_block, value); + } else { + value = ints_to_double(NULL, new_block, value, value1); + } + } + return value; + } else { + /* argument transmitted on stack */ + ir_graph *irg = get_irn_irg(node); + ir_node *fp = get_irg_frame(irg); + ir_node *mem = be_prolog_get_memory(abihelper); + ir_mode *mode = get_type_mode(param->type); + ir_node *load; + ir_node *value; + + if (mode_is_float(mode)) { + load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode, + param->entity, 0, 0, true); + value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res); + } else { + load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode, + param->entity, 0, 0, true); + value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res); + } + set_irn_pinned(load, op_pin_state_floats); - if (proj == pn_be_SubSP_sp) { - ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, - pn_arm_AddSP_stack); - arch_set_irn_register(res, &arm_gp_regs[REG_SP]); - return res; - } else if (proj == pn_be_SubSP_M) { - return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_AddSP_M); + return value; } - panic("Unsupported Proj from SubSP"); } /** - * Transform the Projs from a Cmp. + * Finds number of output value of a mode_T node which is constrained to + * a single specific register. */ -static ir_node *gen_Proj_Cmp(ir_node *node) +static int find_out_for_reg(ir_node *node, const arch_register_t *reg) { - (void) node; - panic("Mux NYI"); -} + int n_outs = arch_get_irn_n_outs(node); + int o; + for (o = 0; o < n_outs; ++o) { + const arch_register_req_t *req = arch_get_irn_register_req_out(node, o); + if (req == reg->single_req) + return o; + } + return -1; +} -/** - * Transform the Thread Local Storage Proj. - */ -static ir_node *gen_Proj_tls(ir_node *node) +static ir_node *gen_Proj_Proj_Call(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - dbg_info *dbgi = NULL; + long pn = get_Proj_proj(node); + ir_node *call = get_Proj_pred(get_Proj_pred(node)); + ir_node *new_call = be_transform_node(call); + ir_type *function_type = get_Call_type(call); + calling_convention_t *cconv + = arm_decide_calling_convention(NULL, function_type); + const reg_or_stackslot_t *res = &cconv->results[pn]; + ir_mode *mode; + int regn; + + /* TODO 64bit modes */ + assert(res->reg0 != NULL && res->reg1 == NULL); + regn = find_out_for_reg(new_call, res->reg0); + if (regn < 0) { + panic("Internal error in calling convention for return %+F", node); + } + mode = res->reg0->reg_class->mode; + + arm_free_calling_convention(cconv); + + return new_r_Proj(new_call, mode, regn); +} - return new_bd_arm_LdTls(dbgi, block, mode_Iu); +static ir_node *gen_Proj_Call(ir_node *node) +{ + long pn = get_Proj_proj(node); + ir_node *call = get_Proj_pred(node); + ir_node *new_call = be_transform_node(call); + + switch ((pn_Call) pn) { + case pn_Call_M: + return new_r_Proj(new_call, mode_M, 0); + case pn_Call_X_regular: + case pn_Call_X_except: + case pn_Call_T_result: + break; + } + panic("Unexpected Call proj %ld\n", pn); } /** @@ -1392,60 +1552,49 @@ static ir_node *gen_Proj_tls(ir_node *node) */ static ir_node *gen_Proj(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); ir_node *pred = get_Proj_pred(node); - long proj = get_Proj_proj(node); + long proj = get_Proj_proj(node); - if (is_Store(pred)) { + switch (get_irn_opcode(pred)) { + case iro_Store: if (proj == pn_Store_M) { return be_transform_node(pred); } else { panic("Unsupported Proj from Store"); } - } else if (is_Load(pred)) { + case iro_Load: return gen_Proj_Load(node); - } else if (is_CopyB(pred)) { + case iro_Call: + return gen_Proj_Call(node); + case iro_CopyB: return gen_Proj_CopyB(node); - } else if (is_Quot(pred)) { - return gen_Proj_Quot(node); - } else if (be_is_SubSP(pred)) { - return gen_Proj_be_SubSP(node); - } else if (be_is_AddSP(pred)) { - return gen_Proj_be_AddSP(node); - } else if (is_Cmp(pred)) { - return gen_Proj_Cmp(node); - } else if (is_Start(pred)) { - if (proj == pn_Start_X_initial_exec) { - ir_node *block = get_nodes_block(pred); - ir_node *jump; - - /* we exchange the ProjX with a jump */ - block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, block); - return jump; - } - if (node == get_irg_anchor(irg, anchor_tls)) { - return gen_Proj_tls(node); - } - } else { - ir_node *new_pred = be_transform_node(pred); - ir_mode *mode = get_irn_mode(node); - if (mode_needs_gp_reg(mode)) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_proj = new_r_Proj(block, new_pred, mode_Iu, - get_Proj_proj(node)); - new_proj->node_nr = node->node_nr; - return new_proj; + case iro_Div: + return gen_Proj_Div(node); + case iro_Start: + return gen_Proj_Start(node); + case iro_Cond: + case iro_Switch: + /* nothing to do */ + return be_duplicate_node(node); + case iro_Proj: { + ir_node *pred_pred = get_Proj_pred(pred); + if (is_Call(pred_pred)) { + return gen_Proj_Proj_Call(node); + } else if (is_Start(pred_pred)) { + return gen_Proj_Proj_Start(node); } + /* FALLTHROUGH */ + } + case iro_Builtin: + return gen_Proj_Builtin(node); + default: + panic("code selection didn't expect Proj after %+F\n", pred); } - - return be_duplicate_node(node); } typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block); -static inline ir_node *create_const(ir_node **place, +static inline ir_node *create_const(ir_graph *irg, ir_node **place, create_const_node_func func, const arch_register_t* reg) { @@ -1454,7 +1603,7 @@ static inline ir_node *create_const(ir_node **place, if (*place != NULL) return *place; - block = get_irg_start_block(env_cg->irg); + block = get_irg_start_block(irg); res = func(NULL, block); arch_set_irn_register(res, reg); *place = res; @@ -1470,10 +1619,9 @@ static ir_node *gen_Unknown(ir_node *node) /* just produce a 0 */ ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - tarval *tv = get_mode_null(mode); - ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv); - be_dep_on_frame(node); - return node; + ir_tarval *tv = get_mode_null(mode); + ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv); + return fconst; } else if (mode_needs_gp_reg(mode)) { return create_const_graph_value(dbgi, new_block, 0); } @@ -1482,125 +1630,422 @@ static ir_node *gen_Unknown(ir_node *node) } /** - * Change some phi modes + * Produces the type which sits between the stack args and the locals on the + * stack. It will contain the return address and space to store the old base + * pointer. + * @return The Firm type modeling the ABI between type. */ -static ir_node *gen_Phi(ir_node *node) +static ir_type *arm_get_between_type(void) { - const arch_register_req_t *req; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *phi; + static ir_type *between_type = NULL; - if (mode_needs_gp_reg(mode)) { - /* we shouldn't have any 64bit stuff around anymore */ - assert(get_mode_size_bits(mode) <= 32); - /* all integer operations are on 32bit registers now */ - mode = mode_Iu; - req = arm_reg_classes[CLASS_arm_gp].class_req; - } else { - req = arch_no_register_req; + if (between_type == NULL) { + between_type = new_type_class(new_id_from_str("arm_between_type")); + set_type_size_bytes(between_type, 0); } - /* phi nodes allow loops, so we use the old arguments for now - * and fix this later */ - phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), - get_irn_in(node) + 1); - copy_node_attr(node, phi); - be_duplicate_deps(node, phi); - - arch_set_out_register_req(phi, 0, req); + return between_type; +} - be_enqueue_preds(node); +static void create_stacklayout(ir_graph *irg) +{ + ir_entity *entity = get_irg_entity(irg); + ir_type *function_type = get_entity_type(entity); + be_stack_layout_t *layout = be_get_irg_stack_layout(irg); + ir_type *arg_type; + int p; + int n_params; + + /* calling conventions must be decided by now */ + assert(cconv != NULL); + + /* construct argument type */ + arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8))); + n_params = get_method_n_params(function_type); + for (p = 0; p < n_params; ++p) { + reg_or_stackslot_t *param = &cconv->parameters[p]; + char buf[128]; + ident *id; + + if (param->type == NULL) + continue; + + snprintf(buf, sizeof(buf), "param_%d", p); + id = new_id_from_str(buf); + param->entity = new_entity(arg_type, id, param->type); + set_entity_offset(param->entity, param->offset); + } - return phi; + /* TODO: what about external functions? we don't know most of the stack + * layout for them. And probably don't need all of this... */ + memset(layout, 0, sizeof(*layout)); + + layout->frame_type = get_irg_frame_type(irg); + layout->between_type = arm_get_between_type(); + layout->arg_type = arg_type; + layout->initial_offset = 0; + layout->initial_bias = 0; + layout->sp_relative = true; + + assert(N_FRAME_TYPES == 3); + layout->order[0] = layout->frame_type; + layout->order[1] = layout->between_type; + layout->order[2] = layout->arg_type; } /** - * the BAD transformer. + * transform the start node to the prolog code */ -static ir_node *bad_transform(ir_node *irn) +static ir_node *gen_Start(ir_node *node) { - panic("ARM backend: Not implemented: %+F", irn); + ir_graph *irg = get_irn_irg(node); + ir_entity *entity = get_irg_entity(irg); + ir_type *function_type = get_entity_type(entity); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *start; + size_t i; + + /* stackpointer is important at function prolog */ + be_prolog_add_reg(abihelper, sp_reg, + arch_register_req_type_produces_sp | arch_register_req_type_ignore); + /* function parameters in registers */ + for (i = 0; i < get_method_n_params(function_type); ++i) { + const reg_or_stackslot_t *param = &cconv->parameters[i]; + if (param->reg0 != NULL) + be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none); + if (param->reg1 != NULL) + be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none); + } + /* announce that we need the values of the callee save regs */ + for (i = 0; i != ARRAY_SIZE(callee_saves); ++i) { + be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none); + } + + start = be_prolog_create_start(abihelper, dbgi, new_block); + return start; } -/** - * Set a node emitter. Make it a bit more type safe. - */ -static void set_transformer(ir_op *op, be_transform_func arm_transform_func) +static ir_node *get_stack_pointer_for(ir_node *node) { - op->ops.generic = (op_func)arm_transform_func; + /* get predecessor in stack_order list */ + ir_node *stack_pred = be_get_stack_pred(stackorder, node); + ir_node *stack; + + if (stack_pred == NULL) { + /* first stack user in the current block. We can simply use the + * initial sp_proj for it */ + ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg); + return sp_proj; + } + + be_transform_node(stack_pred); + stack = pmap_get(ir_node, node_to_stack, stack_pred); + if (stack == NULL) { + return get_stack_pointer_for(stack_pred); + } + + return stack; } /** - * Enters all transform functions into the generic pointer + * transform a Return node into epilogue code + return statement */ -static void arm_register_transformers(void) +static ir_node *gen_Return(ir_node *node) { - /* first clear the generic function pointer for all ops */ - clear_irp_opcodes_generic_func(); - - set_transformer(op_Abs, gen_Abs); - set_transformer(op_Add, gen_Add); - set_transformer(op_And, gen_And); - set_transformer(op_be_AddSP, gen_be_AddSP); - set_transformer(op_be_Call, gen_be_Call); - set_transformer(op_be_Copy, gen_be_Copy); - set_transformer(op_be_FrameAddr, gen_be_FrameAddr); - set_transformer(op_be_SubSP, gen_be_SubSP); - set_transformer(op_Cmp, gen_Cmp); - set_transformer(op_Cond, gen_Cond); - set_transformer(op_Const, gen_Const); - set_transformer(op_Conv, gen_Conv); - set_transformer(op_CopyB, gen_CopyB); - set_transformer(op_Eor, gen_Eor); - set_transformer(op_Jmp, gen_Jmp); - set_transformer(op_Load, gen_Load); - set_transformer(op_Minus, gen_Minus); - set_transformer(op_Mul, gen_Mul); - set_transformer(op_Not, gen_Not); - set_transformer(op_Or, gen_Or); - set_transformer(op_Phi, gen_Phi); - set_transformer(op_Proj, gen_Proj); - set_transformer(op_Quot, gen_Quot); - set_transformer(op_Rotl, gen_Rotl); - set_transformer(op_Shl, gen_Shl); - set_transformer(op_Shr, gen_Shr); - set_transformer(op_Shrs, gen_Shrs); - set_transformer(op_Store, gen_Store); - set_transformer(op_Sub, gen_Sub); - set_transformer(op_SymConst, gen_SymConst); - set_transformer(op_Unknown, gen_Unknown); - - set_transformer(op_ASM, bad_transform); - set_transformer(op_Builtin, bad_transform); - set_transformer(op_CallBegin, bad_transform); - set_transformer(op_Cast, bad_transform); - set_transformer(op_Confirm, bad_transform); - set_transformer(op_DivMod, bad_transform); - set_transformer(op_EndExcept, bad_transform); - set_transformer(op_EndReg, bad_transform); - set_transformer(op_Filter, bad_transform); - set_transformer(op_Free, bad_transform); - set_transformer(op_Id, bad_transform); - set_transformer(op_InstOf, bad_transform); - set_transformer(op_Mulh, bad_transform); - set_transformer(op_Mux, bad_transform); - set_transformer(op_Raise, bad_transform); - set_transformer(op_Sel, bad_transform); - set_transformer(op_Tuple, bad_transform); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *mem = get_Return_mem(node); + ir_node *new_mem = be_transform_node(mem); + size_t n_callee_saves = ARRAY_SIZE(callee_saves); + ir_node *sp_proj = get_stack_pointer_for(node); + size_t n_res = get_Return_n_ress(node); + ir_node *bereturn; + size_t i; + + be_epilog_begin(abihelper); + be_epilog_set_memory(abihelper, new_mem); + /* connect stack pointer with initial stack pointer. fix_stack phase + will later serialize all stack pointer adjusting nodes */ + be_epilog_add_reg(abihelper, sp_reg, + arch_register_req_type_produces_sp | arch_register_req_type_ignore, + sp_proj); + + /* result values */ + for (i = 0; i < n_res; ++i) { + ir_node *res_value = get_Return_res(node, i); + ir_node *new_res_value = be_transform_node(res_value); + const reg_or_stackslot_t *slot = &cconv->results[i]; + const arch_register_t *reg = slot->reg0; + assert(slot->reg1 == NULL); + be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value); + } + + /* connect callee saves with their values at the function begin */ + for (i = 0; i < n_callee_saves; ++i) { + const arch_register_t *reg = callee_saves[i]; + ir_node *value = be_prolog_get_reg_value(abihelper, reg); + be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value); + } + + /* epilog code: an incsp */ + bereturn = be_epilog_create_return(abihelper, dbgi, new_block); + return bereturn; +} + + +static ir_node *gen_Call(ir_node *node) +{ + ir_graph *irg = get_irn_irg(node); + ir_node *callee = get_Call_ptr(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *mem = get_Call_mem(node); + ir_node *new_mem = be_transform_node(mem); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_type *type = get_Call_type(node); + calling_convention_t *cconv = arm_decide_calling_convention(NULL, type); + size_t n_params = get_Call_n_params(node); + size_t const n_param_regs = cconv->n_reg_params; + /* max inputs: memory, callee, register arguments */ + size_t const max_inputs = 2 + n_param_regs; + ir_node **in = ALLOCAN(ir_node*, max_inputs); + ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs); + struct obstack *obst = be_get_be_obst(irg); + const arch_register_req_t **in_req + = OALLOCNZ(obst, const arch_register_req_t*, max_inputs); + size_t in_arity = 0; + size_t sync_arity = 0; + size_t const n_caller_saves = ARRAY_SIZE(caller_saves); + ir_entity *entity = NULL; + ir_node *incsp = NULL; + int mem_pos; + ir_node *res; + size_t p; + size_t o; + size_t out_arity; + + assert(n_params == get_method_n_params(type)); + + /* construct arguments */ + + /* memory input */ + in_req[in_arity] = arch_no_register_req; + mem_pos = in_arity; + ++in_arity; + /* parameters */ + for (p = 0; p < n_params; ++p) { + ir_node *value = get_Call_param(node, p); + ir_node *new_value = be_transform_node(value); + ir_node *new_value1 = NULL; + const reg_or_stackslot_t *param = &cconv->parameters[p]; + ir_type *param_type = get_method_param_type(type, p); + ir_mode *mode = get_type_mode(param_type); + ir_node *str; + + if (mode_is_float(mode) && param->reg0 != NULL) { + unsigned size_bits = get_mode_size_bits(mode); + if (size_bits == 64) { + double_to_ints(dbgi, new_block, new_value, &new_value, + &new_value1); + } else { + assert(size_bits == 32); + new_value = float_to_int(dbgi, new_block, new_value); + } + } + + /* put value into registers */ + if (param->reg0 != NULL) { + in[in_arity] = new_value; + in_req[in_arity] = param->reg0->single_req; + ++in_arity; + if (new_value1 == NULL) + continue; + } + if (param->reg1 != NULL) { + assert(new_value1 != NULL); + in[in_arity] = new_value1; + in_req[in_arity] = param->reg1->single_req; + ++in_arity; + continue; + } + + /* we need a store if we're here */ + if (new_value1 != NULL) { + new_value = new_value1; + mode = mode_gp; + } + + /* create a parameter frame if necessary */ + if (incsp == NULL) { + ir_node *new_frame = get_stack_pointer_for(node); + incsp = be_new_IncSP(sp_reg, new_block, new_frame, + cconv->param_stack_size, 1); + } + if (mode_is_float(mode)) { + str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem, + mode, NULL, 0, param->offset, true); + } else { + str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem, + mode, NULL, 0, param->offset, true); + } + sync_ins[sync_arity++] = str; + } + assert(in_arity <= max_inputs); + + /* construct memory input */ + if (sync_arity == 0) { + in[mem_pos] = new_mem; + } else if (sync_arity == 1) { + in[mem_pos] = sync_ins[0]; + } else { + in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins); + } + + /* TODO: use a generic symconst matcher here */ + if (is_SymConst(callee)) { + entity = get_SymConst_entity(callee); + } else { + /* TODO: finish load matcher here */ +#if 0 + /* callee */ + if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) { + ir_node *load = get_Proj_pred(callee); + ir_node *ptr = get_Load_ptr(load); + ir_node *new_ptr = be_transform_node(ptr); + ir_node *mem = get_Load_mem(load); + ir_node *new_mem = be_transform_node(mem); + ir_mode *mode = get_Load_mode(node); + + } else { +#endif + in[in_arity] = be_transform_node(callee); + in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req; + ++in_arity; + //} + } + + /* outputs: + * - memory + * - caller saves + */ + out_arity = 1 + n_caller_saves; + + if (entity != NULL) { + /* TODO: use a generic symconst matcher here + * so we can also handle entity+offset, etc. */ + res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0); + } else { + /* TODO: + * - use a proper shifter_operand matcher + * - we could also use LinkLdrPC + */ + res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity, + ARM_SHF_REG, 0, 0); + } + + if (incsp != NULL) { + /* IncSP to destroy the call stackframe */ + incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, + 0); + /* if we are the last IncSP producer in a block then we have to keep + * the stack value. + * Note: This here keeps all producers which is more than necessary */ + add_irn_dep(incsp, res); + keep_alive(incsp); + + pmap_insert(node_to_stack, node, incsp); + } + + arch_set_irn_register_reqs_in(res, in_req); + + /* create output register reqs */ + arch_set_irn_register_req_out(res, 0, arch_no_register_req); + for (o = 0; o < n_caller_saves; ++o) { + const arch_register_t *reg = caller_saves[o]; + arch_set_irn_register_req_out(res, o+1, reg->single_req); + } + + /* copy pinned attribute */ + set_irn_pinned(res, get_irn_pinned(node)); + + arm_free_calling_convention(cconv); + return res; +} + +static ir_node *gen_Sel(ir_node *node) +{ + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *ptr = get_Sel_ptr(node); + ir_node *new_ptr = be_transform_node(ptr); + ir_entity *entity = get_Sel_entity(node); + + /* must be the frame pointer all other sels must have been lowered + * already */ + assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr))); + + return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0); +} + +static ir_node *gen_Phi(ir_node *node) +{ + ir_mode *mode = get_irn_mode(node); + const arch_register_req_t *req; + if (mode_needs_gp_reg(mode)) { + /* we shouldn't have any 64bit stuff around anymore */ + assert(get_mode_size_bits(mode) <= 32); + /* all integer operations are on 32bit registers now */ + mode = mode_Iu; + req = arm_reg_classes[CLASS_arm_gp].class_req; + } else { + req = arch_no_register_req; + } + + return be_transform_phi(node, req); } /** - * Pre-transform all unknown nodes. + * Enters all transform functions into the generic pointer */ -static void arm_pretransform_node(void) +static void arm_register_transformers(void) { - arm_code_gen_t *cg = env_cg; - - cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); - cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa); + be_start_transform_setup(); + + be_set_transform_function(op_Add, gen_Add); + be_set_transform_function(op_And, gen_And); + be_set_transform_function(op_Call, gen_Call); + be_set_transform_function(op_Cmp, gen_Cmp); + be_set_transform_function(op_Cond, gen_Cond); + be_set_transform_function(op_Const, gen_Const); + be_set_transform_function(op_Conv, gen_Conv); + be_set_transform_function(op_CopyB, gen_CopyB); + be_set_transform_function(op_Div, gen_Div); + be_set_transform_function(op_Eor, gen_Eor); + be_set_transform_function(op_Jmp, gen_Jmp); + be_set_transform_function(op_Load, gen_Load); + be_set_transform_function(op_Minus, gen_Minus); + be_set_transform_function(op_Mul, gen_Mul); + be_set_transform_function(op_Not, gen_Not); + be_set_transform_function(op_Or, gen_Or); + be_set_transform_function(op_Phi, gen_Phi); + be_set_transform_function(op_Proj, gen_Proj); + be_set_transform_function(op_Return, gen_Return); + be_set_transform_function(op_Rotl, gen_Rotl); + be_set_transform_function(op_Sel, gen_Sel); + be_set_transform_function(op_Shl, gen_Shl); + be_set_transform_function(op_Shr, gen_Shr); + be_set_transform_function(op_Shrs, gen_Shrs); + be_set_transform_function(op_Start, gen_Start); + be_set_transform_function(op_Store, gen_Store); + be_set_transform_function(op_Sub, gen_Sub); + be_set_transform_function(op_Switch, gen_Switch); + be_set_transform_function(op_SymConst, gen_SymConst); + be_set_transform_function(op_Unknown, gen_Unknown); + be_set_transform_function(op_Builtin, gen_Builtin); } /** @@ -1609,48 +2054,74 @@ static void arm_pretransform_node(void) static void arm_init_fpa_immediate(void) { /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */ - fpa_imm[0][fpa_null] = get_tarval_null(mode_F); - fpa_imm[0][fpa_one] = get_tarval_one(mode_F); - fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F); - fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F); - fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F); - fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F); - fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F); - fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); - - fpa_imm[1][fpa_null] = get_tarval_null(mode_D); - fpa_imm[1][fpa_one] = get_tarval_one(mode_D); - fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D); - fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D); - fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D); - fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D); - fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D); - fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); - - fpa_imm[2][fpa_null] = get_tarval_null(mode_E); - fpa_imm[2][fpa_one] = get_tarval_one(mode_E); - fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E); - fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E); - fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E); - fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E); - fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E); - fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E); + fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); + + fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); } /** * Transform a Firm graph into an ARM graph. */ -void arm_transform_graph(arm_code_gen_t *cg) +void arm_transform_graph(ir_graph *irg) { static int imm_initialized = 0; + ir_entity *entity = get_irg_entity(irg); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ir_type *frame_type; + + mode_gp = mode_Iu; + mode_fp = mode_F; if (! imm_initialized) { arm_init_fpa_immediate(); imm_initialized = 1; } arm_register_transformers(); - env_cg = cg; - be_transform_graph(cg->birg, arm_pretransform_node); + + isa = (arm_isa_t*) arch_env; + + node_to_stack = pmap_create(); + + assert(abihelper == NULL); + abihelper = be_abihelper_prepare(irg); + stackorder = be_collect_stacknodes(irg); + assert(cconv == NULL); + cconv = arm_decide_calling_convention(irg, get_entity_type(entity)); + create_stacklayout(irg); + + be_transform_graph(irg, NULL); + + be_abihelper_finish(abihelper); + abihelper = NULL; + be_free_stackorder(stackorder); + stackorder = NULL; + + arm_free_calling_convention(cconv); + cconv = NULL; + + frame_type = get_irg_frame_type(irg); + if (get_type_state(frame_type) == layout_undefined) { + default_layout_compound_type(frame_type); + } + + pmap_destroy(node_to_stack); + node_to_stack = NULL; + + be_add_missing_keeps(irg); } void arm_init_transform(void)