X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_transform.c;h=e231cc9fb41fd8e5c96036fdab9be4fa131451ad;hb=26e4122270acb4d7644f91b08b088fe64a864611;hp=4f06c1dfa77ab644c39567e154f82190ecf57750;hpb=2e33d052cdf2acacc39981474cce3e82ad7b0da7;p=libfirm diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c index 4f06c1dfa..e231cc9fb 100644 --- a/ir/be/arm/arm_transform.c +++ b/ir/be/arm/arm_transform.c @@ -21,7 +21,6 @@ * @file * @brief The codegenerator (transform FIRM into arm FIRM) * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck - * @version $Id$ */ #include "config.h" @@ -30,20 +29,20 @@ #include "irmode_t.h" #include "irgmod.h" #include "iredges.h" -#include "irvrfy.h" #include "ircons.h" #include "irprintf.h" #include "dbginfo.h" #include "iropt_t.h" #include "debug.h" #include "error.h" +#include "util.h" -#include "../benode.h" -#include "../beirg.h" -#include "../beutil.h" -#include "../betranshlp.h" -#include "../beabihelper.h" -#include "../beabi.h" +#include "benode.h" +#include "beirg.h" +#include "beutil.h" +#include "betranshlp.h" +#include "beabihelper.h" +#include "beabi.h" #include "bearch_arm_t.h" #include "arm_nodes_attr.h" @@ -59,16 +58,45 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -/** hold the current code generator during transformation */ -static arm_code_gen_t *env_cg; - -static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP]; +static const arch_register_t *sp_reg = &arm_registers[REG_SP]; static ir_mode *mode_gp; +static ir_mode *mode_fp; static beabi_helper_env_t *abihelper; +static be_stackorder_t *stackorder; static calling_convention_t *cconv = NULL; +static arm_isa_t *isa; static pmap *node_to_stack; +static const arch_register_t *const callee_saves[] = { + &arm_registers[REG_R4], + &arm_registers[REG_R5], + &arm_registers[REG_R6], + &arm_registers[REG_R7], + &arm_registers[REG_R8], + &arm_registers[REG_R9], + &arm_registers[REG_R10], + &arm_registers[REG_R11], + &arm_registers[REG_LR], +}; + +static const arch_register_t *const caller_saves[] = { + &arm_registers[REG_R0], + &arm_registers[REG_R1], + &arm_registers[REG_R2], + &arm_registers[REG_R3], + &arm_registers[REG_LR], + + &arm_registers[REG_F0], + &arm_registers[REG_F1], + &arm_registers[REG_F2], + &arm_registers[REG_F3], + &arm_registers[REG_F4], + &arm_registers[REG_F5], + &arm_registers[REG_F6], + &arm_registers[REG_F7], +}; + static bool mode_needs_gp_reg(ir_mode *mode) { return mode_is_int(mode) || mode_is_reference(mode); @@ -96,7 +124,6 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, if (vn.ops < v.ops) { /* remove bits */ result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]); - be_dep_on_frame(result); for (cnt = 1; cnt < vn.ops; ++cnt) { result = new_bd_arm_Bic_imm(dbgi, block, result, @@ -105,7 +132,6 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, } else { /* add bits */ result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]); - be_dep_on_frame(result); for (cnt = 1; cnt < v.ops; ++cnt) { result = new_bd_arm_Or_imm(dbgi, block, result, @@ -122,9 +148,9 @@ static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, */ static ir_node *create_const_graph(ir_node *irn, ir_node *block) { - tarval *tv = get_Const_tarval(irn); - ir_mode *mode = get_tarval_mode(tv); - unsigned value; + ir_tarval *tv = get_Const_tarval(irn); + ir_mode *mode = get_tarval_mode(tv); + unsigned value; if (mode_is_reference(mode)) { /* ARM is 32bit, so we can safely convert a reference tarval into Iu */ @@ -215,22 +241,24 @@ static ir_node *gen_Conv(ir_node *node) return new_op; if (mode_is_float(src_mode) || mode_is_float(dst_mode)) { - env_cg->have_fp_insn = 1; - - if (USE_FPA(env_cg->isa)) { + if (USE_FPA(isa)) { if (mode_is_float(src_mode)) { if (mode_is_float(dst_mode)) { /* from float to float */ - return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode); + return new_bd_arm_Mvf(dbg, block, new_op, dst_mode); } else { /* from float to int */ - return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode); + panic("TODO"); } } else { /* from int to float */ - return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode); + if (!mode_is_signed(src_mode)) { + panic("TODO"); + } else { + return new_bd_arm_FltX(dbg, block, new_op, dst_mode); + } } - } else if (USE_VFP(env_cg->isa)) { + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -349,15 +377,29 @@ static ir_node *arm_skip_downconv(ir_node *node) typedef enum { MATCH_NONE = 0, - MATCH_COMMUTATIVE = 1 << 0, - MATCH_SIZE_NEUTRAL = 1 << 1, + MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */ + MATCH_REVERSE = 1 << 1, /**< support reverse opcode */ + MATCH_SIZE_NEUTRAL = 1 << 2, + MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */ } match_flags_t; +ENUM_BITSET(match_flags_t) -typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2); -typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot); +/** + * possible binop constructors. + */ +typedef struct arm_binop_factory_t { + /** normal reg op reg operation. */ + ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2); + /** normal reg op imm operation. */ + ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot); + /** barrel shifter reg op (reg shift reg operation. */ + ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier); + /** barrel shifter reg op (reg shift imm operation. */ + ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate); +} arm_binop_factory_t; static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, - new_binop_reg_func new_reg, new_binop_imm_func new_imm) + const arm_binop_factory_t *factory) { ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_binop_left(node); @@ -367,6 +409,14 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, dbg_info *dbgi = get_irn_dbg_info(node); arm_immediate_t imm; + if (flags & MATCH_SKIP_NOT) { + if (is_Not(op1)) + op1 = get_Not_op(op1); + else if (is_Not(op2)) + op2 = get_Not_op(op2); + else + panic("cannot execute MATCH_SKIP_NOT"); + } if (flags & MATCH_SIZE_NEUTRAL) { op1 = arm_skip_downconv(op1); op2 = arm_skip_downconv(op2); @@ -375,16 +425,92 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, } if (try_encode_as_immediate(op2, &imm)) { - ir_node *new_op1 = be_transform_node(op1); - return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot); + new_op1 = be_transform_node(op1); + return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot); } new_op2 = be_transform_node(op2); - if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) { - return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); + if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) { + if (flags & MATCH_REVERSE) + return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); + else + return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); } new_op1 = be_transform_node(op1); - return new_reg(dbgi, block, new_op1, new_op2); + /* check if we can fold in a Mov */ + if (is_arm_Mov(new_op2)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2); + + switch (attr->shift_modifier) { + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + if (factory->new_binop_reg_shift_imm) { + ir_node *mov_op = get_irn_n(new_op2, 0); + return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op, + attr->shift_modifier, attr->shift_immediate); + } + break; + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + if (factory->new_binop_reg_shift_reg) { + ir_node *mov_op = get_irn_n(new_op2, 0); + ir_node *mov_sft = get_irn_n(new_op2, 1); + return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft, + attr->shift_modifier); + } + break; + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); + } + } + if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1); + int idx = flags & MATCH_REVERSE ? 1 : 0; + + switch (attr->shift_modifier) { + ir_node *mov_op, *mov_sft; + + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + if (factory[idx].new_binop_reg_shift_imm) { + mov_op = get_irn_n(new_op1, 0); + return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op, + attr->shift_modifier, attr->shift_immediate); + } + break; + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + if (factory[idx].new_binop_reg_shift_reg) { + mov_op = get_irn_n(new_op1, 0); + mov_sft = get_irn_n(new_op1, 1); + return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft, + attr->shift_modifier); + } + break; + + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); + } + } + return factory->new_binop_reg(dbgi, block, new_op1, new_op2); } /** @@ -394,7 +520,14 @@ static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, */ static ir_node *gen_Add(ir_node *node) { - ir_mode *mode = get_irn_mode(node); + static const arm_binop_factory_t add_factory = { + new_bd_arm_Add_reg, + new_bd_arm_Add_imm, + new_bd_arm_Add_reg_shift_reg, + new_bd_arm_Add_reg_shift_imm + }; + + ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -403,17 +536,9 @@ static ir_node *gen_Add(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_op1 = be_transform_node(op1); ir_node *new_op2 = be_transform_node(op2); - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_fpaMvf_i(new_op1)) - return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_fpaMvf_i(new_op2)) - return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -437,8 +562,7 @@ static ir_node *gen_Add(ir_node *node) } #endif - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Add_reg, new_bd_arm_Add_imm); + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory); } } @@ -458,17 +582,9 @@ static ir_node *gen_Mul(ir_node *node) dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -478,29 +594,22 @@ static ir_node *gen_Mul(ir_node *node) return new_bd_arm_Mul(dbg, block, new_op1, new_op2); } -static ir_node *gen_Quot(ir_node *node) +static ir_node *gen_Div(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Quot_left(node); + ir_node *op1 = get_Div_left(node); ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Quot_right(node); + ir_node *op2 = get_Div_right(node); ir_node *new_op2 = be_transform_node(op2); - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_Div_resmode(node); dbg_info *dbg = get_irn_dbg_info(node); - assert(mode != mode_E && "IEEE Extended FP not supported"); + /* integer division should be replaced by builtin call */ + assert(mode_is_float(mode)); - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -509,24 +618,72 @@ static ir_node *gen_Quot(ir_node *node) static ir_node *gen_And(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_And_reg, new_bd_arm_And_imm); + static const arm_binop_factory_t and_factory = { + new_bd_arm_And_reg, + new_bd_arm_And_imm, + new_bd_arm_And_reg_shift_reg, + new_bd_arm_And_reg_shift_imm + }; + static const arm_binop_factory_t bic_factory = { + new_bd_arm_Bic_reg, + new_bd_arm_Bic_imm, + new_bd_arm_Bic_reg_shift_reg, + new_bd_arm_Bic_reg_shift_imm + }; + + /* check for and not */ + ir_node *left = get_And_left(node); + ir_node *right = get_And_right(node); + + if (is_Not(left) || is_Not(right)) { + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT, + &bic_factory); + } + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory); } static ir_node *gen_Or(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Or_reg, new_bd_arm_Or_imm); + static const arm_binop_factory_t or_factory = { + new_bd_arm_Or_reg, + new_bd_arm_Or_imm, + new_bd_arm_Or_reg_shift_reg, + new_bd_arm_Or_reg_shift_imm + }; + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory); } static ir_node *gen_Eor(ir_node *node) { - return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, - new_bd_arm_Eor_reg, new_bd_arm_Eor_imm); + static const arm_binop_factory_t eor_factory = { + new_bd_arm_Eor_reg, + new_bd_arm_Eor_imm, + new_bd_arm_Eor_reg_shift_reg, + new_bd_arm_Eor_reg_shift_imm + }; + + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory); } static ir_node *gen_Sub(ir_node *node) { + static const arm_binop_factory_t sub_rsb_factory[2] = { + { + new_bd_arm_Sub_reg, + new_bd_arm_Sub_imm, + new_bd_arm_Sub_reg_shift_reg, + new_bd_arm_Sub_reg_shift_imm + }, + { + new_bd_arm_Rsb_reg, + new_bd_arm_Rsb_imm, + new_bd_arm_Rsb_reg_shift_reg, + new_bd_arm_Rsb_reg_shift_imm + } + }; + ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_Sub_left(node); ir_node *new_op1 = be_transform_node(op1); @@ -536,24 +693,15 @@ static ir_node *gen_Sub(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { -#if 0 - if (is_arm_Mov_i(new_op1)) - return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); -#endif - return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); } } else { - return gen_int_binop(node, MATCH_SIZE_NEUTRAL, - new_bd_arm_Sub_reg, new_bd_arm_Sub_imm); + return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory); } } @@ -585,9 +733,13 @@ static ir_node *make_shift(ir_node *node, match_flags_t flags, ir_node *op1 = get_binop_left(node); ir_node *op2 = get_binop_right(node); dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); ir_node *new_op1; ir_node *new_op2; + if (get_mode_modulo_shift(mode) != 32) + panic("modulo shift!=32 not supported"); + if (flags & MATCH_SIZE_NEUTRAL) { op1 = arm_skip_downconv(op1); op2 = arm_skip_downconv(op2); @@ -595,7 +747,7 @@ static ir_node *make_shift(ir_node *node, match_flags_t flags, new_op1 = be_transform_node(op1); if (is_Const(op2)) { - tarval *tv = get_Const_tarval(op2); + ir_tarval *tv = get_Const_tarval(op2); unsigned int val = get_tarval_long(tv); assert(tarval_is_long(tv)); if (can_use_shift_constant(val, shift_modifier)) { @@ -668,10 +820,10 @@ static ir_node *gen_Rotl(ir_node *node) if (is_Add(op2)) { ir_node *right = get_Add_right(op2); if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); - ir_node *left = get_Add_left(op2); + ir_tarval *tv = get_Const_tarval(right); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *left = get_Add_left(op2); if (is_Minus(left) && tarval_is_long(tv) && @@ -682,10 +834,10 @@ static ir_node *gen_Rotl(ir_node *node) } else if (is_Sub(op2)) { ir_node *left = get_Sub_left(op2); if (is_Const(left)) { - tarval *tv = get_Const_tarval(left); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); - ir_node *right = get_Sub_right(op2); + ir_tarval *tv = get_Const_tarval(left); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *right = get_Sub_right(op2); if (tarval_is_long(tv) && get_tarval_long(tv) == bits && @@ -693,9 +845,9 @@ static ir_node *gen_Rotl(ir_node *node) rotate = gen_Ror(node, op1, right); } } else if (is_Const(op2)) { - tarval *tv = get_Const_tarval(op2); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); + ir_tarval *tv = get_Const_tarval(op2); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); if (tarval_is_long(tv) && bits == 32) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -721,32 +873,40 @@ static ir_node *gen_Not(ir_node *node) ir_node *new_op = be_transform_node(op); dbg_info *dbgi = get_irn_dbg_info(node); - /* TODO: we could do alot more here with all the Mvn variations */ - - return new_bd_arm_Mvn_reg(dbgi, block, new_op); -} - -static ir_node *gen_Abs(ir_node *node) -{ - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Abs_op(node); - ir_node *new_op = be_transform_node(op); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - - if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - return new_bd_arm_fpaAbs(dbgi, block, new_op, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet"); - } else { - panic("Softfloat not supported yet"); + /* check if we can fold in a Mov */ + if (is_arm_Mov(new_op)) { + const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op); + + switch (attr->shift_modifier) { + ir_node *mov_op, *mov_sft; + + case ARM_SHF_IMM: + case ARM_SHF_ASR_IMM: + case ARM_SHF_LSL_IMM: + case ARM_SHF_LSR_IMM: + case ARM_SHF_ROR_IMM: + mov_op = get_irn_n(new_op, 0); + return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op, + attr->shift_modifier, attr->shift_immediate); + + case ARM_SHF_ASR_REG: + case ARM_SHF_LSL_REG: + case ARM_SHF_LSR_REG: + case ARM_SHF_ROR_REG: + mov_op = get_irn_n(new_op, 0); + mov_sft = get_irn_n(new_op, 1); + return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft, + attr->shift_modifier); + + case ARM_SHF_REG: + case ARM_SHF_RRX: + break; + case ARM_SHF_INVALID: + panic("invalid shift"); } } - assert(mode_is_data(mode)); - return new_bd_arm_Abs(dbgi, block, new_op); + + return new_bd_arm_Mvn_reg(dbgi, block, new_op); } static ir_node *gen_Minus(ir_node *node) @@ -758,11 +918,9 @@ static ir_node *gen_Minus(ir_node *node) ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - return new_bd_arm_fpaMvf(dbgi, block, op, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + return new_bd_arm_Mvf(dbgi, block, op, mode); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -783,12 +941,14 @@ static ir_node *gen_Load(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_load = NULL; + if (get_Load_unaligned(node) == align_non_aligned) + panic("unaligned Loads not supported yet"); + if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode, + NULL, 0, 0, false); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -823,13 +983,14 @@ static ir_node *gen_Store(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_store = NULL; + if (get_Store_unaligned(node) == align_non_aligned) + panic("unaligned Stores not supported yet"); + if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val, - new_mem, mode); - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + if (USE_FPA(isa)) { + new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val, + new_mem, mode, NULL, 0, 0, false); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -852,46 +1013,23 @@ static ir_node *gen_Jmp(ir_node *node) return new_bd_arm_Jmp(dbgi, new_block); } -static ir_node *gen_SwitchJmp(ir_node *node) +static ir_node *gen_Switch(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *selector = get_Cond_selector(node); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_op = be_transform_node(selector); - ir_node *const_graph; - ir_node *sub; - - ir_node *proj; - const ir_edge_t *edge; - int min = INT_MAX; - int max = INT_MIN; - int translation; - int pn; - int n_projs; + ir_graph *irg = get_irn_irg(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *selector = get_Switch_selector(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op = be_transform_node(selector); + ir_mode *mode = get_irn_mode(selector); + const ir_switch_table *table = get_Switch_table(node); + unsigned n_outs = get_Switch_n_outs(node); - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - - pn = get_Proj_proj(proj); - - min = pnmax ? pn : max; - } - translation = min; - n_projs = max - translation + 1; + table = ir_switch_table_duplicate(irg, table); - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); + /* switch with smaller modes not implemented yet */ + assert(get_mode_size_bits(mode) == 32); - pn = get_Proj_proj(proj) - translation; - set_Proj_proj(proj, pn); - } - - const_graph = create_const_graph_value(dbgi, block, translation); - sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph); - return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation); + return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table); } static ir_node *gen_Cmp(ir_node *node) @@ -911,39 +1049,11 @@ static ir_node *gen_Cmp(ir_node *node) new_op2 = be_transform_node(op2); return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false); - - panic("FloatCmp NIY"); -#if 0 - ir_node *new_op2 = be_transform_node(op2); - /* floating point compare */ - pn_Cmp pnc = get_Proj_proj(selector); - - if (pnc & pn_Cmp_Uo) { - /* check for unordered, need cmf */ - return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc); - } - /* Hmm: use need cmfe */ - return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc); -#endif } assert(get_irn_mode(op2) == cmp_mode); is_unsigned = !mode_is_signed(cmp_mode); - /* compare with 0 can be done with Tst */ - if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) { - new_op1 = be_transform_node(op1); - new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); - return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false, - is_unsigned); - } - if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) { - new_op2 = be_transform_node(op2); - new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode); - return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true, - is_unsigned); - } - /* integer compare, TODO: use shifter_op in all its combinations */ new_op1 = be_transform_node(op1); new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); @@ -955,25 +1065,29 @@ static ir_node *gen_Cmp(ir_node *node) static ir_node *gen_Cond(ir_node *node) { - ir_node *selector = get_Cond_selector(node); - ir_mode *mode = get_irn_mode(selector); - ir_node *block; - ir_node *flag_node; - dbg_info *dbgi; + ir_node *selector = get_Cond_selector(node); + ir_relation relation; + ir_node *block; + ir_node *flag_node; + dbg_info *dbgi; - if (mode != mode_b) { - return gen_SwitchJmp(node); - } - assert(is_Proj(selector)); + assert(is_Cmp(selector)); block = be_transform_node(get_nodes_block(node)); dbgi = get_irn_dbg_info(node); - flag_node = be_transform_node(get_Proj_pred(selector)); + flag_node = be_transform_node(selector); + relation = get_Cmp_relation(selector); - return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector)); + return new_bd_arm_B(dbgi, block, flag_node, relation); } -static tarval *fpa_imm[3][fpa_max]; +enum fpa_imm_mode { + FPA_IMM_FLOAT = 0, + FPA_IMM_DOUBLE = 1, + FPA_IMM_MAX = FPA_IMM_DOUBLE +}; + +static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max]; #if 0 /** @@ -987,13 +1101,11 @@ static int is_fpa_immediate(tarval *tv) switch (get_mode_size_bits(mode)) { case 32: - i = 0; + i = FPA_IMM_FLOAT; break; case 64: - i = 1; + i = FPA_IMM_DOUBLE; break; - default: - i = 2; } if (tarval_is_negative(tv)) { @@ -1016,27 +1128,11 @@ static ir_node *gen_Const(ir_node *node) dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - env_cg->have_fp_insn = 1; - if (USE_FPA(env_cg->isa)) { - tarval *tv = get_Const_tarval(node); -#if 0 - int imm = is_fpa_immediate(tv); - - if (imm != fpa_max) { - if (imm > 0) { - node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm); - } else { - node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm); - } - } else -#endif - { - node = new_bd_arm_fpaConst(dbg, block, tv); - } - be_dep_on_frame(node); + if (USE_FPA(isa)) { + ir_tarval *tv = get_Const_tarval(node); + node = new_bd_arm_fConst(dbg, block, tv); return node; - } else if (USE_VFP(env_cg->isa)) { - assert(mode != mode_E && "IEEE Extended FP not supported"); + } else if (USE_VFP(isa)) { panic("VFP not supported yet"); } else { panic("Softfloat not supported yet"); @@ -1053,10 +1149,86 @@ static ir_node *gen_SymConst(ir_node *node) ir_node *new_node; new_node = new_bd_arm_SymConst(dbgi, block, entity, 0); - be_dep_on_frame(new_node); return new_node; } +static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0, + ir_node *node1) +{ + /* the good way to do this would be to use the stm (store multiple) + * instructions, since our input is nearly always 2 consecutive 32bit + * registers... */ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp, + NULL, 0, 0, true); + ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp, + NULL, 0, 4, true); + ir_node *in[2] = { str0, str1 }; + ir_node *sync = new_r_Sync(block, 2, in); + ir_node *ldf; + set_irn_pinned(str0, op_pin_state_floats); + set_irn_pinned(str1, op_pin_state_floats); + + ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true); + set_irn_pinned(ldf, op_pin_state_floats); + + return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res); +} + +static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp, + NULL, 0, 0, true); + ir_node *ldf; + set_irn_pinned(str, op_pin_state_floats); + + ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true); + set_irn_pinned(ldf, op_pin_state_floats); + + return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res); +} + +static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F, + NULL, 0, 0, true); + ir_node *ldr; + set_irn_pinned(stf, op_pin_state_floats); + + ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true); + set_irn_pinned(ldr, op_pin_state_floats); + + return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res); +} + +static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node, + ir_node **out_value0, ir_node **out_value1) +{ + ir_graph *irg = current_ir_graph; + ir_node *stack = get_irg_frame(irg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D, + NULL, 0, 0, true); + ir_node *ldr0, *ldr1; + set_irn_pinned(stf, op_pin_state_floats); + + ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true); + set_irn_pinned(ldr0, op_pin_state_floats); + ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true); + set_irn_pinned(ldr1, op_pin_state_floats); + + *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res); + *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res); +} + static ir_node *gen_CopyB(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); @@ -1071,8 +1243,8 @@ static ir_node *gen_CopyB(ir_node *node) ir_node *src_copy; ir_node *dst_copy; - src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src); - dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst); + src_copy = be_new_Copy(block, new_src); + dst_copy = be_new_Copy(block, new_dst); return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy, new_bd_arm_EmptyReg(dbg, block), @@ -1081,6 +1253,82 @@ static ir_node *gen_CopyB(ir_node *node) new_mem, size); } +/** + * Transform builtin clz. + */ +static ir_node *gen_clz(ir_node *node) +{ + ir_node *block = be_transform_node(get_nodes_block(node)); + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *op = get_irn_n(node, 1); + ir_node *new_op = be_transform_node(op); + + /* TODO armv5 instruction, otherwise create a call */ + return new_bd_arm_Clz(dbg, block, new_op); +} + +/** + * Transform Builtin node. + */ +static ir_node *gen_Builtin(ir_node *node) +{ + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_return_address: + case ir_bk_frame_address: + case ir_bk_prefetch: + case ir_bk_ffs: + break; + case ir_bk_clz: + return gen_clz(node); + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + case ir_bk_outport: + case ir_bk_inport: + case ir_bk_inner_trampoline: + break; + } + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); +} + +/** + * Transform Proj(Builtin) node. + */ +static ir_node *gen_Proj_Builtin(ir_node *proj) +{ + ir_node *node = get_Proj_pred(proj); + ir_node *new_node = be_transform_node(node); + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_return_address: + case ir_bk_frame_address: + case ir_bk_ffs: + case ir_bk_clz: + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + assert(get_Proj_proj(proj) == pn_Builtin_max+1); + return new_node; + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_prefetch: + case ir_bk_outport: + assert(get_Proj_proj(proj) == pn_Builtin_M); + return new_node; + case ir_bk_inport: + case ir_bk_inner_trampoline: + break; + } + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); +} + static ir_node *gen_Proj_Load(ir_node *node) { ir_node *load = get_Proj_pred(node); @@ -1098,12 +1346,12 @@ static ir_node *gen_Proj_Load(ir_node *node) return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M); } break; - case iro_arm_fpaLdf: + case iro_arm_Ldf: if (proj == pn_Load_res) { ir_mode *mode = get_Load_mode(load); - return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res); + return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M); + return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M); } break; default: @@ -1131,7 +1379,7 @@ static ir_node *gen_Proj_CopyB(ir_node *node) panic("Unsupported Proj from CopyB"); } -static ir_node *gen_Proj_Quot(ir_node *node) +static ir_node *gen_Proj_Div(ir_node *node) { ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -1140,49 +1388,20 @@ static ir_node *gen_Proj_Quot(ir_node *node) long proj = get_Proj_proj(node); switch (proj) { - case pn_Quot_M: - if (is_arm_fpaDvf(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M); - } else if (is_arm_fpaRdf(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M); - } else if (is_arm_fpaFdv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M); - } else if (is_arm_fpaFrd(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M); - } - break; - case pn_Quot_res: - if (is_arm_fpaDvf(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res); - } else if (is_arm_fpaRdf(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res); - } else if (is_arm_fpaFdv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res); - } else if (is_arm_fpaFrd(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res); - } - break; + case pn_Div_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M); + case pn_Div_res: + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res); default: break; } - panic("Unsupported Proj from Quot"); -} - -/** - * Transform the Projs from a Cmp. - */ -static ir_node *gen_Proj_Cmp(ir_node *node) -{ - (void) node; - /* we should only be here in case of a Mux node */ - panic("Mux NYI"); + panic("Unsupported Proj from Div"); } static ir_node *gen_Proj_Start(ir_node *node) { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *barrier = be_transform_node(get_Proj_pred(node)); long proj = get_Proj_proj(node); switch ((pn_Start) proj) { @@ -1191,26 +1410,25 @@ static ir_node *gen_Proj_Start(ir_node *node) return new_bd_arm_Jmp(NULL, new_block); case pn_Start_M: - return new_r_Proj(barrier, mode_M, 0); + return be_prolog_get_memory(abihelper); case pn_Start_T_args: - return barrier; + return new_r_Bad(get_irn_irg(block), mode_T); case pn_Start_P_frame_base: return be_prolog_get_reg_value(abihelper, sp_reg); - - case pn_Start_P_tls: - return new_bd_arm_LdTls(NULL, new_block); - - case pn_Start_max: - break; } panic("unexpected start proj: %ld\n", proj); } static ir_node *gen_Proj_Proj_Start(ir_node *node) { - long pn = get_Proj_proj(node); + long pn = get_Proj_proj(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_entity *entity = get_irg_entity(current_ir_graph); + ir_type *method_type = get_entity_type(entity); + ir_type *param_type = get_method_param_type(method_type, pn); const reg_or_stackslot_t *param; /* Proj->Proj->Start must be a method argument */ @@ -1220,18 +1438,50 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node) if (param->reg0 != NULL) { /* argument transmitted in register */ - return be_prolog_get_reg_value(abihelper, param->reg0); + ir_mode *mode = get_type_mode(param_type); + ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0); + + if (mode_is_float(mode)) { + ir_node *value1 = NULL; + + if (param->reg1 != NULL) { + value1 = be_prolog_get_reg_value(abihelper, param->reg1); + } else if (param->entity != NULL) { + ir_graph *irg = get_irn_irg(node); + ir_node *fp = get_irg_frame(irg); + ir_node *mem = be_prolog_get_memory(abihelper); + ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem, + mode_gp, param->entity, + 0, 0, true); + value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res); + } + + /* convert integer value to float */ + if (value1 == NULL) { + value = int_to_float(NULL, new_block, value); + } else { + value = ints_to_double(NULL, new_block, value, value1); + } + } + return value; } else { /* argument transmitted on stack */ - ir_graph *irg = get_irn_irg(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *fp = get_irg_frame(irg); - ir_node *mem = be_prolog_get_memory(abihelper); - ir_mode *mode = get_type_mode(param->type); - ir_node *load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode, - param->entity, 0, 0, true); - ir_node *value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res); + ir_graph *irg = get_irn_irg(node); + ir_node *fp = get_irg_frame(irg); + ir_node *mem = be_prolog_get_memory(abihelper); + ir_mode *mode = get_type_mode(param->type); + ir_node *load; + ir_node *value; + + if (mode_is_float(mode)) { + load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode, + param->entity, 0, 0, true); + value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res); + } else { + load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode, + param->entity, 0, 0, true); + value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res); + } set_irn_pinned(load, op_pin_state_floats); return value; @@ -1244,11 +1494,11 @@ static ir_node *gen_Proj_Proj_Start(ir_node *node) */ static int find_out_for_reg(ir_node *node, const arch_register_t *reg) { - int n_outs = arch_irn_get_n_outs(node); + int n_outs = arch_get_irn_n_outs(node); int o; for (o = 0; o < n_outs; ++o) { - const arch_register_req_t *req = arch_get_out_register_req(node, o); + const arch_register_req_t *req = arch_get_irn_register_req_out(node, o); if (req == reg->single_req) return o; } @@ -1261,7 +1511,8 @@ static ir_node *gen_Proj_Proj_Call(ir_node *node) ir_node *call = get_Proj_pred(get_Proj_pred(node)); ir_node *new_call = be_transform_node(call); ir_type *function_type = get_Call_type(call); - calling_convention_t *cconv = decide_calling_convention(function_type); + calling_convention_t *cconv + = arm_decide_calling_convention(NULL, function_type); const reg_or_stackslot_t *res = &cconv->results[pn]; ir_mode *mode; int regn; @@ -1274,7 +1525,7 @@ static ir_node *gen_Proj_Proj_Call(ir_node *node) } mode = res->reg0->reg_class->mode; - free_calling_convention(cconv); + arm_free_calling_convention(cconv); return new_r_Proj(new_call, mode, regn); } @@ -1291,8 +1542,6 @@ static ir_node *gen_Proj_Call(ir_node *node) case pn_Call_X_regular: case pn_Call_X_except: case pn_Call_T_result: - case pn_Call_P_value_res_base: - case pn_Call_max: break; } panic("Unexpected Call proj %ld\n", pn); @@ -1319,13 +1568,12 @@ static ir_node *gen_Proj(ir_node *node) return gen_Proj_Call(node); case iro_CopyB: return gen_Proj_CopyB(node); - case iro_Quot: - return gen_Proj_Quot(node); - case iro_Cmp: - return gen_Proj_Cmp(node); + case iro_Div: + return gen_Proj_Div(node); case iro_Start: return gen_Proj_Start(node); case iro_Cond: + case iro_Switch: /* nothing to do */ return be_duplicate_node(node); case iro_Proj: { @@ -1337,6 +1585,8 @@ static ir_node *gen_Proj(ir_node *node) } /* FALLTHROUGH */ } + case iro_Builtin: + return gen_Proj_Builtin(node); default: panic("code selection didn't expect Proj after %+F\n", pred); } @@ -1344,7 +1594,7 @@ static ir_node *gen_Proj(ir_node *node) typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block); -static inline ir_node *create_const(ir_node **place, +static inline ir_node *create_const(ir_graph *irg, ir_node **place, create_const_node_func func, const arch_register_t* reg) { @@ -1353,7 +1603,7 @@ static inline ir_node *create_const(ir_node **place, if (*place != NULL) return *place; - block = get_irg_start_block(env_cg->irg); + block = get_irg_start_block(irg); res = func(NULL, block); arch_set_irn_register(res, reg); *place = res; @@ -1369,10 +1619,9 @@ static ir_node *gen_Unknown(ir_node *node) /* just produce a 0 */ ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - tarval *tv = get_mode_null(mode); - ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv); - be_dep_on_frame(node); - return node; + ir_tarval *tv = get_mode_null(mode); + ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv); + return fconst; } else if (mode_needs_gp_reg(mode)) { return create_const_graph_value(dbgi, new_block, 0); } @@ -1434,10 +1683,8 @@ static void create_stacklayout(ir_graph *irg) layout->frame_type = get_irg_frame_type(irg); layout->between_type = arm_get_between_type(); layout->arg_type = arg_type; - layout->param_map = NULL; /* TODO */ layout->initial_offset = 0; layout->initial_bias = 0; - layout->stack_dir = -1; layout->sp_relative = true; assert(N_FRAME_TYPES == 3); @@ -1447,7 +1694,7 @@ static void create_stacklayout(ir_graph *irg) } /** - * transform the start node to the prolog code + initial barrier + * transform the start node to the prolog code */ static ir_node *gen_Start(ir_node *node) { @@ -1458,10 +1705,7 @@ static ir_node *gen_Start(ir_node *node) ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *start; - ir_node *incsp; - ir_node *sp; - ir_node *barrier; - int i; + size_t i; /* stackpointer is important at function prolog */ be_prolog_add_reg(abihelper, sp_reg, @@ -1470,29 +1714,23 @@ static ir_node *gen_Start(ir_node *node) for (i = 0; i < get_method_n_params(function_type); ++i) { const reg_or_stackslot_t *param = &cconv->parameters[i]; if (param->reg0 != NULL) - be_prolog_add_reg(abihelper, param->reg0, 0); + be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none); if (param->reg1 != NULL) - be_prolog_add_reg(abihelper, param->reg1, 0); + be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none); } /* announce that we need the values of the callee save regs */ - for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) { - be_prolog_add_reg(abihelper, callee_saves[i], 0); + for (i = 0; i != ARRAY_SIZE(callee_saves); ++i) { + be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none); } start = be_prolog_create_start(abihelper, dbgi, new_block); - sp = be_prolog_get_reg_value(abihelper, sp_reg); - incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0); - be_prolog_set_reg_value(abihelper, sp_reg, incsp); - barrier = be_prolog_create_barrier(abihelper, new_block); - - return barrier; + return start; } static ir_node *get_stack_pointer_for(ir_node *node) { /* get predecessor in stack_order list */ - ir_node *stack_pred = be_get_stack_pred(abihelper, node); - ir_node *stack_pred_transformed; + ir_node *stack_pred = be_get_stack_pred(stackorder, node); ir_node *stack; if (stack_pred == NULL) { @@ -1502,8 +1740,8 @@ static ir_node *get_stack_pointer_for(ir_node *node) return sp_proj; } - stack_pred_transformed = be_transform_node(stack_pred); - stack = pmap_get(node_to_stack, stack_pred); + be_transform_node(stack_pred); + stack = pmap_get(ir_node, node_to_stack, stack_pred); if (stack == NULL) { return get_stack_pointer_for(stack_pred); } @@ -1521,16 +1759,11 @@ static ir_node *gen_Return(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_node *mem = get_Return_mem(node); ir_node *new_mem = be_transform_node(mem); - int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]); + size_t n_callee_saves = ARRAY_SIZE(callee_saves); ir_node *sp_proj = get_stack_pointer_for(node); + size_t n_res = get_Return_n_ress(node); ir_node *bereturn; - ir_node *incsp; - int i; - int n_res; - const arch_register_t *const result_regs[] = { - &arm_gp_regs[REG_R0], - &arm_gp_regs[REG_R1] - }; + size_t i; be_epilog_begin(abihelper); be_epilog_set_memory(abihelper, new_mem); @@ -1541,35 +1774,24 @@ static ir_node *gen_Return(ir_node *node) sp_proj); /* result values */ - n_res = get_Return_n_ress(node); - if (n_res > (int) (sizeof(result_regs)/sizeof(result_regs[0]))) { - panic("Too many return values for arm backend (%+F)", node); - } for (i = 0; i < n_res; ++i) { - ir_node *res_value = get_Return_res(node, i); - ir_node *new_res_value = be_transform_node(res_value); - const arch_register_t *reg = result_regs[i]; - be_epilog_add_reg(abihelper, reg, 0, new_res_value); + ir_node *res_value = get_Return_res(node, i); + ir_node *new_res_value = be_transform_node(res_value); + const reg_or_stackslot_t *slot = &cconv->results[i]; + const arch_register_t *reg = slot->reg0; + assert(slot->reg1 == NULL); + be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value); } /* connect callee saves with their values at the function begin */ for (i = 0; i < n_callee_saves; ++i) { const arch_register_t *reg = callee_saves[i]; ir_node *value = be_prolog_get_reg_value(abihelper, reg); - be_epilog_add_reg(abihelper, reg, 0, value); + be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value); } - /* create the barrier before the epilog code */ - be_epilog_create_barrier(abihelper, new_block); - /* epilog code: an incsp */ - sp_proj = be_epilog_get_reg_value(abihelper, sp_reg); - incsp = be_new_IncSP(sp_reg, new_block, sp_proj, - BE_STACK_FRAME_SIZE_SHRINK, 0); - be_epilog_set_reg_value(abihelper, sp_reg, incsp); - bereturn = be_epilog_create_return(abihelper, dbgi, new_block); - return bereturn; } @@ -1584,27 +1806,26 @@ static ir_node *gen_Call(ir_node *node) ir_node *new_mem = be_transform_node(mem); dbg_info *dbgi = get_irn_dbg_info(node); ir_type *type = get_Call_type(node); - calling_convention_t *cconv = decide_calling_convention(type); - int n_params = get_Call_n_params(node); - int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]); + calling_convention_t *cconv = arm_decide_calling_convention(NULL, type); + size_t n_params = get_Call_n_params(node); + size_t const n_param_regs = cconv->n_reg_params; /* max inputs: memory, callee, register arguments */ - int max_inputs = 2 + n_param_regs; + size_t const max_inputs = 2 + n_param_regs; ir_node **in = ALLOCAN(ir_node*, max_inputs); ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs); struct obstack *obst = be_get_be_obst(irg); const arch_register_req_t **in_req = OALLOCNZ(obst, const arch_register_req_t*, max_inputs); - int in_arity = 0; - int sync_arity = 0; - int n_caller_saves - = sizeof(caller_saves)/sizeof(caller_saves[0]); - ir_entity *entity = NULL; - ir_node *incsp = NULL; + size_t in_arity = 0; + size_t sync_arity = 0; + size_t const n_caller_saves = ARRAY_SIZE(caller_saves); + ir_entity *entity = NULL; + ir_node *incsp = NULL; int mem_pos; ir_node *res; - int p; - int o; - int out_arity; + size_t p; + size_t o; + size_t out_arity; assert(n_params == get_method_n_params(type)); @@ -1616,35 +1837,61 @@ static ir_node *gen_Call(ir_node *node) ++in_arity; /* parameters */ for (p = 0; p < n_params; ++p) { - ir_node *value = get_Call_param(node, p); - ir_node *new_value = be_transform_node(value); - const reg_or_stackslot_t *param = &cconv->parameters[p]; - const arch_register_t *reg = param->reg0; - - /* double not implemented yet */ - assert(get_mode_size_bits(get_irn_mode(value)) <= 32); - assert(param->reg1 == NULL); - - if (reg != NULL) { - in[in_arity] = new_value; - /* this should not happen, LR cannot be a parameter register ... */ - assert(reg != &arm_gp_regs[REG_LR]); - in_req[in_arity] = reg->single_req; - ++in_arity; - } else { - ir_mode *mode; - ir_node *str; - if (incsp == NULL) { - /* create a parameter frame */ - ir_node *new_frame = get_stack_pointer_for(node); - incsp = be_new_IncSP(sp_reg, new_block, new_frame, cconv->param_stack_size, 1); + ir_node *value = get_Call_param(node, p); + ir_node *new_value = be_transform_node(value); + ir_node *new_value1 = NULL; + const reg_or_stackslot_t *param = &cconv->parameters[p]; + ir_type *param_type = get_method_param_type(type, p); + ir_mode *mode = get_type_mode(param_type); + ir_node *str; + + if (mode_is_float(mode) && param->reg0 != NULL) { + unsigned size_bits = get_mode_size_bits(mode); + if (size_bits == 64) { + double_to_ints(dbgi, new_block, new_value, &new_value, + &new_value1); + } else { + assert(size_bits == 32); + new_value = float_to_int(dbgi, new_block, new_value); } - mode = get_irn_mode(value); - str = new_bd_arm_Str(dbgi, new_block, incsp, value, new_mem, mode, - NULL, 0, param->offset, true); + } + + /* put value into registers */ + if (param->reg0 != NULL) { + in[in_arity] = new_value; + in_req[in_arity] = param->reg0->single_req; + ++in_arity; + if (new_value1 == NULL) + continue; + } + if (param->reg1 != NULL) { + assert(new_value1 != NULL); + in[in_arity] = new_value1; + in_req[in_arity] = param->reg1->single_req; + ++in_arity; + continue; + } + + /* we need a store if we're here */ + if (new_value1 != NULL) { + new_value = new_value1; + mode = mode_gp; + } - sync_ins[sync_arity++] = str; + /* create a parameter frame if necessary */ + if (incsp == NULL) { + ir_node *new_frame = get_stack_pointer_for(node); + incsp = be_new_IncSP(sp_reg, new_block, new_frame, + cconv->param_stack_size, 1); } + if (mode_is_float(mode)) { + str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem, + mode, NULL, 0, param->offset, true); + } else { + str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem, + mode, NULL, 0, param->offset, true); + } + sync_ins[sync_arity++] = str; } assert(in_arity <= max_inputs); @@ -1712,19 +1959,19 @@ static ir_node *gen_Call(ir_node *node) pmap_insert(node_to_stack, node, incsp); } - set_arm_in_req_all(res, in_req); + arch_set_irn_register_reqs_in(res, in_req); /* create output register reqs */ - arch_set_out_register_req(res, 0, arch_no_register_req); + arch_set_irn_register_req_out(res, 0, arch_no_register_req); for (o = 0; o < n_caller_saves; ++o) { const arch_register_t *reg = caller_saves[o]; - arch_set_out_register_req(res, o+1, reg->single_req); + arch_set_irn_register_req_out(res, o+1, reg->single_req); } /* copy pinned attribute */ set_irn_pinned(res, get_irn_pinned(node)); - free_calling_convention(cconv); + arm_free_calling_convention(cconv); return res; } @@ -1740,26 +1987,14 @@ static ir_node *gen_Sel(ir_node *node) /* must be the frame pointer all other sels must have been lowered * already */ assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr))); - /* we should not have value types from parameters anymore - they should be - lowered */ - assert(get_entity_owner(entity) != - get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node))))); return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0); } -/** - * Change some phi modes - */ static ir_node *gen_Phi(ir_node *node) { + ir_mode *mode = get_irn_mode(node); const arch_register_req_t *req; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *phi; - if (mode_needs_gp_reg(mode)) { /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); @@ -1770,21 +2005,9 @@ static ir_node *gen_Phi(ir_node *node) req = arch_no_register_req; } - /* phi nodes allow loops, so we use the old arguments for now - * and fix this later */ - phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), - get_irn_in(node) + 1); - copy_node_attr(irg, node, phi); - be_duplicate_deps(node, phi); - - arch_set_out_register_req(phi, 0, req); - - be_enqueue_preds(node); - - return phi; + return be_transform_phi(node, req); } - /** * Enters all transform functions into the generic pointer */ @@ -1792,7 +2015,6 @@ static void arm_register_transformers(void) { be_start_transform_setup(); - be_set_transform_function(op_Abs, gen_Abs); be_set_transform_function(op_Add, gen_Add); be_set_transform_function(op_And, gen_And); be_set_transform_function(op_Call, gen_Call); @@ -1801,6 +2023,7 @@ static void arm_register_transformers(void) be_set_transform_function(op_Const, gen_Const); be_set_transform_function(op_Conv, gen_Conv); be_set_transform_function(op_CopyB, gen_CopyB); + be_set_transform_function(op_Div, gen_Div); be_set_transform_function(op_Eor, gen_Eor); be_set_transform_function(op_Jmp, gen_Jmp); be_set_transform_function(op_Load, gen_Load); @@ -1810,7 +2033,6 @@ static void arm_register_transformers(void) be_set_transform_function(op_Or, gen_Or); be_set_transform_function(op_Phi, gen_Phi); be_set_transform_function(op_Proj, gen_Proj); - be_set_transform_function(op_Quot, gen_Quot); be_set_transform_function(op_Return, gen_Return); be_set_transform_function(op_Rotl, gen_Rotl); be_set_transform_function(op_Sel, gen_Sel); @@ -1820,8 +2042,10 @@ static void arm_register_transformers(void) be_set_transform_function(op_Start, gen_Start); be_set_transform_function(op_Store, gen_Store); be_set_transform_function(op_Sub, gen_Sub); + be_set_transform_function(op_Switch, gen_Switch); be_set_transform_function(op_SymConst, gen_SymConst); be_set_transform_function(op_Unknown, gen_Unknown); + be_set_transform_function(op_Builtin, gen_Builtin); } /** @@ -1830,68 +2054,63 @@ static void arm_register_transformers(void) static void arm_init_fpa_immediate(void) { /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */ - fpa_imm[0][fpa_null] = get_mode_null(mode_F); - fpa_imm[0][fpa_one] = get_mode_one(mode_F); - fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F); - fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F); - fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F); - fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F); - fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F); - fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); - - fpa_imm[1][fpa_null] = get_mode_null(mode_D); - fpa_imm[1][fpa_one] = get_mode_one(mode_D); - fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D); - fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D); - fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D); - fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D); - fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D); - fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); - - fpa_imm[2][fpa_null] = get_mode_null(mode_E); - fpa_imm[2][fpa_one] = get_mode_one(mode_E); - fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E); - fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E); - fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E); - fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E); - fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E); - fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E); + fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F); + fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); + + fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D); + fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); } /** * Transform a Firm graph into an ARM graph. */ -void arm_transform_graph(arm_code_gen_t *cg) +void arm_transform_graph(ir_graph *irg) { static int imm_initialized = 0; - ir_graph *irg = cg->irg; ir_entity *entity = get_irg_entity(irg); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); ir_type *frame_type; mode_gp = mode_Iu; + mode_fp = mode_F; if (! imm_initialized) { arm_init_fpa_immediate(); imm_initialized = 1; } arm_register_transformers(); - env_cg = cg; + + isa = (arm_isa_t*) arch_env; node_to_stack = pmap_create(); assert(abihelper == NULL); abihelper = be_abihelper_prepare(irg); - be_collect_stacknodes(abihelper); + stackorder = be_collect_stacknodes(irg); assert(cconv == NULL); - cconv = decide_calling_convention(get_entity_type(entity)); + cconv = arm_decide_calling_convention(irg, get_entity_type(entity)); create_stacklayout(irg); - be_transform_graph(cg->irg, NULL); + be_transform_graph(irg, NULL); be_abihelper_finish(abihelper); abihelper = NULL; + be_free_stackorder(stackorder); + stackorder = NULL; - free_calling_convention(cconv); + arm_free_calling_convention(cconv); cconv = NULL; frame_type = get_irg_frame_type(irg);