X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_transform.c;h=96353fb2cbf4e8c45f464d1215662afb1d1b1b42;hb=72fca46dfebc45e1c8466d0b7035a68b9d1495fe;hp=d1bc9b35debe24609c0a6e57022804d1ffbb493b;hpb=fdce0699d5d6ad23b9ce405e1a4fb9707fb9d51f;p=libfirm diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c index d1bc9b35d..96353fb2c 100644 --- a/ir/be/arm/arm_transform.c +++ b/ir/be/arm/arm_transform.c @@ -23,9 +23,7 @@ * @author Oliver Richter, Tobias Gneist, Michael Beck * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "irnode_t.h" #include "irgraph_t.h" @@ -40,14 +38,13 @@ #include "debug.h" #include "error.h" -#include "../benode_t.h" -#include "../beirg_t.h" +#include "../benode.h" +#include "../beirg.h" #include "../beutil.h" #include "../betranshlp.h" #include "bearch_arm_t.h" #include "arm_nodes_attr.h" -#include "archop.h" #include "arm_transform.h" #include "arm_optimize.h" #include "arm_new_nodes.h" @@ -57,91 +54,46 @@ #include +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) /** hold the current code generator during transformation */ static arm_code_gen_t *env_cg; -extern ir_op *get_op_Mulh(void); - - -/**************************************************************************************************** - * _ _ __ _ _ - * | | | | / _| | | (_) - * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __ - * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \ - * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | | - * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_| - * - ****************************************************************************************************/ - -static INLINE int mode_needs_gp_reg(ir_mode *mode) { +static inline int mode_needs_gp_reg(ir_mode *mode) +{ return mode_is_int(mode) || mode_is_reference(mode); } -/** - * Creates a arm_Const node. - */ -static ir_node *create_mov_node(dbg_info *dbg, ir_node *block, long value) { - ir_mode *mode = mode_Iu; - ir_graph *irg = current_ir_graph; - ir_node *res; - - if (mode_needs_gp_reg(mode)) - mode = mode_Iu; - res = new_rd_arm_Mov_i(dbg, irg, block, mode, value); - /* ensure the const is scheduled AFTER the stack frame */ - add_irn_dep(res, get_irg_frame(irg)); - return res; -} - -/** - * Creates a arm_Const_Neg node. - */ -static ir_node *create_mvn_node(dbg_info *dbg, ir_node *block, long value) { - ir_mode *mode = mode_Iu; - ir_graph *irg = current_ir_graph; - ir_node *res; - - if (mode_needs_gp_reg(mode)) - mode = mode_Iu; - res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value); - /* ensure the const is scheduled AFTER the stack frame */ - add_irn_dep(res, get_irg_frame(irg)); - return res; -} - -#define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode) - /** * Creates a possible DAG for an constant. */ -static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) { +static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block, + unsigned int value) +{ ir_node *result; arm_vals v, vn; int cnt; - ir_mode *mode = mode_Iu; arm_gen_vals_from_word(value, &v); arm_gen_vals_from_word(~value, &vn); if (vn.ops < v.ops) { /* remove bits */ - result = create_mvn_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0])); + result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]); + be_dep_on_frame(result); for (cnt = 1; cnt < vn.ops; ++cnt) { - long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]); - ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value); - result = bic_i_node; + result = new_bd_arm_Bic_imm(dbgi, block, result, + vn.values[cnt], vn.rors[cnt]); } - } - else { + } else { /* add bits */ - result = create_mov_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0])); + result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]); + be_dep_on_frame(result); for (cnt = 1; cnt < v.ops; ++cnt) { - long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]); - ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value); - result = orr_i_node; + result = new_bd_arm_Or_imm(dbgi, block, result, + v.values[cnt], v.rors[cnt]); } } return result; @@ -152,10 +104,11 @@ static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned * * @param irn a Firm const */ -static ir_node *create_const_graph(ir_node *irn, ir_node *block) { +static ir_node *create_const_graph(ir_node *irn, ir_node *block) +{ tarval *tv = get_Const_tarval(irn); ir_mode *mode = get_tarval_mode(tv); - int value; + unsigned value; if (mode_is_reference(mode)) { /* ARM is 32bit, so we can safely convert a reference tarval into Iu */ @@ -167,36 +120,77 @@ static ir_node *create_const_graph(ir_node *irn, ir_node *block) { } /** - * Create an And that will mask all upper bits + * Create an And that will zero out upper bits. + * + * @param dbgi debug info + * @param block the basic block + * @param op the original node + * param src_bits number of lower bits that will remain */ -static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) { - unsigned mask_bits = (1 << result_bits) - 1; - ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits); - return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0); +static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op, + int src_bits) +{ + if (src_bits == 8) { + return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0); + } else if (src_bits == 16) { + ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16); + ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16); + return rshift; + } else { + panic("zero extension only supported for 8 and 16 bits"); + } } /** * Generate code for a sign extension. */ -static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) { - ir_graph *irg = current_ir_graph; - int shift_width = 32 - result_bits; - ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width); - ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu); - ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu); +static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op, + int src_bits) +{ + int shift_width = 32 - src_bits; + ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width); + ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width); return rshift_node; } +static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op, + ir_mode *orig_mode) +{ + int bits = get_mode_size_bits(orig_mode); + if (bits == 32) + return op; + + if (mode_is_signed(orig_mode)) { + return gen_sign_extension(dbgi, block, op, bits); + } else { + return gen_zero_extension(dbgi, block, op, bits); + } +} + +/** + * returns true if it is assured, that the upper bits of a node are "clean" + * which means for a 16 or 8 bit value, that the upper bits in the register + * are 0 for unsigned and a copy of the last significant bit for signed + * numbers. + */ +static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode) +{ + (void) transformed_node; + (void) mode; + /* TODO */ + return false; +} + /** * Transforms a Conv node. * * @return The created ia32 Conv node */ -static ir_node *gen_Conv(ir_node *node) { +static ir_node *gen_Conv(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; ir_mode *src_mode = get_irn_mode(op); ir_mode *dst_mode = get_irn_mode(node); dbg_info *dbg = get_irn_dbg_info(node); @@ -211,82 +205,172 @@ static ir_node *gen_Conv(ir_node *node) { if (mode_is_float(src_mode)) { if (mode_is_float(dst_mode)) { /* from float to float */ - return new_rd_arm_fpaMvf(dbg, irg, block, new_op, dst_mode); + return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode); } else { /* from float to int */ - return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode); + return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode); } } else { /* from int to float */ - return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode); + return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode); } + } else if (USE_VFP(env_cg->isa)) { + panic("VFP not supported yet"); + } else { + panic("Softfloat not supported yet"); } - else if (USE_VFP(env_cg->isa)) { - panic("VFP not supported yet\n"); - return NULL; - } - else { - panic("Softfloat not supported yet\n"); - return NULL; - } - } - else { /* complete in gp registers */ + } else { /* complete in gp registers */ int src_bits = get_mode_size_bits(src_mode); int dst_bits = get_mode_size_bits(dst_mode); int min_bits; ir_mode *min_mode; - if (is_Load(skip_Proj(op))) { - if (src_bits == dst_bits) { - /* kill unneccessary conv */ - return new_op; - } - /* after a load, the bit size is already converted */ - src_bits = 32; - } - if (src_bits == dst_bits) { /* kill unneccessary conv */ return new_op; - } else if (dst_bits <= 32 && src_bits <= 32) { - if (src_bits < dst_bits) { - min_bits = src_bits; - min_mode = src_mode; - } else { - min_bits = dst_bits; - min_mode = dst_mode; - } - if (mode_is_signed(min_mode)) { - return gen_sign_extension(dbg, block, new_op, min_bits); - } else { - return gen_zero_extension(dbg, block, new_op, min_bits); - } + } + + if (src_bits < dst_bits) { + min_bits = src_bits; + min_mode = src_mode; } else { - panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode, - src_bits, dst_bits); - return NULL; + min_bits = dst_bits; + min_mode = dst_mode; + } + + if (upper_bits_clean(new_op, min_mode)) { + return new_op; + } + + if (mode_is_signed(min_mode)) { + return gen_sign_extension(dbg, block, new_op, min_bits); + } else { + return gen_zero_extension(dbg, block, new_op, min_bits); } } } -/** - * Return true if an operand is a shifter operand - */ -static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) { - arm_shift_modifier mod = ARM_SHF_NONE; +typedef struct { + unsigned char imm_8; + unsigned char rot; +} arm_immediate_t; + +static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res) +{ + unsigned val, low_pos, high_pos; - if (is_arm_Mov(n)) - mod = get_arm_shift_modifier(n); + if (!is_Const(node)) + return false; + + val = get_tarval_long(get_Const_tarval(node)); + + if (val == 0) { + res->imm_8 = 0; + res->rot = 0; + return true; + } + if (val <= 0xff) { + res->imm_8 = val; + res->rot = 0; + return true; + } + /* arm allows to use to rotate an 8bit immediate value by a multiple of 2 + (= 0, 2, 4, 6, ...). + So we determine the smallest even position with a bit set + and the highest even position with no bit set anymore. + If the difference between these 2 is <= 8, then we can encode the value + as immediate. + */ + low_pos = ntz(val) & ~1u; + high_pos = (32-nlz(val)+1) & ~1u; + + if (high_pos - low_pos <= 8) { + res->imm_8 = val >> low_pos; + res->rot = 32 - low_pos; + return true; + } - *pmod = mod; - if (mod != ARM_SHF_NONE) { - long v = get_arm_imm_value(n); - if (v < 32) - return (int)v; + if (high_pos > 24) { + res->rot = 34 - high_pos; + val = val >> (32-res->rot) | val << (res->rot); + if (val <= 0xff) { + res->imm_8 = val; + return true; + } } - return 0; + + return false; +} + +static int is_downconv(const ir_node *node) +{ + ir_mode *src_mode; + ir_mode *dest_mode; + + if (!is_Conv(node)) + return 0; + + /* we only want to skip the conv when we're the only user + * (not optimal but for now...) + */ + if (get_irn_n_edges(node) > 1) + return 0; + + src_mode = get_irn_mode(get_Conv_op(node)); + dest_mode = get_irn_mode(node); + return + mode_needs_gp_reg(src_mode) && + mode_needs_gp_reg(dest_mode) && + get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode); +} + +static ir_node *arm_skip_downconv(ir_node *node) +{ + while (is_downconv(node)) + node = get_Conv_op(node); + return node; +} + +typedef enum { + MATCH_NONE = 0, + MATCH_COMMUTATIVE = 1 << 0, + MATCH_SIZE_NEUTRAL = 1 << 1, +} match_flags_t; + +typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2); +typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot); + +static ir_node *gen_int_binop(ir_node *node, match_flags_t flags, + new_binop_reg_func new_reg, new_binop_imm_func new_imm) +{ + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_binop_left(node); + ir_node *new_op1; + ir_node *op2 = get_binop_right(node); + ir_node *new_op2; + dbg_info *dbgi = get_irn_dbg_info(node); + arm_immediate_t imm; + + if (flags & MATCH_SIZE_NEUTRAL) { + op1 = arm_skip_downconv(op1); + op2 = arm_skip_downconv(op2); + } else { + assert(get_mode_size_bits(get_irn_mode(node)) == 32); + } + + if (try_encode_as_immediate(op2, &imm)) { + ir_node *new_op1 = be_transform_node(op1); + return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot); + } + new_op2 = be_transform_node(op2); + if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) { + return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot); + } + new_op1 = be_transform_node(op1); + + return new_reg(dbgi, block, new_op1, new_op2); } /** @@ -294,76 +378,54 @@ static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) { * * @return the created arm Add node */ -static ir_node *gen_Add(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Add_left(node); - ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Add_right(node); - ir_node *new_op2 = be_transform_node(op2); +static ir_node *gen_Add(ir_node *node) +{ ir_mode *mode = get_irn_mode(node); - ir_graph *irg = current_ir_graph; - ir_node *new_op3; - int v; - arm_shift_modifier mod; - dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Add_left(node); + ir_node *op2 = get_Add_right(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *new_op2 = be_transform_node(op2); env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { +#if 0 if (is_arm_fpaMvf_i(new_op1)) - return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_fpaMvf_i(new_op2)) - return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); - return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode); + return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); +#endif + return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); - return NULL; + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); - return NULL; + panic("Softfloat not supported yet"); } } else { - assert(mode_is_data(mode)); - mode = mode_Iu; - - if (is_arm_Mov_i(new_op1)) - return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); - +#if 0 /* check for MLA */ if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) { new_op3 = new_op2; new_op2 = get_irn_n(new_op1, 1); new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode); + return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3); } if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) { new_op3 = new_op1; new_op1 = get_irn_n(new_op2, 0); new_op2 = get_irn_n(new_op2, 1); - return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode); - } - - /* is the first a shifter */ - v = is_shifter_operand(new_op1, &mod); - if (v) { - new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v); - } - /* is the second a shifter */ - v = is_shifter_operand(new_op2, &mod); - if (v) { - new_op2 = get_irn_n(new_op2, 0); - return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v); + return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3); } +#endif - /* normal ADD */ - return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, + new_bd_arm_Add_reg, new_bd_arm_Add_imm); } } @@ -372,38 +434,37 @@ static ir_node *gen_Add(ir_node *node) { * * @return the created arm Mul node */ -static ir_node *gen_Mul(ir_node *node) { +static ir_node *gen_Mul(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_Mul_left(node); ir_node *new_op1 = be_transform_node(op1); ir_node *op2 = get_Mul_right(node); ir_node *new_op2 = be_transform_node(op2); ir_mode *mode = get_irn_mode(node); - ir_graph *irg = current_ir_graph; dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { +#if 0 if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); - return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode); + return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); +#endif + return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); - return NULL; + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); - return NULL; + panic("Softfloat not supported yet"); } } assert(mode_is_data(mode)); - mode = mode_Iu; - return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode); + return new_bd_arm_Mul(dbg, block, new_op1, new_op2); } /** @@ -412,7 +473,8 @@ static ir_node *gen_Mul(ir_node *node) { * @param env The transformation environment * @return the created arm fDiv node */ -static ir_node *gen_Quot(ir_node *node) { +static ir_node *gen_Quot(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_Quot_left(node); ir_node *new_op1 = be_transform_node(op1); @@ -425,59 +487,31 @@ static ir_node *gen_Quot(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { +#if 0 if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1)); + return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2)); - return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode); + return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); +#endif + return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); - return NULL; + panic("Softfloat not supported yet"); } } -#define GEN_INT_OP(op) \ - ir_node *block = be_transform_node(get_nodes_block(node)); \ - ir_node *op1 = get_ ## op ## _left(node); \ - ir_node *new_op1 = be_transform_node(op1); \ - ir_node *op2 = get_ ## op ## _right(node); \ - ir_node *new_op2 = be_transform_node(op2); \ - ir_graph *irg = current_ir_graph; \ - ir_mode *mode = mode_Iu; \ - dbg_info *dbg = get_irn_dbg_info(node); \ - int v; \ - arm_shift_modifier mod; \ - \ - if (is_arm_Mov_i(new_op1)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \ - if (is_arm_Mov_i(new_op2)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \ - /* is the first a shifter */ \ - v = is_shifter_operand(new_op1, &mod); \ - if (v) { \ - new_op1 = get_irn_n(new_op1, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \ - } \ - /* is the second a shifter */ \ - v = is_shifter_operand(new_op2, &mod); \ - if (v) { \ - new_op2 = get_irn_n(new_op2, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \ - } \ - /* Normal op */ \ - return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \ - /** * Creates an ARM And. * * @return the created arm And node */ -static ir_node *gen_And(ir_node *node) { - GEN_INT_OP(And); +static ir_node *gen_And(ir_node *node) +{ + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, + new_bd_arm_And_reg, new_bd_arm_And_imm); } /** @@ -486,8 +520,10 @@ static ir_node *gen_And(ir_node *node) { * @param env The transformation environment * @return the created arm Or node */ -static ir_node *gen_Or(ir_node *node) { - GEN_INT_OP(Or); +static ir_node *gen_Or(ir_node *node) +{ + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, + new_bd_arm_Or_reg, new_bd_arm_Or_imm); } /** @@ -495,8 +531,10 @@ static ir_node *gen_Or(ir_node *node) { * * @return the created arm Eor node */ -static ir_node *gen_Eor(ir_node *node) { - GEN_INT_OP(Eor); +static ir_node *gen_Eor(ir_node *node) +{ + return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, + new_bd_arm_Eor_reg, new_bd_arm_Eor_imm); } /** @@ -504,60 +542,55 @@ static ir_node *gen_Eor(ir_node *node) { * * @return the created arm Sub node */ -static ir_node *gen_Sub(ir_node *node) { +static ir_node *gen_Sub(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op1 = get_Sub_left(node); ir_node *new_op1 = be_transform_node(op1); ir_node *op2 = get_Sub_right(node); ir_node *new_op2 = be_transform_node(op2); ir_mode *mode = get_irn_mode(node); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(node); - int v; - arm_shift_modifier mod; + dbg_info *dbgi = get_irn_dbg_info(node); if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { +#if 0 if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); - return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode); + return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2)); +#endif + return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); - return NULL; - } - else { - panic("Softfloat not supported yet\n"); - return NULL; + panic("VFP not supported yet"); + } else { + panic("Softfloat not supported yet"); } + } else { + return gen_int_binop(node, MATCH_SIZE_NEUTRAL, + new_bd_arm_Sub_reg, new_bd_arm_Sub_imm); } - else { - assert(mode_is_data(mode) && "unknown mode for Sub"); - mode = mode_Iu; - - if (is_arm_Mov_i(new_op1)) - return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); - if (is_arm_Mov_i(new_op2)) - return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); +} - /* is the first a shifter */ - v = is_shifter_operand(new_op1, &mod); - if (v) { - new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v); - } - /* is the second a shifter */ - v = is_shifter_operand(new_op2, &mod); - if (v) { - new_op2 = get_irn_n(new_op2, 0); - return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v); - } - /* normal sub */ - return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); +static ir_node *make_shift(ir_node *node, match_flags_t flags, + arm_shift_modifier shift_modifier) +{ + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_binop_left(node); + ir_node *op2 = get_binop_right(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op1; + ir_node *new_op2; + + if (flags & MATCH_SIZE_NEUTRAL) { + op1 = arm_skip_downconv(op1); + op2 = arm_skip_downconv(op2); } + new_op1 = be_transform_node(op1); + new_op2 = be_transform_node(op2); + return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, shift_modifier); } /** @@ -565,19 +598,9 @@ static ir_node *gen_Sub(ir_node *node) { * * @return the created ARM Shl node */ -static ir_node *gen_Shl(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Shl_left(node); - ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Shl_right(node); - ir_node *new_op2 = be_transform_node(op2); - ir_mode *mode = mode_Iu; - dbg_info *dbg = get_irn_dbg_info(node); - - if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2)); - } - return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode); +static ir_node *gen_Shl(ir_node *node) +{ + return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG); } /** @@ -585,39 +608,118 @@ static ir_node *gen_Shl(ir_node *node) { * * @return the created ARM Shr node */ -static ir_node *gen_Shr(ir_node *node) { +static ir_node *gen_Shr(ir_node *node) +{ + return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG); +} + +/** + * Creates an ARM Shrs. + * + * @return the created ARM Shrs node + */ +static ir_node *gen_Shrs(ir_node *node) +{ + return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG); +} + +/** + * Creates an ARM Ror. + * + * @return the created ARM Ror node + */ +static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) +{ ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Shr_left(node); ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Shr_right(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_op2 = be_transform_node(op2); - ir_mode *mode = mode_Iu; - dbg_info *dbg = get_irn_dbg_info(node); - if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2)); - } - return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode); + return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, + ARM_SHF_ROR_REG); } /** - * Creates an ARM Shrs. + * Creates an ARM Rol. * - * @return the created ARM Shrs node + * @return the created ARM Rol node + * + * Note: there is no Rol on arm, we have to use Ror */ -static ir_node *gen_Shrs(ir_node *node) { +static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) +{ ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Shrs_left(node); ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Shrs_right(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_op2 = be_transform_node(op2); - ir_mode *mode = mode_Iu; - dbg_info *dbg = get_irn_dbg_info(node); - if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2)); + new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0); + return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, + ARM_SHF_ROR_REG); +} + +/** + * Creates an ARM ROR from a Firm Rotl. + * + * @return the created ARM Ror node + */ +static ir_node *gen_Rotl(ir_node *node) +{ + ir_node *rotate = NULL; + ir_node *op1 = get_Rotl_left(node); + ir_node *op2 = get_Rotl_right(node); + + /* Firm has only RotL, so we are looking for a right (op2) + operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e", + that means we can create a RotR. */ + + if (is_Add(op2)) { + ir_node *right = get_Add_right(op2); + if (is_Const(right)) { + tarval *tv = get_Const_tarval(right); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *left = get_Add_left(op2); + + if (is_Minus(left) && + tarval_is_long(tv) && + get_tarval_long(tv) == bits && + bits == 32) + rotate = gen_Ror(node, op1, get_Minus_op(left)); + } + } else if (is_Sub(op2)) { + ir_node *left = get_Sub_left(op2); + if (is_Const(left)) { + tarval *tv = get_Const_tarval(left); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + ir_node *right = get_Sub_right(op2); + + if (tarval_is_long(tv) && + get_tarval_long(tv) == bits && + bits == 32) + rotate = gen_Ror(node, op1, right); + } + } else if (is_Const(op2)) { + tarval *tv = get_Const_tarval(op2); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); + + if (tarval_is_long(tv) && bits == 32) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *new_op1 = be_transform_node(op1); + dbg_info *dbgi = get_irn_dbg_info(node); + + bits = (bits - get_tarval_long(tv)) & 31; + rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits); + } } - return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode); + + if (rotate == NULL) { + rotate = gen_Rol(node, op1, op2); + } + + return rotate; } /** @@ -625,19 +727,16 @@ static ir_node *gen_Shrs(ir_node *node) { * * @return the created ARM Not node */ -static ir_node *gen_Not(ir_node *node) { +static ir_node *gen_Not(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Not_op(node); ir_node *new_op = be_transform_node(op); - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = mode_Iu; - arm_shift_modifier mod = ARM_SHF_NONE; - int v = is_shifter_operand(new_op, &mod); + dbg_info *dbgi = get_irn_dbg_info(node); - if (v) { - new_op = get_irn_n(new_op, 0); - } - return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v); + /* TODO: we could do alot more here with all the Mvn variations */ + + return new_bd_arm_Mvn_reg(dbgi, block, new_op); } /** @@ -646,28 +745,28 @@ static ir_node *gen_Not(ir_node *node) { * @param env The transformation environment * @return the created ARM Abs node */ -static ir_node *gen_Abs(ir_node *node) { +static ir_node *gen_Abs(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Abs_op(node); ir_node *new_op = be_transform_node(op); - dbg_info *dbg = get_irn_dbg_info(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) - return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode); + return new_bd_arm_fpaAbs(dbgi, block, new_op, mode); else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); + panic("Softfloat not supported yet"); } } assert(mode_is_data(mode)); - mode = mode_Iu; - return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode); + return new_bd_arm_Abs(dbgi, block, new_op); } /** @@ -675,28 +774,28 @@ static ir_node *gen_Abs(ir_node *node) { * * @return the created ARM Minus node */ -static ir_node *gen_Minus(ir_node *node) { +static ir_node *gen_Minus(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Minus_op(node); ir_node *new_op = be_transform_node(op); - dbg_info *dbg = get_irn_dbg_info(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) - return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode); + return new_bd_arm_fpaMvf(dbgi, block, op, mode); else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); + panic("Softfloat not supported yet"); } } assert(mode_is_data(mode)); - mode = mode_Iu; - return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0); + return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0); } /** @@ -704,71 +803,39 @@ static ir_node *gen_Minus(ir_node *node) { * * @return the created ARM Load node */ -static ir_node *gen_Load(ir_node *node) { +static ir_node *gen_Load(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *ptr = get_Load_ptr(node); ir_node *new_ptr = be_transform_node(ptr); ir_node *mem = get_Load_mem(node); ir_node *new_mem = be_transform_node(mem); ir_mode *mode = get_Load_mode(node); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_load = NULL; if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) - new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode); + new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode); else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); - } - else { - panic("Softfloat not supported yet\n"); + panic("VFP not supported yet"); + } else { + panic("Softfloat not supported yet"); } - } - else { + } else { assert(mode_is_data(mode) && "unsupported mode for Load"); - if (mode_is_signed(mode)) { - /* sign extended loads */ - switch (get_mode_size_bits(mode)) { - case 8: - new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem); - break; - case 16: - new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem); - break; - case 32: - new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem); - break; - default: - panic("mode size not supported\n"); - } - } else { - /* zero extended loads */ - switch (get_mode_size_bits(mode)) { - case 8: - new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem); - break; - case 16: - new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem); - break; - case 32: - new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem); - break; - default: - panic("mode size not supported\n"); - } - } + new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false); } set_irn_pinned(new_load, get_irn_pinned(node)); /* check for special case: the loaded value might not be used */ if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) { /* add a result proj and a Keep to produce a pseudo use */ - ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res); - be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj); + ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res); + be_new_Keep(block, 1, &proj); } return new_load; @@ -779,7 +846,8 @@ static ir_node *gen_Load(ir_node *node) { * * @return the created ARM Store node */ -static ir_node *gen_Store(ir_node *node) { +static ir_node *gen_Store(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *ptr = get_Store_ptr(node); ir_node *new_ptr = be_transform_node(ptr); @@ -788,140 +856,176 @@ static ir_node *gen_Store(ir_node *node) { ir_node *val = get_Store_value(node); ir_node *new_val = be_transform_node(val); ir_mode *mode = get_irn_mode(val); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(node); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_store = NULL; if (mode_is_float(mode)) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) - new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode); + new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val, + new_mem, mode); else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); + panic("Softfloat not supported yet"); } } else { assert(mode_is_data(mode) && "unsupported mode for Store"); - switch (get_mode_size_bits(mode)) { - case 8: - new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem); - case 16: - new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem); - default: - new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem); - } + new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode, + NULL, 0, 0, false); } set_irn_pinned(new_store, get_irn_pinned(node)); return new_store; } -/** - * Transforms a Cond. - * - * @return the created ARM Cond node - */ -static ir_node *gen_Cond(ir_node *node) { +static ir_node *gen_Jmp(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + + return new_bd_arm_Jmp(dbgi, new_block); +} + +static ir_node *gen_be_Call(ir_node *node) +{ + ir_node *res = be_duplicate_node(node); + arch_irn_add_flags(res, arch_irn_flags_modify_flags); + + return res; +} + +static ir_node *gen_SwitchJmp(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *selector = get_Cond_selector(node); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(selector); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op = be_transform_node(selector); + ir_node *const_graph; + ir_node *sub; + + ir_node *proj; + const ir_edge_t *edge; + int min = INT_MAX; + int max = INT_MIN; + int translation; + int pn; + int n_projs; + + foreach_out_edge(node, edge) { + proj = get_edge_src_irn(edge); + assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); + + pn = get_Proj_proj(proj); + + min = pnmax ? pn : max; + } + translation = min; + n_projs = max - translation + 1; - if (mode == mode_b) { - /* an conditional jump */ - ir_node *cmp_node = get_Proj_pred(selector); - ir_node *op1 = get_Cmp_left(cmp_node); - ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_Cmp_right(cmp_node); - ir_node *new_op2 = be_transform_node(op2); + foreach_out_edge(node, edge) { + proj = get_edge_src_irn(edge); + assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - if (mode_is_float(get_irn_mode(op1))) { - /* floating point compare */ - pn_Cmp pnc = get_Proj_proj(selector); + pn = get_Proj_proj(proj) - translation; + set_Proj_proj(proj, pn); + } - if (pnc & pn_Cmp_Uo) { - /* check for unordered, need cmf */ - return new_rd_arm_fpaCmfBra(dbg, irg, block, new_op1, new_op2, pnc); - } - /* Hmm: use need cmfe */ - return new_rd_arm_fpaCmfeBra(dbg, irg, block, new_op1, new_op2, pnc); - } else { - /* integer compare */ - return new_rd_arm_CmpBra(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector)); - } - } else { - /* SwitchJmp */ - ir_node *new_op = be_transform_node(selector); - ir_node *const_graph; - ir_node *sub; - - ir_node *proj; - const ir_edge_t *edge; - int min = INT_MAX; - int max = INT_MIN; - int translation; - int pn; - int n_projs; - - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - - pn = get_Proj_proj(proj); - - min = pnmax ? pn : max; - } - translation = min; - n_projs = max - translation + 1; + const_graph = create_const_graph_value(dbgi, block, translation); + sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph); + return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation); +} + +static ir_node *gen_Cmp(ir_node *node) +{ + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Cmp_left(node); + ir_node *op2 = get_Cmp_right(node); + ir_mode *cmp_mode = get_irn_mode(op1); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_op1; + ir_node *new_op2; + bool is_unsigned; - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); + if (mode_is_float(cmp_mode)) { + /* TODO: revivie this code */ + panic("FloatCmp NIY"); +#if 0 + ir_node *new_op2 = be_transform_node(op2); + /* floating point compare */ + pn_Cmp pnc = get_Proj_proj(selector); - pn = get_Proj_proj(proj) - translation; - set_Proj_proj(proj, pn); + if (pnc & pn_Cmp_Uo) { + /* check for unordered, need cmf */ + return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc); } + /* Hmm: use need cmfe */ + return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc); +#endif + } + + assert(get_irn_mode(op2) == cmp_mode); + is_unsigned = !mode_is_signed(cmp_mode); - const_graph = create_const_graph_value(dbg, block, translation); - sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0); - return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation); + /* compare with 0 can be done with Tst */ + if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) { + new_op1 = be_transform_node(op1); + new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); + return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false, + is_unsigned); + } + if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) { + new_op2 = be_transform_node(op2); + new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode); + return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true, + is_unsigned); } + + /* integer compare, TODO: use shifer_op in all its combinations */ + new_op1 = be_transform_node(op1); + new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode); + new_op2 = be_transform_node(op2); + new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode); + return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false, + is_unsigned); } /** - * Returns the name of a SymConst. - * @param symc the SymConst - * @return name of the SymConst + * Transforms a Cond. + * + * @return the created ARM Cond node */ -static ident *get_sc_ident(ir_node *symc) { - ir_entity *ent; - - switch (get_SymConst_kind(symc)) { - case symconst_addr_name: - return get_SymConst_name(symc); - - case symconst_addr_ent: - ent = get_SymConst_entity(symc); - set_entity_backend_marked(ent, 1); - return get_entity_ld_ident(ent); +static ir_node *gen_Cond(ir_node *node) +{ + ir_node *selector = get_Cond_selector(node); + ir_mode *mode = get_irn_mode(selector); + ir_node *block; + ir_node *flag_node; + dbg_info *dbgi; - default: - assert(0 && "Unsupported SymConst"); + if (mode != mode_b) { + return gen_SwitchJmp(node); } + assert(is_Proj(selector)); - return NULL; + block = be_transform_node(get_nodes_block(node)); + dbgi = get_irn_dbg_info(node); + flag_node = be_transform_node(get_Proj_pred(selector)); + + return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector)); } static tarval *fpa_imm[3][fpa_max]; +#if 0 /** * Check, if a floating point tarval is an fpa immediate, i.e. * one of 0, 1, 2, 3, 4, 5, 10, or 0.5. */ -static int is_fpa_immediate(tarval *tv) { +static int is_fpa_immediate(tarval *tv) +{ ir_mode *mode = get_tarval_mode(tv); int i, j, res = 1; @@ -936,7 +1040,7 @@ static int is_fpa_immediate(tarval *tv) { i = 2; } - if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) { + if (tarval_is_negative(tv)) { tv = tarval_neg(tv); res = -1; } @@ -947,15 +1051,16 @@ static int is_fpa_immediate(tarval *tv) { } return fpa_max; } +#endif /** * Transforms a Const node. * * @return The transformed ARM node. */ -static ir_node *gen_Const(ir_node *node) { +static ir_node *gen_Const(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; ir_mode *mode = get_irn_mode(node); dbg_info *dbg = get_irn_dbg_info(node); @@ -963,26 +1068,28 @@ static ir_node *gen_Const(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { tarval *tv = get_Const_tarval(node); +#if 0 int imm = is_fpa_immediate(tv); if (imm != fpa_max) { if (imm > 0) - node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm); + node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm); else - node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm); + node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm); } else { - node = new_rd_arm_fpaConst(dbg, irg, block, tv); +#endif + { + node = new_bd_arm_fpaConst(dbg, block, tv); } - /* ensure the const is scheduled AFTER the stack frame */ - add_irn_dep(node, get_irg_frame(irg)); + be_dep_on_frame(node); return node; } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); - panic("VFP not supported yet\n"); + panic("VFP not supported yet"); } else { - panic("Softfloat not supported yet\n"); + panic("Softfloat not supported yet"); } } return create_const_graph(node, block); @@ -993,17 +1100,16 @@ static ir_node *gen_Const(ir_node *node) { * * @return The transformed ARM node. */ -static ir_node *gen_SymConst(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_mode *mode = mode_Iu; - dbg_info *dbg = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *res; +static ir_node *gen_SymConst(ir_node *node) +{ + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_entity *entity = get_SymConst_entity(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; - res = new_rd_arm_SymConst(dbg, irg, block, mode, get_sc_ident(node)); - /* ensure the const is scheduled AFTER the stack frame */ - add_irn_dep(res, get_irg_frame(irg)); - return res; + new_node = new_bd_arm_SymConst(dbgi, block, entity); + be_dep_on_frame(new_node); + return new_node; } /** @@ -1011,7 +1117,8 @@ static ir_node *gen_SymConst(ir_node *node) { * * @return The transformed ARM node. */ -static ir_node *gen_CopyB(ir_node *node) { +static ir_node *gen_CopyB(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *src = get_CopyB_src(node); ir_node *new_src = be_transform_node(src); @@ -1019,132 +1126,53 @@ static ir_node *gen_CopyB(ir_node *node) { ir_node *new_dst = be_transform_node(dst); ir_node *mem = get_CopyB_mem(node); ir_node *new_mem = be_transform_node(mem); - ir_graph *irg = current_ir_graph; dbg_info *dbg = get_irn_dbg_info(node); int size = get_type_size_bytes(get_CopyB_type(node)); ir_node *src_copy; ir_node *dst_copy; - src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src); - dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst); + src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src); + dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst); - return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy, - new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), - new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), - new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), + return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy, + new_bd_arm_EmptyReg(dbg, block), + new_bd_arm_EmptyReg(dbg, block), + new_bd_arm_EmptyReg(dbg, block), new_mem, size); } - -/******************************************** - * _ _ - * | | | | - * | |__ ___ _ __ ___ __| | ___ ___ - * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __| - * | |_) | __/ | | | (_) | (_| | __/\__ \ - * |_.__/ \___|_| |_|\___/ \__,_|\___||___/ - * - ********************************************/ - -/** - * Return an expanding stack offset. - * Note that function is called in the transform phase - * where the stack offsets are still relative regarding - * the first (frame allocating) IncSP. - * However this is exactly what we want because frame - * access must be done relative the the fist IncSP ... - */ -static int get_sp_expand_offset(ir_node *inc_sp) { - int offset = be_get_IncSP_offset(inc_sp); - - if (offset == BE_STACK_FRAME_SIZE_EXPAND) - return 0; - - return offset; -} - -#if 0 -static ir_node *gen_StackParam(ir_node *irn) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *mem = new_rd_NoMem(env->irg); - ir_node *ptr = get_irn_n(irn, 0); - ir_entity *ent = be_get_frame_entity(irn); - ir_mode *mode = env->mode; - -// /* If the StackParam has only one user -> */ -// /* put it in the Block where the user resides */ -// if (get_irn_n_edges(node) == 1) { -// env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node))); -// } - - if (mode_is_float(mode)) { - if (USE_SSE2(env->cg)) - new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T); - else { - env->cg->used_x87 = 1; - new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T); - } - } - else { - new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T); - } - - set_ia32_frame_ent(new_op, ent); - set_ia32_use_frame(new_op); - - set_ia32_am_support(new_op, ia32_am_Source); - set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_am_flavour(new_op, ia32_B); - set_ia32_ls_mode(new_op, mode); - - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); - - return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0); -} -#endif - /** * Transforms a FrameAddr into an ARM Add. */ -static ir_node *gen_be_FrameAddr(ir_node *node) { +static ir_node *gen_be_FrameAddr(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_entity *ent = be_get_frame_entity(node); - int offset = get_entity_offset(ent); - ir_node *op = be_get_FrameAddr_frame(node); - ir_node *new_op = be_transform_node(op); - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = mode_Iu; - ir_node *cnst; - - if (be_is_IncSP(op)) { - /* BEWARE: we get an offset which is absolute from an offset that - is relative. Both must be merged */ - offset += get_sp_expand_offset(op); - } - cnst = create_const_graph_value(dbg, block, (unsigned)offset); - if (is_arm_Mov_i(cnst)) - return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst)); - return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0); + ir_node *fp = be_get_FrameAddr_frame(node); + ir_node *new_fp = be_transform_node(fp); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; + + new_node = new_bd_arm_FrameAddr(dbgi, block, new_fp, ent); + return new_node; } /** * Transform a be_AddSP into an arm_AddSP. Eat up const sizes. */ -static ir_node *gen_be_AddSP(ir_node *node) { +static ir_node *gen_be_AddSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *sz = get_irn_n(node, be_pos_AddSP_size); ir_node *new_sz = be_transform_node(sz); ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); ir_node *new_sp = be_transform_node(sp); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *nomem = new_NoMem(); ir_node *new_op; /* ARM stack grows in reverse direction, make a SubSPandCopy */ - new_op = new_rd_arm_SubSPandCopy(dbgi, irg, block, new_sp, new_sz, nomem); + new_op = new_bd_arm_SubSPandCopy(dbgi, block, new_sp, new_sz, nomem); return new_op; } @@ -1152,19 +1180,19 @@ static ir_node *gen_be_AddSP(ir_node *node) { /** * Transform a be_SubSP into an arm_SubSP. Eat up const sizes. */ -static ir_node *gen_be_SubSP(ir_node *node) { +static ir_node *gen_be_SubSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *sz = get_irn_n(node, be_pos_SubSP_size); ir_node *new_sz = be_transform_node(sz); ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); ir_node *new_sp = be_transform_node(sp); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *nomem = new_NoMem(); ir_node *new_op; /* ARM stack grows in reverse direction, make an AddSP */ - new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem); + new_op = new_bd_arm_AddSP(dbgi, block, new_sp, new_sz, nomem); return new_op; } @@ -1172,7 +1200,8 @@ static ir_node *gen_be_SubSP(ir_node *node) { /** * Transform a be_Copy. */ -static ir_node *gen_be_Copy(ir_node *node) { +static ir_node *gen_be_Copy(ir_node *node) +{ ir_node *result = be_duplicate_node(node); ir_mode *mode = get_irn_mode(result); @@ -1186,185 +1215,169 @@ static ir_node *gen_be_Copy(ir_node *node) { /** * Transform a Proj from a Load. */ -static ir_node *gen_Proj_Load(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Proj_Load(ir_node *node) +{ ir_node *load = get_Proj_pred(node); ir_node *new_load = be_transform_node(load); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); /* renumber the proj */ switch (get_arm_irn_opcode(new_load)) { - case iro_arm_Load: - case iro_arm_Loadb: - case iro_arm_Loadbs: - case iro_arm_Loadh: - case iro_arm_Loadhs: + case iro_arm_Ldr: /* handle all gp loads equal: they have the same proj numbers. */ if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res); + return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M); + return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M); } break; case iro_arm_fpaLdf: if (proj == pn_Load_res) { ir_mode *mode = get_Load_mode(load); - return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res); + return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M); + return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M); } break; default: break; } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("Unsupported Proj from Load"); } /** * Transform and renumber the Projs from a CopyB. */ -static ir_node *gen_Proj_CopyB(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Proj_CopyB(ir_node *node) +{ ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_CopyB_M_regular: if (is_arm_CopyB(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M); + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M); } break; default: break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("Unsupported Proj from CopyB"); } /** * Transform and renumber the Projs from a Quot. */ -static ir_node *gen_Proj_Quot(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Proj_Quot(ir_node *node) +{ ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); switch (proj) { case pn_Quot_M: - if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M); - } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M); - } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M); - } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M); + if (is_arm_fpaDvf(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M); + } else if (is_arm_fpaRdf(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M); + } else if (is_arm_fpaFdv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M); + } else if (is_arm_fpaFrd(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M); } break; case pn_Quot_res: - if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res); - } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res); - } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res); - } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res); + if (is_arm_fpaDvf(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res); + } else if (is_arm_fpaRdf(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res); + } else if (is_arm_fpaFdv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res); + } else if (is_arm_fpaFrd(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res); } break; default: break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("Unsupported Proj from Quot"); } /** * Transform the Projs of a be_AddSP. */ -static ir_node *gen_Proj_be_AddSP(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Proj_be_AddSP(ir_node *node) +{ ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_AddSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_arm_SubSPandCopy_stack); - arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]); + arch_set_irn_register(res, &arm_gp_regs[REG_SP]); return res; - } else if(proj == pn_be_AddSP_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, - pn_arm_SubSPandCopy_addr); + } else if (proj == pn_be_AddSP_res) { + return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_arm_SubSPandCopy_addr); } else if (proj == pn_be_AddSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSPandCopy_M); + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_SubSPandCopy_M); } - - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("Unsupported Proj from AddSP"); } /** * Transform the Projs of a be_SubSP. */ -static ir_node *gen_Proj_be_SubSP(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Proj_be_SubSP(ir_node *node) +{ ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_SubSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_arm_AddSP_stack); - arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]); + arch_set_irn_register(res, &arm_gp_regs[REG_SP]); return res; } else if (proj == pn_be_SubSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M); + return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_AddSP_M); } - - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("Unsupported Proj from SubSP"); } /** * Transform the Projs from a Cmp. */ -static ir_node *gen_Proj_Cmp(ir_node *node) { +static ir_node *gen_Proj_Cmp(ir_node *node) +{ (void) node; - panic("Psi NYI\n"); + panic("Mux NYI"); } /** * Transform the Thread Local Storage Proj. */ -static ir_node *gen_Proj_tls(ir_node *node) { +static ir_node *gen_Proj_tls(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = NULL; - return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu); + return new_bd_arm_LdTls(dbgi, block, mode_Iu); } /** * Transform a Proj node. */ -static ir_node *gen_Proj(ir_node *node) { +static ir_node *gen_Proj(ir_node *node) +{ ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *pred = get_Proj_pred(node); @@ -1374,8 +1387,7 @@ static ir_node *gen_Proj(ir_node *node) { if (proj == pn_Store_M) { return be_transform_node(pred); } else { - assert(0); - return new_r_Bad(irg); + panic("Unsupported Proj from Store"); } } else if (is_Load(pred)) { return gen_Proj_Load(node); @@ -1389,15 +1401,14 @@ static ir_node *gen_Proj(ir_node *node) { return gen_Proj_be_AddSP(node); } else if (is_Cmp(pred)) { return gen_Proj_Cmp(node); - } else if (get_irn_op(pred) == op_Start) { + } else if (is_Start(pred)) { if (proj == pn_Start_X_initial_exec) { ir_node *block = get_nodes_block(pred); ir_node *jump; /* we exchange the ProjX with a jump */ block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, irg, block); - ir_fprintf(stderr, "created jump: %+F\n", jump); + jump = new_rd_Jmp(dbgi, block); return jump; } if (node == get_irg_anchor(irg, anchor_tls)) { @@ -1407,12 +1418,9 @@ static ir_node *gen_Proj(ir_node *node) { ir_node *new_pred = be_transform_node(pred); ir_mode *mode = get_irn_mode(node); if (mode_needs_gp_reg(mode)) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, + ir_node *new_proj = new_r_Proj(new_pred, mode_Iu, get_Proj_proj(node)); -#ifdef DEBUG_libfirm new_proj->node_nr = node->node_nr; -#endif return new_proj; } } @@ -1420,9 +1428,9 @@ static ir_node *gen_Proj(ir_node *node) { return be_duplicate_node(node); } -typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_graph *irg, ir_node *block); +typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block); -static INLINE ir_node *create_const(ir_node **place, +static inline ir_node *create_const(ir_node **place, create_const_node_func func, const arch_register_t* reg) { @@ -1432,51 +1440,38 @@ static INLINE ir_node *create_const(ir_node **place, return *place; block = get_irg_start_block(env_cg->irg); - res = func(NULL, env_cg->irg, block); - arch_set_irn_register(env_cg->arch_env, res, reg); + res = func(NULL, block); + arch_set_irn_register(res, reg); *place = res; - - add_irn_dep(get_irg_end(env_cg->irg), res); return res; } -static ir_node *arm_new_Unknown_gp(void) { - return create_const(&env_cg->unknown_gp, new_rd_arm_Unknown_GP, - &arm_gp_regs[REG_GP_UKNWN]); -} - -static ir_node *arm_new_Unknown_fpa(void) { - return create_const(&env_cg->unknown_fpa, new_rd_arm_Unknown_FPA, - &arm_fpa_regs[REG_FPA_UKNWN]); -} +static ir_node *gen_Unknown(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); -/** - * This function just sets the register for the Unknown node - * as this is not done during register allocation because Unknown - * is an "ignore" node. - */ -static ir_node *gen_Unknown(ir_node *node) { + /* just produce a 0 */ ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_FPA(env_cg->isa)) - return arm_new_Unknown_fpa(); - else if (USE_VFP(env_cg->isa)) - panic("VFP not supported yet"); - else - panic("Softfloat not supported yet"); + tarval *tv = get_mode_null(mode); + ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv); + be_dep_on_frame(node); + return node; } else if (mode_needs_gp_reg(mode)) { - return arm_new_Unknown_gp(); - } else { - assert(0 && "unsupported Unknown-Mode"); + return create_const_graph_value(dbgi, new_block, 0); } - return NULL; + panic("Unexpected Unknown mode"); } /** * Change some phi modes */ -static ir_node *gen_Phi(ir_node *node) { +static ir_node *gen_Phi(ir_node *node) +{ + const arch_register_req_t *req; ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -1488,152 +1483,108 @@ static ir_node *gen_Phi(ir_node *node) { assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ mode = mode_Iu; + req = arm_reg_classes[CLASS_arm_gp].class_req; + } else { + req = arch_no_register_req; } /* phi nodes allow loops, so we use the old arguments for now * and fix this later */ - phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1); - copy_node_attr(node, phi); + phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), + get_irn_in(node) + 1); + copy_node_attr(irg, node, phi); be_duplicate_deps(node, phi); - be_set_transformed_node(node, phi); + arch_set_out_register_req(phi, 0, req); + be_enqueue_preds(node); return phi; } -/********************************************************* - * _ _ _ - * (_) | | (_) - * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __ - * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__| - * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ | - * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_| - * - *********************************************************/ - /** * the BAD transformer. */ -static ir_node *bad_transform(ir_node *irn) { - panic("ARM backend: Not implemented: %+F\n", irn); - return irn; +static ir_node *bad_transform(ir_node *irn) +{ + panic("ARM backend: unexpected node %+F", irn); } /** * Set a node emitter. Make it a bit more type safe. */ -static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) { +static void set_transformer(ir_op *op, be_transform_func arm_transform_func) +{ op->ops.generic = (op_func)arm_transform_func; } /** * Enters all transform functions into the generic pointer */ -static void arm_register_transformers(void) { - ir_op *op_Max, *op_Min, *op_Mulh; - +static void arm_register_transformers(void) +{ /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); -#define GEN(a) set_transformer(op_##a, gen_##a) -#define BAD(a) set_transformer(op_##a, bad_transform) - - GEN(Add); - GEN(Sub); - GEN(Mul); - GEN(And); - GEN(Or); - GEN(Eor); - - GEN(Shl); - GEN(Shr); - GEN(Shrs); - BAD(Rot); /* unsupported yet */ - - GEN(Quot); - - /* should be lowered */ - BAD(Div); - BAD(Mod); - BAD(DivMod); - - GEN(Minus); - GEN(Conv); - GEN(Abs); - GEN(Not); - - GEN(Load); - GEN(Store); - GEN(Cond); - - BAD(ASM); /* unsupported yet */ - GEN(CopyB); - BAD(Mux); - BAD(Psi); /* unsupported yet */ - GEN(Proj); - GEN(Phi); - - GEN(Const); - GEN(SymConst); - - /* we should never see these nodes */ - BAD(Raise); - BAD(Sel); - BAD(InstOf); - BAD(Cast); - BAD(Free); - BAD(Tuple); - BAD(Id); - //BAD(Bad); - BAD(Confirm); - BAD(Filter); - BAD(CallBegin); - BAD(EndReg); - BAD(EndExcept); - - /* handle generic backend nodes */ - GEN(be_FrameAddr); - //GEN(be_Call); - //GEN(be_Return); - GEN(be_AddSP); - GEN(be_SubSP); - GEN(be_Copy); - - /* set the register for all Unknown nodes */ - GEN(Unknown); - - op_Max = get_op_Max(); - if (op_Max) - BAD(Max); /* unsupported yet */ - op_Min = get_op_Min(); - if (op_Min) - BAD(Min); /* unsupported yet */ - op_Mulh = get_op_Mulh(); - if (op_Mulh) - BAD(Mulh); /* unsupported yet */ - -#undef GEN -#undef BAD -} - -/** - * Pre-transform all unknown nodes. - */ -static void arm_pretransform_node(void *arch_cg) { - arm_code_gen_t *cg = arch_cg; - - cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); - cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa); + set_transformer(op_Abs, gen_Abs); + set_transformer(op_Add, gen_Add); + set_transformer(op_And, gen_And); + set_transformer(op_be_AddSP, gen_be_AddSP); + set_transformer(op_be_Call, gen_be_Call); + set_transformer(op_be_Copy, gen_be_Copy); + set_transformer(op_be_FrameAddr, gen_be_FrameAddr); + set_transformer(op_be_SubSP, gen_be_SubSP); + set_transformer(op_Cmp, gen_Cmp); + set_transformer(op_Cond, gen_Cond); + set_transformer(op_Const, gen_Const); + set_transformer(op_Conv, gen_Conv); + set_transformer(op_CopyB, gen_CopyB); + set_transformer(op_Eor, gen_Eor); + set_transformer(op_Jmp, gen_Jmp); + set_transformer(op_Load, gen_Load); + set_transformer(op_Minus, gen_Minus); + set_transformer(op_Mul, gen_Mul); + set_transformer(op_Not, gen_Not); + set_transformer(op_Or, gen_Or); + set_transformer(op_Phi, gen_Phi); + set_transformer(op_Proj, gen_Proj); + set_transformer(op_Quot, gen_Quot); + set_transformer(op_Rotl, gen_Rotl); + set_transformer(op_Shl, gen_Shl); + set_transformer(op_Shr, gen_Shr); + set_transformer(op_Shrs, gen_Shrs); + set_transformer(op_Store, gen_Store); + set_transformer(op_Sub, gen_Sub); + set_transformer(op_SymConst, gen_SymConst); + set_transformer(op_Unknown, gen_Unknown); + + set_transformer(op_ASM, bad_transform); + set_transformer(op_Builtin, bad_transform); + set_transformer(op_CallBegin, bad_transform); + set_transformer(op_Cast, bad_transform); + set_transformer(op_Confirm, bad_transform); + set_transformer(op_DivMod, bad_transform); + set_transformer(op_EndExcept, bad_transform); + set_transformer(op_EndReg, bad_transform); + set_transformer(op_Filter, bad_transform); + set_transformer(op_Free, bad_transform); + set_transformer(op_Id, bad_transform); + set_transformer(op_InstOf, bad_transform); + set_transformer(op_Mulh, bad_transform); + set_transformer(op_Mux, bad_transform); + set_transformer(op_Raise, bad_transform); + set_transformer(op_Sel, bad_transform); + set_transformer(op_Tuple, bad_transform); } /** * Initialize fpa Immediate support. */ -static void arm_init_fpa_immediate(void) { +static void arm_init_fpa_immediate(void) +{ /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */ - fpa_imm[0][fpa_null] = get_tarval_null(mode_F); - fpa_imm[0][fpa_one] = get_tarval_one(mode_F); + fpa_imm[0][fpa_null] = get_mode_null(mode_F); + fpa_imm[0][fpa_one] = get_mode_one(mode_F); fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F); fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F); fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F); @@ -1641,8 +1592,8 @@ static void arm_init_fpa_immediate(void) { fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F); fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); - fpa_imm[1][fpa_null] = get_tarval_null(mode_D); - fpa_imm[1][fpa_one] = get_tarval_one(mode_D); + fpa_imm[1][fpa_null] = get_mode_null(mode_D); + fpa_imm[1][fpa_one] = get_mode_one(mode_D); fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D); fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D); fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D); @@ -1650,8 +1601,8 @@ static void arm_init_fpa_immediate(void) { fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D); fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); - fpa_imm[2][fpa_null] = get_tarval_null(mode_E); - fpa_imm[2][fpa_one] = get_tarval_one(mode_E); + fpa_imm[2][fpa_null] = get_mode_null(mode_E); + fpa_imm[2][fpa_one] = get_mode_one(mode_E); fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E); fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E); fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E); @@ -1663,7 +1614,8 @@ static void arm_init_fpa_immediate(void) { /** * Transform a Firm graph into an ARM graph. */ -void arm_transform_graph(arm_code_gen_t *cg) { +void arm_transform_graph(arm_code_gen_t *cg) +{ static int imm_initialized = 0; if (! imm_initialized) { @@ -1672,9 +1624,10 @@ void arm_transform_graph(arm_code_gen_t *cg) { } arm_register_transformers(); env_cg = cg; - be_transform_graph(cg->birg, arm_pretransform_node, cg); + be_transform_graph(cg->irg, NULL); } -void arm_init_transform(void) { - // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform"); +void arm_init_transform(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform"); }