X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_transform.c;h=2ef801958e7d1f878639a674796a6ddd899e92de;hb=ede86ffb1270f07437edcc8ea3dd5d46530f93eb;hp=b189b960c224f6b964fe6a43724bd6ccbf40abe3;hpb=e3fdbd41ed77d327784775db5ba8f6577da45abe;p=libfirm diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c index b189b960c..2ef801958 100644 --- a/ir/be/arm/arm_transform.c +++ b/ir/be/arm/arm_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -38,12 +38,16 @@ #include "dbginfo.h" #include "iropt_t.h" #include "debug.h" +#include "error.h" #include "../benode_t.h" +#include "../beirg_t.h" +#include "../beutil.h" +#include "../betranshlp.h" #include "bearch_arm_t.h" #include "arm_nodes_attr.h" -#include "../arch/archop.h" /* we need this for Min and Max nodes */ +#include "archop.h" #include "arm_transform.h" #include "arm_new_nodes.h" #include "arm_map_regs.h" @@ -53,8 +57,10 @@ #include -extern ir_op *get_op_Mulh(void); +/** hold the current code generator during transformation */ +static arm_code_gen_t *env_cg; +extern ir_op *get_op_Mulh(void); /**************************************************************************************************** @@ -67,6 +73,10 @@ extern ir_op *get_op_Mulh(void); * ****************************************************************************************************/ +static INLINE int mode_needs_gp_reg(ir_mode *mode) { + return mode_is_int(mode) || mode_is_reference(mode); +} + typedef struct vals_ { int ops; unsigned char values[4]; @@ -79,7 +89,7 @@ static unsigned do_rol(unsigned v, unsigned rol) { } /** - * construct 8bit values und rot amounts for a value + * construct 8bit values and rot amounts for a value */ static void gen_vals_from_word(unsigned int value, vals *result) { @@ -122,19 +132,33 @@ static void gen_vals_from_word(unsigned int value, vals *result) /** * Creates a arm_Const node. */ -static ir_node *create_const_node(ir_node *irn, ir_node *block, long value) { - tarval *tv = new_tarval_from_long(value, mode_Iu); - dbg_info *dbg = get_irn_dbg_info(irn); - return new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv); +static ir_node *create_const_node(dbg_info *dbg, ir_node *block, long value) { + ir_mode *mode = mode_Iu; + ir_graph *irg = current_ir_graph; + ir_node *res; + + if (mode_needs_gp_reg(mode)) + mode = mode_Iu; + res = new_rd_arm_Mov_i(dbg, irg, block, mode, value); + /* ensure the const is scheduled AFTER the stack frame */ + add_irn_dep(res, get_irg_frame(irg)); + return res; } /** * Creates a arm_Const_Neg node. */ -static ir_node *create_const_neg_node(ir_node *irn, ir_node *block, long value) { - tarval *tv = new_tarval_from_long(value, mode_Iu); - dbg_info *dbg = get_irn_dbg_info(irn); - return new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv); +static ir_node *create_const_neg_node(dbg_info *dbg, ir_node *block, long value) { + ir_mode *mode = mode_Iu; + ir_graph *irg = current_ir_graph; + ir_node *res; + + if (mode_needs_gp_reg(mode)) + mode = mode_Iu; + res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value); + /* ensure the const is scheduled AFTER the stack frame */ + add_irn_dep(res, get_irg_frame(irg)); + return res; } #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode) @@ -149,8 +173,8 @@ static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int imme /** * Decode an immediate with shifter operand */ -unsigned int arm_decode_imm_w_shift(tarval *tv) { - unsigned l = get_tarval_long(tv); +unsigned int arm_decode_imm_w_shift(long imm_value) { + unsigned l = (unsigned)imm_value; unsigned rol = (l & ~0xFF) >> 7; return do_rol(l & 0xFF, rol); @@ -159,33 +183,32 @@ unsigned int arm_decode_imm_w_shift(tarval *tv) { /** * Creates a possible DAG for an constant. */ -static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned int value) { +static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) { ir_node *result; vals v, vn; int cnt; - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); + ir_mode *mode = mode_Iu; gen_vals_from_word(value, &v); gen_vals_from_word(~value, &vn); if (vn.ops < v.ops) { /* remove bits */ - result = create_const_neg_node(irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0])); + result = create_const_neg_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0])); for (cnt = 1; cnt < vn.ops; ++cnt) { - tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu); - ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv); + long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]); + ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value); result = bic_i_node; } } else { /* add bits */ - result = create_const_node(irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0])); + result = create_const_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0])); for (cnt = 1; cnt < v.ops; ++cnt) { - tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu); - ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv); + long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]); + ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value); result = orr_i_node; } } @@ -198,154 +221,122 @@ static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned * @param irn a Firm const */ static ir_node *create_const_graph(ir_node *irn, ir_node *block) { - int value = get_tarval_long(get_Const_tarval(irn)); - return create_const_graph_value(irn, block, value); -} - + tarval *tv = get_Const_tarval(irn); + ir_mode *mode = get_tarval_mode(tv); + int value; -/** - * Creates code for a Firm Const node. - */ -static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) { - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(irn); - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - - if (mode_is_float(mode)) { - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaConst(dbg, irg, block, mode, get_Const_tarval(irn)); - else if (USE_VFP(cg->isa)) - assert(mode != mode_E && "IEEE Extended FP not supported"); - assert(0 && "NYI"); + if (mode_is_reference(mode)) { + /* ARM is 32bit, so we can safely convert a reference tarval into Iu */ + assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu)); + tv = tarval_convert_to(tv, mode_Iu); } - else if (mode_is_reference(mode)) - return irn; - return create_const_graph(irn, block); + value = get_tarval_long(tv); + return create_const_graph_value(get_irn_dbg_info(irn), block, value); } -static ir_node *gen_mask(ir_node *irn, ir_node *op, int result_bits) { - ir_node *block = get_nodes_block(irn); +/** + * Create an And that will mask all upper bits + */ +static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) { unsigned mask_bits = (1 << result_bits) - 1; - ir_node *mask_node = create_const_graph_value(irn, block, mask_bits); - dbg_info *dbg = get_irn_dbg_info(irn); - return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL); + ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits); + return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0); } -static ir_node *gen_sign_extension(ir_node *irn, ir_node *op, int result_bits) { - ir_node *block = get_nodes_block(irn); +/** + * Generate code for a sign extension. + */ +static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) { + ir_graph *irg = current_ir_graph; int shift_width = 32 - result_bits; - ir_graph *irg = current_ir_graph; - ir_node *shift_const_node = create_const_graph_value(irn, block, shift_width); - dbg_info *dbg = get_irn_dbg_info(irn); - ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op)); - ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn)); + ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width); + ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu); + ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu); return rshift_node; } /** * Transforms a Conv node. * - * @param env The transformation environment - * @return the created arm Conv node + * @return The created ia32 Conv node */ -static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) { - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(irn); - ir_node *op = get_Conv_op(irn); - ir_mode *in_mode = get_irn_mode(op); - ir_mode *out_mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - - if (in_mode == out_mode) - return op; - - if (mode_is_float(in_mode) || mode_is_float(out_mode)) { - cg->have_fp = 1; - - if (USE_FPA(cg->isa)) { - if (mode_is_float(in_mode)) { - if (mode_is_float(out_mode)) { +static ir_node *gen_Conv(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op = get_Conv_op(node); + ir_node *new_op = be_transform_node(op); + ir_graph *irg = current_ir_graph; + ir_mode *src_mode = get_irn_mode(op); + ir_mode *dst_mode = get_irn_mode(node); + dbg_info *dbg = get_irn_dbg_info(node); + + if (src_mode == dst_mode) + return new_op; + + if (mode_is_float(src_mode) || mode_is_float(dst_mode)) { + env_cg->have_fp_insn = 1; + + if (USE_FPA(env_cg->isa)) { + if (mode_is_float(src_mode)) { + if (mode_is_float(dst_mode)) { /* from float to float */ - return new_rd_arm_fpaMov(dbg, irg, block, op, out_mode); + return new_rd_arm_fpaMvf(dbg, irg, block, new_op, dst_mode); } else { /* from float to int */ - return new_rd_arm_fpaFix(dbg, irg, block, op, out_mode); + return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode); } } else { /* from int to float */ - return new_rd_arm_fpaFlt(dbg, irg, block, op, out_mode); + return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode); } } - assert(0 && "NYI"); + else if (USE_VFP(env_cg->isa)) { + panic("VFP not supported yet\n"); + return NULL; + } + else { + panic("Softfloat not supported yet\n"); + return NULL; + } } else { /* complete in gp registers */ - int in_bits = get_mode_size_bits(in_mode); - int out_bits = get_mode_size_bits(out_mode); - int in_sign = get_mode_sign(in_mode); - int out_sign = get_mode_sign(out_mode); - - // 32 -> 32 - // NOPpen - if (in_bits == out_bits && in_bits == 32) - return op; - - // 16 -> 16 - // unsigned -> unsigned - // NOP - // unsigned -> signed - // sign extension (31:16)=(15) - // signed -> unsigned - // maskieren (31:16)=0 - // signed -> signed - // NOP - if (in_bits == out_bits && out_bits < 32) { - if (in_sign && !out_sign) { - return gen_mask(irn, op, out_bits); - } else { - return gen_sign_extension(irn, op, out_bits); + int src_bits = get_mode_size_bits(src_mode); + int dst_bits = get_mode_size_bits(dst_mode); + int min_bits; + ir_mode *min_mode; + + if (is_Load(skip_Proj(op))) { + if (src_bits == dst_bits) { + /* kill unneccessary conv */ + return new_op; } + /* after a load, the bit size is already converted */ + src_bits = 32; } - // 16 -> 32 - // unsigned -> unsigned - // NOP - // unsigned -> signed - // NOP - // signed -> unsigned - // sign extension (31:16)=(15) - // signed -> signed - // sign extension (31:16)=(15) - if (in_bits < out_bits) { - if (in_sign) { - return gen_sign_extension(irn, op, out_bits); + if (src_bits == dst_bits) { + /* kill unneccessary conv */ + return new_op; + } else if (dst_bits <= 32 && src_bits <= 32) { + if (src_bits < dst_bits) { + min_bits = src_bits; + min_mode = src_mode; } else { - return op; + min_bits = dst_bits; + min_mode = dst_mode; } - } - - // 32 -> 16 - // unsigned -> unsigned - // maskieren (31:16)=0 - // unsigned -> signed - // maskieren (31:16)=0 - // signed -> unsigned - // maskieren (31:16)=0 - // signed -> signed - // sign extension (erledigt auch maskieren) (31:16)=(15) - if (in_bits > out_bits) { - if (in_sign && out_sign) { - return gen_sign_extension(irn, op, out_bits); + if (mode_is_signed(min_mode)) { + return gen_sign_extension(dbg, block, new_op, min_bits); } else { - return gen_mask(irn, op, out_bits); + return gen_zero_extension(dbg, block, new_op, min_bits); } + } else { + panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode, + src_bits, dst_bits); + return NULL; } - assert(0 && "recheck integer conversion logic!"); - return irn; } - return NULL; } /** @@ -359,7 +350,7 @@ static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) { *pmod = mod; if (mod != ARM_SHF_NONE) { - long v = get_tarval_long(get_arm_value(n)); + long v = get_arm_imm_value(n); if (v < 32) return (int)v; } @@ -367,493 +358,582 @@ static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) { } /** - * Creates an arm Add. + * Creates an ARM Add. * - * @param env The transformation environment * @return the created arm Add node */ -static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Add_left(irn); - ir_node *op2 = get_Add_right(irn); - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - ir_node *op3; +static ir_node *gen_Add(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Add_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Add_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = get_irn_mode(node); + ir_graph *irg = current_ir_graph; + ir_node *new_op3; int v; arm_shift_modifier mod; - dbg_info *dbg = get_irn_dbg_info(irn); + dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaAdd(dbg, irg, block, op1, op2, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) { + if (is_arm_fpaMvf_i(new_op1)) + return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_fpaMvf_i(new_op2)) + return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); + return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode); + } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + return NULL; } - assert(0 && "NYI"); - } - if (mode_is_numP(mode)) { - if (is_arm_Mov_i(op1)) - return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1)); - if (is_arm_Mov_i(op2)) - return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2)); + else { + panic("Softfloat not supported yet\n"); + return NULL; + } + } else { + assert(mode_is_data(mode)); + mode = mode_Iu; + + if (is_arm_Mov_i(new_op1)) + return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_Mov_i(new_op2)) + return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); /* check for MLA */ - if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) { - op3 = op2; - op2 = get_irn_n(op1, 1); - op1 = get_irn_n(op1, 0); + if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) { + new_op3 = new_op2; + new_op2 = get_irn_n(new_op1, 1); + new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode); + return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode); } - if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) { - op3 = op1; - op1 = get_irn_n(op2, 0); - op2 = get_irn_n(op2, 1); + if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) { + new_op3 = new_op1; + new_op1 = get_irn_n(new_op2, 0); + new_op2 = get_irn_n(new_op2, 1); - return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode); + return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode); } /* is the first a shifter */ - v = is_shifter_operand(op1, &mod); + v = is_shifter_operand(new_op1, &mod); if (v) { - op1 = get_irn_n(op1, 0); - return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); + new_op1 = get_irn_n(new_op1, 0); + return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v); } /* is the second a shifter */ - v = is_shifter_operand(op2, &mod); + v = is_shifter_operand(new_op2, &mod); if (v) { - op2 = get_irn_n(op2, 0); - return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); + new_op2 = get_irn_n(new_op2, 0); + return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v); } /* normal ADD */ - return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); } - - assert(0 && "unknown mode for add"); - return NULL; } /** - * Creates an arm Mul. + * Creates an ARM Mul. * - * @param env The transformation environment * @return the created arm Mul node */ -static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Mul_left(irn); - ir_node *op2 = get_Mul_right(irn); - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Mul(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Mul_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Mul_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = get_irn_mode(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaMul(dbg, irg, block, op1, op2, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) { + if (is_arm_Mov_i(new_op1)) + return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_Mov_i(new_op2)) + return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); + return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode); + } + else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + return NULL; + } + else { + panic("Softfloat not supported yet\n"); + return NULL; } - assert(0 && "NYI"); } - return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode); + assert(mode_is_data(mode)); + mode = mode_Iu; + return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode); } /** - * Creates an arm floating point Div. + * Creates an ARM floating point Div. * * @param env The transformation environment * @return the created arm fDiv node */ -static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Quot_left(irn); - ir_node *op2 = get_Quot_right(irn); - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Quot(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Quot_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Quot_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = get_irn_mode(node); + dbg_info *dbg = get_irn_dbg_info(node); assert(mode != mode_E && "IEEE Extended FP not supported"); - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, op1, op2, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) { + if (is_arm_Mov_i(new_op1)) + return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_Mov_i(new_op2)) + return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2)); + return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode); + } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } + else { + panic("Softfloat not supported yet\n"); + return NULL; } - assert(0 && "NYI"); - - return NULL; } #define GEN_INT_OP(op) \ -static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \ - ir_graph *irg = current_ir_graph; \ - ir_node *block = get_nodes_block(irn); \ - ir_node *op1 = get_ ## op ## _left(irn); \ - ir_node *op2 = get_ ## op ## _right(irn); \ - int v; \ + ir_node *block = be_transform_node(get_nodes_block(node)); \ + ir_node *op1 = get_ ## op ## _left(node); \ + ir_node *new_op1 = be_transform_node(op1); \ + ir_node *op2 = get_ ## op ## _right(node); \ + ir_node *new_op2 = be_transform_node(op2); \ + ir_graph *irg = current_ir_graph; \ + ir_mode *mode = mode_Iu; \ + dbg_info *dbg = get_irn_dbg_info(node); \ + int v; \ arm_shift_modifier mod; \ - ir_mode *mode = get_irn_mode(irn); \ - dbg_info *dbg = get_irn_dbg_info(irn); \ \ - if (is_arm_Mov_i(op1)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \ - if (is_arm_Mov_i(op2)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \ + if (is_arm_Mov_i(new_op1)) \ + return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \ + if (is_arm_Mov_i(new_op2)) \ + return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \ /* is the first a shifter */ \ - v = is_shifter_operand(op1, &mod); \ + v = is_shifter_operand(new_op1, &mod); \ if (v) { \ - op1 = get_irn_n(op1, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \ + new_op1 = get_irn_n(new_op1, 0); \ + return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \ } \ /* is the second a shifter */ \ - v = is_shifter_operand(op2, &mod); \ + v = is_shifter_operand(new_op2, &mod); \ if (v) { \ - op2 = get_irn_n(op2, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \ + new_op2 = get_irn_n(new_op2, 0); \ + return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \ } \ /* Normal op */ \ - return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \ -} - + return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \ /** - * Creates an arm And. + * Creates an ARM And. * - * @param env The transformation environment * @return the created arm And node */ -static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg); -GEN_INT_OP(And) +static ir_node *gen_And(ir_node *node) { + GEN_INT_OP(And); +} /** - * Creates an arm Orr. + * Creates an ARM Orr. * * @param env The transformation environment * @return the created arm Or node */ -static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg); -GEN_INT_OP(Or) +static ir_node *gen_Or(ir_node *node) { + GEN_INT_OP(Or); +} /** - * Creates an arm Eor. + * Creates an ARM Eor. * - * @param env The transformation environment * @return the created arm Eor node */ -static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg); -GEN_INT_OP(Eor) +static ir_node *gen_Eor(ir_node *node) { + GEN_INT_OP(Eor); +} /** - * Creates an arm Sub. + * Creates an ARM Sub. * - * @param env The transformation environment * @return the created arm Sub node */ -static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Sub_left(irn); - ir_node *op2 = get_Sub_right(irn); - int v; +static ir_node *gen_Sub(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Sub_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Sub_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = get_irn_mode(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); + int v; arm_shift_modifier mod; - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaSub(dbg, irg, block, op1, op2, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) { + if (is_arm_Mov_i(new_op1)) + return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_Mov_i(new_op2)) + return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); + return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode); + } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + return NULL; + } + else { + panic("Softfloat not supported yet\n"); + return NULL; } - assert(0 && "NYI"); } - if (mode_is_numP(mode)) { - if (is_arm_Mov_i(op1)) - return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1)); - if (is_arm_Mov_i(op2)) - return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2)); + else { + assert(mode_is_data(mode) && "unknown mode for Sub"); + mode = mode_Iu; + + if (is_arm_Mov_i(new_op1)) + return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); + if (is_arm_Mov_i(new_op2)) + return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); /* is the first a shifter */ - v = is_shifter_operand(op1, &mod); + v = is_shifter_operand(new_op1, &mod); if (v) { - op1 = get_irn_n(op1, 0); - return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); + new_op1 = get_irn_n(new_op1, 0); + return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v); } /* is the second a shifter */ - v = is_shifter_operand(op2, &mod); + v = is_shifter_operand(new_op2, &mod); if (v) { - op2 = get_irn_n(op2, 0); - return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); + new_op2 = get_irn_n(new_op2, 0); + return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v); } /* normal sub */ - return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); } - assert(0 && "unknown mode for sub"); - return NULL; } /** - * Creates an arm Shl. + * Creates an ARM Shl. * - * @param env The transformation environment - * @return the created arm Shl node + * @return the created ARM Shl node */ -static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) { - ir_node *result; - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Shl_left(irn); - ir_node *op2 = get_Shl_right(irn); - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); - - if (is_arm_Mov_i(op2)) { - result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2)); - } else { - result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode); +static ir_node *gen_Shl(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Shl_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Shl_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = mode_Iu; + dbg_info *dbg = get_irn_dbg_info(node); + + if (is_arm_Mov_i(new_op2)) { + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2)); } - return result; + return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode); } /** - * Creates an arm Shr. + * Creates an ARM Shr. * - * @param env The transformation environment - * @return the created arm Shr node + * @return the created ARM Shr node */ -static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) { - ir_node *result; - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Shr_left(irn); - ir_node *op2 = get_Shr_right(irn); - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); - - if (is_arm_Mov_i(op2)) { - result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2)); - } else { - result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode); +static ir_node *gen_Shr(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Shr_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Shr_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = mode_Iu; + dbg_info *dbg = get_irn_dbg_info(node); + + if (is_arm_Mov_i(new_op2)) { + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2)); } - return result; + return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode); } /** - * Creates an arm Shrs. + * Creates an ARM Shrs. * - * @param env The transformation environment - * @return the created arm Shrs node + * @return the created ARM Shrs node */ -static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) { - ir_node *result; - ir_node *block = get_nodes_block(irn); - ir_node *op1 = get_Shrs_left(irn); - ir_node *op2 = get_Shrs_right(irn); - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - - if (is_arm_Mov_i(op2)) { - result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2)); - } else { - result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode); +static ir_node *gen_Shrs(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op1 = get_Shrs_left(node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Shrs_right(node); + ir_node *new_op2 = be_transform_node(op2); + ir_mode *mode = mode_Iu; + dbg_info *dbg = get_irn_dbg_info(node); + + if (is_arm_Mov_i(new_op2)) { + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2)); } - return result; + return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode); } /** * Transforms a Not node. * - * @param env The transformation environment - * @return the created arm Not node + * @return the created ARM Not node */ -static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op = get_Not_op(irn); - int v; +static ir_node *gen_Not(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op = get_Not_op(node); + ir_node *new_op = be_transform_node(op); + dbg_info *dbg = get_irn_dbg_info(node); + ir_mode *mode = mode_Iu; arm_shift_modifier mod = ARM_SHF_NONE; - tarval *tv = NULL; - dbg_info *dbg = get_irn_dbg_info(irn); + int v = is_shifter_operand(new_op, &mod); - v = is_shifter_operand(op, &mod); if (v) { - op = get_irn_n(op, 0); - tv = new_tarval_from_long(v, mode_Iu); + new_op = get_irn_n(new_op, 0); } - return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv); + return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v); } /** * Transforms an Abs node. * * @param env The transformation environment - * @return the created arm Abs node + * @return the created ARM Abs node */ -static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op = get_Abs_op(irn); - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Abs(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op = get_Abs_op(node); + ir_node *new_op = be_transform_node(op); + dbg_info *dbg = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, op, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) + return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode); + else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } + else { + panic("Softfloat not supported yet\n"); } - assert(0 && "NYI"); } - return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode); + assert(mode_is_data(mode)); + mode = mode_Iu; + return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode); } /** * Transforms a Minus node. * - * @param env The transformation environment - * @return the created arm Minus node + * @return the created ARM Minus node */ -static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_node *op = get_Minus_op(irn); - ir_mode *mode = get_irn_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Minus(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *op = get_Minus_op(node); + ir_node *new_op = be_transform_node(op); + dbg_info *dbg = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaMnv(dbg, irg, block, op, mode); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) + return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode); + else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } + else { + panic("Softfloat not supported yet\n"); } - assert(0 && "NYI"); } - return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode)); + assert(mode_is_data(mode)); + mode = mode_Iu; + return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0); } /** * Transforms a Load. * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Load node - * @param mode node mode - * @return the created arm Load node + * @return the created ARM Load node */ -static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_mode *mode = get_Load_mode(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Load(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = get_Load_ptr(node); + ir_node *new_ptr = be_transform_node(ptr); + ir_node *mem = get_Load_mem(node); + ir_node *new_mem = be_transform_node(mem); + ir_mode *mode = get_Load_mode(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *new_load = NULL; if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaLdf(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), - get_Load_mode(irn)); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) + new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode); + else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } + else { + panic("Softfloat not supported yet\n"); } - assert(0 && "NYI"); - } - if (mode == mode_Bu) { - return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); - } - if (mode == mode_Bs) { - return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); - } - if (mode == mode_Hu) { - return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); } - if (mode == mode_Hs) { - return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); + else { + assert(mode_is_data(mode) && "unsupported mode for Load"); + + if (mode_is_signed(mode)) { + /* sign extended loads */ + switch (get_mode_size_bits(mode)) { + case 8: + new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem); + break; + case 16: + new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem); + break; + case 32: + new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem); + break; + default: + panic("mode size not supported\n"); + } + } else { + /* zero extended loads */ + switch (get_mode_size_bits(mode)) { + case 8: + new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem); + break; + case 16: + new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem); + break; + case 32: + new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem); + break; + default: + panic("mode size not supported\n"); + } + } } - if (mode_is_reference(mode)) { - return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); + set_irn_pinned(new_load, get_irn_pinned(node)); + + /* check for special case: the loaded value might not be used */ + if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) { + /* add a result proj and a Keep to produce a pseudo use */ + ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res); + be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj); } - return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn)); + + return new_load; } /** * Transforms a Store. * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Store node - * @param mode node mode - * @return the created arm Store node + * @return the created ARM Store node */ -static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_mode *mode = get_irn_mode(get_Store_value(irn)); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_Store(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = get_Store_ptr(node); + ir_node *new_ptr = be_transform_node(ptr); + ir_node *mem = get_Store_mem(node); + ir_node *new_mem = be_transform_node(mem); + ir_node *val = get_Store_value(node); + ir_node *new_val = be_transform_node(val); + ir_mode *mode = get_irn_mode(val); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *new_store = NULL; - assert(mode != mode_E && "IEEE Extended FP not supported"); if (mode_is_float(mode)) { - cg->have_fp = 1; - if (USE_FPA(cg->isa)) - return new_rd_arm_fpaStf(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), - get_Store_mem(irn), get_irn_mode(get_Store_value(irn))); - else if (USE_VFP(cg->isa)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) + new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode); + else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } else { + panic("Softfloat not supported yet\n"); + } + } else { + assert(mode_is_data(mode) && "unsupported mode for Store"); + switch (get_mode_size_bits(mode)) { + case 8: + new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem); + case 16: + new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem); + default: + new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem); } - assert(0 && "NYI"); - } - if (mode == mode_Bu) { - return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn)); - } - if (mode == mode_Bs) { - return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn)); - } - if (mode == mode_Hu) { - return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn)); - } - if (mode == mode_Hs) { - return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn)); } - return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn)); + set_irn_pinned(new_store, get_irn_pinned(node)); + return new_store; } - -static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) { - ir_node *result = NULL; - ir_node *selector = get_Cond_selector(irn); - ir_node *block = get_nodes_block(irn); - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(irn); - - if ( get_irn_mode(selector) == mode_b ) { - //CondJmp - ir_node *proj_node = get_Cond_selector(irn); - ir_node *cmp_node = get_Proj_pred(proj_node); - ir_node *op1 = get_Cmp_left(cmp_node); - ir_node *op2 = get_Cmp_right(cmp_node); - result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, mode_T); - set_arm_proj_num(result, get_Proj_proj(proj_node)); +/** + * Transforms a Cond. + * + * @return the created ARM Cond node + */ +static ir_node *gen_Cond(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *selector = get_Cond_selector(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(selector); + + if (mode == mode_b) { + /* an conditional jump */ + ir_node *cmp_node = get_Proj_pred(selector); + ir_node *op1 = get_Cmp_left(cmp_node); + ir_node *new_op1 = be_transform_node(op1); + ir_node *op2 = get_Cmp_right(cmp_node); + ir_node *new_op2 = be_transform_node(op2); + + if (mode_is_float(get_irn_mode(op1))) { + /* floating point compare */ + pn_Cmp pnc = get_Proj_proj(selector); + + if (pnc & pn_Cmp_Uo) { + /* check for unordered, need cmf */ + return new_rd_arm_fpaCmfBra(dbg, irg, block, new_op1, new_op2, pnc); + } + /* Hmm: use need cmfe */ + return new_rd_arm_fpaCmfeBra(dbg, irg, block, new_op1, new_op2, pnc); + } else { + /* integer compare */ + return new_rd_arm_CmpBra(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector)); + } } else { - //SwitchJmp - ir_node *op = get_irn_n(irn, 0); + /* SwitchJmp */ + ir_node *new_op = be_transform_node(selector); ir_node *const_graph; ir_node *sub; - ir_node *const_node; ir_node *proj; const ir_edge_t *edge; int min = INT_MAX; int max = INT_MIN; int translation; - int norm_max; - int norm_min; int pn; int n_projs; - ir_node **projs; - foreach_out_edge(irn, edge) { + foreach_out_edge(node, edge) { proj = get_edge_src_irn(edge); assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); @@ -863,14 +943,9 @@ static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) { max = pn>max ? pn : max; } translation = min; - norm_max = max - translation; - norm_min = min - translation; - - n_projs = norm_max + 1; - projs = xcalloc(n_projs , sizeof(ir_node*)); - + n_projs = max - translation + 1; - foreach_out_edge(irn, edge) { + foreach_out_edge(node, edge) { proj = get_edge_src_irn(edge); assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); @@ -878,15 +953,10 @@ static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) { set_Proj_proj(proj, pn); } - - const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu)); - const_graph = gen_Const(const_node, cg); - sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL); - result = new_rd_arm_SwitchJmp(dbg, irg, block, sub, mode_T); - set_arm_n_projs(result, n_projs); - set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation); + const_graph = create_const_graph_value(dbg, block, translation); + sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0); + return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation); } - return result; } /** @@ -894,19 +964,17 @@ static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) { * @param symc the SymConst * @return name of the SymConst */ -const char *get_sc_name(ir_node *symc) { +static ident *get_sc_ident(ir_node *symc) { ir_entity *ent; - if (get_irn_opcode(symc) != iro_SymConst) - return "NONE"; switch (get_SymConst_kind(symc)) { case symconst_addr_name: - return get_id_str(get_SymConst_name(symc)); + return get_SymConst_name(symc); case symconst_addr_ent: ent = get_SymConst_entity(symc); - mark_entity_visited(ent); - return get_entity_ld_name(ent); + set_entity_backend_marked(ent, 1); + return get_entity_ld_ident(ent); default: assert(0 && "Unsupported SymConst"); @@ -915,45 +983,125 @@ const char *get_sc_name(ir_node *symc) { return NULL; } -static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_name(irn)); -} +static tarval *fpa_imm[3][fpa_max]; +/** + * Check, if a floating point tarval is an fpa immediate, i.e. + * one of 0, 1, 2, 3, 4, 5, 10, or 0.5. + */ +static int is_fpa_immediate(tarval *tv) { + ir_mode *mode = get_tarval_mode(tv); + int i, j, res = 1; + + switch (get_mode_size_bits(mode)) { + case 32: + i = 0; + break; + case 64: + i = 1; + break; + default: + i = 2; + } + + if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) { + tv = tarval_neg(tv); + res = -1; + } + for (j = 0; j < fpa_max; ++j) { + if (tv == fpa_imm[i][j]) + return res * j; + } + return fpa_max; +} /** - * Transforms a CopyB node. + * Transforms a Const node. * - * @param env The transformation environment - * @return The transformed node. + * @return The transformed ARM node. */ -static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) { - ir_node *res = NULL; - dbg_info *dbg = get_irn_dbg_info(irn); - ir_mode *mode = get_irn_mode(irn); - ir_node *src = get_CopyB_src(irn); - ir_node *dst = get_CopyB_dst(irn); - ir_node *mem = get_CopyB_mem(irn); - ir_node *block = get_nodes_block(irn); - int size = get_type_size_bytes(get_CopyB_type(irn)); - ir_graph *irg = current_ir_graph; - ir_node *src_copy; - ir_node *dst_copy; +static ir_node *gen_Const(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_graph *irg = current_ir_graph; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbg = get_irn_dbg_info(node); - src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src); - dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst); + if (mode_is_float(mode)) { + env_cg->have_fp_insn = 1; + if (USE_FPA(env_cg->isa)) { + tarval *tv = get_Const_tarval(node); + int imm = is_fpa_immediate(tv); + + if (imm != fpa_max) { + if (imm > 0) + node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm); + else + node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm); + } else { + node = new_rd_arm_fpaConst(dbg, irg, block, tv); + } + /* ensure the const is scheduled AFTER the stack frame */ + add_irn_dep(node, get_irg_frame(irg)); + return node; + } + else if (USE_VFP(env_cg->isa)) { + assert(mode != mode_E && "IEEE Extended FP not supported"); + panic("VFP not supported yet\n"); + } + else { + panic("Softfloat not supported yet\n"); + } + } + return create_const_graph(node, block); +} - res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode); - set_arm_value(res, new_tarval_from_long(size, mode_Iu)); +/** + * Transforms a SymConst node. + * + * @return The transformed ARM node. + */ +static ir_node *gen_SymConst(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_mode *mode = mode_Iu; + dbg_info *dbg = get_irn_dbg_info(node); + ir_graph *irg = current_ir_graph; + ir_node *res; + res = new_rd_arm_SymConst(dbg, irg, block, mode, get_sc_ident(node)); + /* ensure the const is scheduled AFTER the stack frame */ + add_irn_dep(res, get_irg_frame(irg)); return res; } - - +/** + * Transforms a CopyB node. + * + * @return The transformed ARM node. + */ +static ir_node *gen_CopyB(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *src = get_CopyB_src(node); + ir_node *new_src = be_transform_node(src); + ir_node *dst = get_CopyB_dst(node); + ir_node *new_dst = be_transform_node(dst); + ir_node *mem = get_CopyB_mem(node); + ir_node *new_mem = be_transform_node(mem); + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(node); + int size = get_type_size_bytes(get_CopyB_type(node)); + ir_node *src_copy; + ir_node *dst_copy; + + src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src); + dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst); + + return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy, + new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), + new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), + new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), + new_mem, size); +} /******************************************** @@ -984,9 +1132,9 @@ static int get_sp_expand_offset(ir_node *inc_sp) { } #if 0 -static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) { +static ir_node *gen_StackParam(ir_node *irn) { + ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *new_op = NULL; - ir_node *block = get_nodes_block(irn); ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = new_rd_NoMem(env->irg); ir_node *ptr = get_irn_n(irn, 0); @@ -1026,33 +1174,34 @@ static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) { #endif /** - * Transforms a FrameAddr into an ia32 Add. + * Transforms a FrameAddr into an ARM Add. */ -static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) { - ir_node *block = get_nodes_block(irn); - ir_entity *ent = be_get_frame_entity(irn); - int offset = get_entity_offset(ent); - ir_node *op = get_irn_n(irn, 0); - ir_node *cnst; - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); +static ir_node *gen_be_FrameAddr(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_entity *ent = be_get_frame_entity(node); + int offset = get_entity_offset(ent); + ir_node *op = be_get_FrameAddr_frame(node); + ir_node *new_op = be_transform_node(op); + dbg_info *dbg = get_irn_dbg_info(node); + ir_mode *mode = mode_Iu; + ir_node *cnst; if (be_is_IncSP(op)) { /* BEWARE: we get an offset which is absolute from an offset that is relative. Both must be merged */ offset += get_sp_expand_offset(op); } - cnst = create_const_graph_value(irn, block, (unsigned)offset); + cnst = create_const_graph_value(dbg, block, (unsigned)offset); if (is_arm_Mov_i(cnst)) - return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst)); - return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst)); + return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0); } #if 0 /** - * Transforms a FrameLoad into an ia32 Load. + * Transforms a FrameLoad into an ARM Load. */ -static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) { +static ir_node *gen_FrameLoad(ir_node *irn) { ir_node *new_op = NULL; ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = get_irn_n(irn, 0); @@ -1086,212 +1235,455 @@ static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) { } #endif -#if 0 /** - * Transforms a FrameStore into an ia32 Store. + * Transform a be_AddSP into an arm_AddSP. Eat up const sizes. */ -static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) { - ir_node *new_op = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *mem = get_irn_n(irn, 0); - ir_node *ptr = get_irn_n(irn, 1); - ir_node *val = get_irn_n(irn, 2); - ir_entity *ent = be_get_frame_entity(irn); - ir_mode *mode = get_irn_mode(val); +static ir_node *gen_be_AddSP(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sz = get_irn_n(node, be_pos_AddSP_size); + ir_node *new_sz = be_transform_node(sz); + ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); + ir_node *new_sp = be_transform_node(sp); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *nomem = new_NoMem(); + ir_node *new_op; + + /* ARM stack grows in reverse direction, make a SubSP */ + new_op = new_rd_arm_SubSP(dbgi, irg, block, new_sp, new_sz, nomem); - if (mode_is_float(mode)) { - if (USE_SSE2(env->cg)) - new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); - else { - env->cg->used_x87 = 1; - new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + return new_op; +} + +/** + * Transform a be_SubSP into an arm_SubSP. Eat up const sizes. + */ +static ir_node *gen_be_SubSP(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sz = get_irn_n(node, be_pos_SubSP_size); + ir_node *new_sz = be_transform_node(sz); + ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); + ir_node *new_sp = be_transform_node(sp); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *nomem = new_NoMem(); + ir_node *new_op; + + /* ARM stack grows in reverse direction, make an AddSP */ + new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem); + + return new_op; +} + +/** + * Transform a be_Copy. + */ +static ir_node *gen_be_Copy(ir_node *node) { + ir_node *result = be_duplicate_node(node); + ir_mode *mode = get_irn_mode(result); + + if (mode_needs_gp_reg(mode)) { + set_irn_mode(node, mode_Iu); + } + + return result; +} + +/** + * Transform a Proj from a Load. + */ +static ir_node *gen_Proj_Load(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *load = get_Proj_pred(node); + ir_node *new_load = be_transform_node(load); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + + /* renumber the proj */ + switch (get_arm_irn_opcode(new_load)) { + case iro_arm_Load: + case iro_arm_Loadb: + case iro_arm_Loadbs: + case iro_arm_Loadh: + case iro_arm_Loadhs: + /* handle all gp loads equal: they have the same proj numbers. */ + if (proj == pn_Load_res) { + return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res); + } else if (proj == pn_Load_M) { + return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M); + } + break; + case iro_arm_fpaLdf: + if (proj == pn_Load_res) { + ir_mode *mode = get_Load_mode(load); + return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res); + } else if (proj == pn_Load_M) { + return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M); } + break; + default: + break; } - else if (get_mode_size_bits(mode) == 8) { - new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + assert(0); + return new_rd_Unknown(irg, get_irn_mode(node)); +} + +/** + * Transform and renumber the Projs from a CopyB. + */ +static ir_node *gen_Proj_CopyB(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); + + switch(proj) { + case pn_CopyB_M_regular: + if (is_arm_CopyB(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M); + } + break; + default: + break; } - else { - new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + assert(0); + return new_rd_Unknown(irg, mode); +} + +/** + * Transform and renumber the Projs from a Quot. + */ +static ir_node *gen_Proj_Quot(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); + + switch (proj) { + case pn_Quot_M: + if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M); + } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M); + } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M); + } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M); + } + break; + case pn_Quot_res: + if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res); + } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res); + } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res); + } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res); + } + break; + default: + break; } + assert(0); + return new_rd_Unknown(irg, mode); +} - set_ia32_frame_ent(new_op, ent); - set_ia32_use_frame(new_op); +/** + * Transform the Projs of a be_AddSP. + */ +static ir_node *gen_Proj_be_AddSP(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + + if (proj == pn_be_AddSP_sp) { + ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + pn_arm_SubSP_stack); + arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]); + return res; + } else if(proj == pn_be_AddSP_res) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + pn_arm_SubSP_addr); + } else if (proj == pn_be_AddSP_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSP_M); + } - set_ia32_am_support(new_op, ia32_am_Dest); - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_am_flavour(new_op, ia32_B); - set_ia32_ls_mode(new_op, mode); + assert(0); + return new_rd_Unknown(irg, get_irn_mode(node)); +} - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); +/** + * Transform the Projs of a be_SubSP. + */ +static ir_node *gen_Proj_be_SubSP(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + + if (proj == pn_be_SubSP_sp) { + ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + pn_arm_AddSP_stack); + arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]); + return res; + } else if (proj == pn_be_SubSP_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M); + } - return new_op; + assert(0); + return new_rd_Unknown(irg, get_irn_mode(node)); } -#endif - -// static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) { -// return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode); -// } +/** + * Transform the Projs from a Cmp. + */ +static ir_node *gen_Proj_Cmp(ir_node *node) { + (void) node; + panic("Psi NYI\n"); +} -/********************************************************* - * _ _ _ - * (_) | | (_) - * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __ - * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__| - * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ | - * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_| - * - *********************************************************/ /** - * move constants out of the start block + * Transform the Thread Local Storage Proj. */ -void arm_move_consts(ir_node *node, void *env) { - int i; +static ir_node *gen_Proj_tls(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = NULL; - if (is_Block(node)) - return; + return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu); +} - if (is_Phi(node)) { - for (i = get_irn_arity(node) - 1; i >= 0; --i) { - ir_node *pred = get_irn_n(node,i); - ir_opcode pred_code = get_irn_opcode(pred); - if (pred_code == iro_Const) { - ir_node *const_graph; - const_graph = create_const_graph(pred, get_nodes_block(get_irn_n(get_nodes_block(node),i))); - set_irn_n(node, i, const_graph); - } - else if (pred_code == iro_SymConst) { - /* FIXME: in general, SymConst always require a load, so it - might be better to place them into the first real block - and let the spiller rematerialize them. */ - const char *str = get_sc_name(pred); - ir_node *symconst_node; - symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred), - current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)), - get_irn_mode(pred), str); - set_irn_n(node, i, symconst_node); - } +/** + * Transform a Proj node. + */ +static ir_node *gen_Proj(ir_node *node) { + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *pred = get_Proj_pred(node); + long proj = get_Proj_proj(node); + + if (is_Store(pred)) { + if (proj == pn_Store_M) { + return be_transform_node(pred); + } else { + assert(0); + return new_r_Bad(irg); } - return; - } - for (i = 0; i < get_irn_arity(node); i++) { - ir_node *pred = get_irn_n(node,i); - ir_opcode pred_code = get_irn_opcode(pred); - if (pred_code == iro_Const) { - ir_node *const_graph; - const_graph = create_const_graph(pred, get_nodes_block(node)); - set_irn_n(node, i, const_graph); - } else if (pred_code == iro_SymConst) { - const char *str = get_sc_name(pred); - ir_node *symconst_node; - symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred), - current_ir_graph, get_nodes_block(node), - get_irn_mode(pred), str); - set_irn_n(node, i, symconst_node); + } else if (is_Load(pred)) { + return gen_Proj_Load(node); + } else if (is_CopyB(pred)) { + return gen_Proj_CopyB(node); + } else if (is_Quot(pred)) { + return gen_Proj_Quot(node); + } else if (be_is_SubSP(pred)) { + return gen_Proj_be_SubSP(node); + } else if (be_is_AddSP(pred)) { + return gen_Proj_be_AddSP(node); + } else if (is_Cmp(pred)) { + return gen_Proj_Cmp(node); + } else if (get_irn_op(pred) == op_Start) { + if (proj == pn_Start_X_initial_exec) { + ir_node *block = get_nodes_block(pred); + ir_node *jump; + + /* we exchange the ProjX with a jump */ + block = be_transform_node(block); + jump = new_rd_Jmp(dbgi, irg, block); + ir_fprintf(stderr, "created jump: %+F\n", jump); + return jump; + } + if (node == get_irg_anchor(irg, anchor_tls)) { + return gen_Proj_tls(node); + } + } else { + ir_node *new_pred = be_transform_node(pred); + ir_mode *mode = get_irn_mode(node); + if (mode_needs_gp_reg(mode)) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, + get_Proj_proj(node)); +#ifdef DEBUG_libfirm + new_proj->node_nr = node->node_nr; +#endif + return new_proj; } } + + return be_duplicate_node(node); } +typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_graph *irg, ir_node *block); -/************************************************************************/ -/* move symbolic constants out of startblock */ -/************************************************************************/ -void arm_move_symconsts(ir_node *node, void *env) { - int i; +static INLINE ir_node *create_const(ir_node **place, + create_const_node_func func, + const arch_register_t* reg) +{ + ir_node *block, *res; - if (is_Block(node)) - return; + if (*place != NULL) + return *place; - for (i = 0; i < get_irn_arity(node); i++) { - ir_node *pred = get_irn_n(node,i); - ir_opcode pred_code = get_irn_opcode(pred); + block = get_irg_start_block(env_cg->irg); + res = func(NULL, env_cg->irg, block); + arch_set_irn_register(env_cg->arch_env, res, reg); + *place = res; - if (pred_code == iro_SymConst) { - const char *str = get_sc_name(pred); - ir_node *symconst_node; + add_irn_dep(get_irg_end(env_cg->irg), res); + return res; +} - symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred), - current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str); - set_irn_n(node, i, symconst_node); - } +static ir_node *arm_new_Unknown_gp(void) { + return create_const(&env_cg->unknown_gp, new_rd_arm_Unknown_GP, + &arm_gp_regs[REG_GP_UKNWN]); +} + +static ir_node *arm_new_Unknown_fpa(void) { + return create_const(&env_cg->unknown_fpa, new_rd_arm_Unknown_FPA, + &arm_fpa_regs[REG_FPA_UKNWN]); +} + +/** + * This function just sets the register for the Unknown node + * as this is not done during register allocation because Unknown + * is an "ignore" node. + */ +static ir_node *gen_Unknown(ir_node *node) { + ir_mode *mode = get_irn_mode(node); + if (mode_is_float(mode)) { + if (USE_FPA(env_cg->isa)) + return arm_new_Unknown_fpa(); + else if (USE_VFP(env_cg->isa)) + panic("VFP not supported yet"); + else + panic("Softfloat not supported yet"); + } else if (mode_needs_gp_reg(mode)) { + return arm_new_Unknown_gp(); + } else { + assert(0 && "unsupported Unknown-Mode"); } + + return NULL; } +/** + * Change some phi modes + */ +static ir_node *gen_Phi(ir_node *node) { + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *phi; + + if (mode_needs_gp_reg(mode)) { + /* we shouldn't have any 64bit stuff around anymore */ + assert(get_mode_size_bits(mode) <= 32); + /* all integer operations are on 32bit registers now */ + mode = mode_Iu; + } + + /* phi nodes allow loops, so we use the old arguments for now + * and fix this later */ + phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1); + copy_node_attr(node, phi); + be_duplicate_deps(node, phi); + + be_set_transformed_node(node, phi); + be_enqueue_preds(node); + + return phi; +} + +/********************************************************* + * _ _ _ + * (_) | | (_) + * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __ + * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__| + * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ | + * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_| + * + *********************************************************/ + /** * the BAD transformer. */ -static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) { - ir_fprintf(stderr, "Not implemented: %+F\n", irn); - assert(0); - return NULL; +static ir_node *bad_transform(ir_node *irn) { + panic("ARM backend: Not implemented: %+F\n", irn); + return irn; +} + +/** + * Set a node emitter. Make it a bit more type safe. + */ +static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) { + op->ops.generic = (op_func)arm_transform_func; } /** * Enters all transform functions into the generic pointer */ -void arm_register_transformers(void) { +static void arm_register_transformers(void) { ir_op *op_Max, *op_Min, *op_Mulh; /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); -#define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a -#define BAD(a) op_##a->ops.generic = (op_func)bad_transform -#define IGN(a) - - FIRM_OP(Add); // done - FIRM_OP(Mul); // done - FIRM_OP(Quot); // done - FIRM_OP(And); // done - FIRM_OP(Or); // done - FIRM_OP(Eor); // done - - FIRM_OP(Sub); // done - FIRM_OP(Shl); // done - FIRM_OP(Shr); // done - FIRM_OP(Shrs); // done - - FIRM_OP(Minus); // done - FIRM_OP(Not); // done - FIRM_OP(Abs); // done - - FIRM_OP(CopyB); // done - FIRM_OP(Const); // TODO: floating point consts - FIRM_OP(Conv); // TODO: floating point conversions +#define GEN(a) set_transformer(op_##a, gen_##a) +#define BAD(a) set_transformer(op_##a, bad_transform) - FIRM_OP(Load); // done - FIRM_OP(Store); // done + GEN(Add); + GEN(Sub); + GEN(Mul); + GEN(And); + GEN(Or); + GEN(Eor); - FIRM_OP(SymConst); - FIRM_OP(Cond); // integer done + GEN(Shl); + GEN(Shr); + GEN(Shrs); + BAD(Rot); /* unsupported yet */ - /* TODO: implement these nodes */ + GEN(Quot); - IGN(Div); // intrinsic lowering - IGN(Mod); // intrinsic lowering - IGN(DivMod); // TODO: implement DivMod + /* should be lowered */ + BAD(Div); + BAD(Mod); + BAD(DivMod); - IGN(Mux); - IGN(Unknown); - IGN(Cmp); // done, implemented in cond + GEN(Minus); + GEN(Conv); + GEN(Abs); + GEN(Not); - /* You probably don't need to handle the following nodes */ + GEN(Load); + GEN(Store); + GEN(Cond); - IGN(Call); - IGN(Proj); - IGN(Alloc); + BAD(ASM); /* unsupported yet */ + GEN(CopyB); + BAD(Mux); + BAD(Psi); /* unsupported yet */ + GEN(Proj); + GEN(Phi); - IGN(Block); - IGN(Start); - IGN(End); - IGN(NoMem); - IGN(Phi); - IGN(IJmp); - IGN(Jmp); // emitter done - IGN(Break); - IGN(Sync); + GEN(Const); + GEN(SymConst); + /* we should never see these nodes */ BAD(Raise); BAD(Sel); BAD(InstOf); @@ -1299,60 +1691,96 @@ void arm_register_transformers(void) { BAD(Free); BAD(Tuple); BAD(Id); - BAD(Bad); + //BAD(Bad); BAD(Confirm); BAD(Filter); BAD(CallBegin); BAD(EndReg); BAD(EndExcept); - FIRM_OP(be_FrameAddr); + /* handle generic backend nodes */ + GEN(be_FrameAddr); + //GEN(be_Call); + //GEN(be_Return); + GEN(be_AddSP); + GEN(be_SubSP); + GEN(be_Copy); + + /* set the register for all Unknown nodes */ + GEN(Unknown); op_Max = get_op_Max(); if (op_Max) - BAD(Max); + BAD(Max); /* unsupported yet */ op_Min = get_op_Min(); if (op_Min) - BAD(Min); + BAD(Min); /* unsupported yet */ op_Mulh = get_op_Mulh(); if (op_Mulh) - BAD(Mulh); + BAD(Mulh); /* unsupported yet */ -#undef IGN -#undef FIRM_OP +#undef GEN #undef BAD } -typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg); - /** - * Transforms the given firm node (and maybe some other related nodes) - * into one or more assembler nodes. - * - * @param node the firm node - * @param env the debug module + * Pre-transform all unknown nodes. */ -void arm_transform_node(ir_node *node, void *env) { - arm_code_gen_t *cg = (arm_code_gen_t *)env; - ir_op *op = get_irn_op(node); - ir_node *asm_node = NULL; +static void arm_pretransform_node(void *arch_cg) { + arm_code_gen_t *cg = arch_cg; - if (op == op_Block) - return; + cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); + cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa); +} - DBG((cg->mod, LEVEL_1, "check %+F ... ", node)); +/** + * Initialize fpa Immediate support. + */ +static void arm_init_fpa_immediate(void) { + /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */ + fpa_imm[0][fpa_null] = get_tarval_null(mode_F); + fpa_imm[0][fpa_one] = get_tarval_one(mode_F); + fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F); + fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F); + fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F); + fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F); + fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F); + fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F); + + fpa_imm[1][fpa_null] = get_tarval_null(mode_D); + fpa_imm[1][fpa_one] = get_tarval_one(mode_D); + fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D); + fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D); + fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D); + fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D); + fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D); + fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D); + + fpa_imm[2][fpa_null] = get_tarval_null(mode_E); + fpa_imm[2][fpa_one] = get_tarval_one(mode_E); + fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E); + fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E); + fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E); + fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E); + fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E); + fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E); +} - if (op->ops.generic) { - transform_func *transform = (transform_func *)op->ops.generic; +/** + * Transform a Firm graph into an ARM graph. + */ +void arm_transform_graph(arm_code_gen_t *cg) { + static int imm_initialized = 0; - asm_node = (*transform)(node, cg); + if (! imm_initialized) { + arm_init_fpa_immediate(); + imm_initialized = 1; } + arm_register_transformers(); + env_cg = cg; + be_transform_graph(cg->birg, arm_pretransform_node, cg); +} - if (asm_node) { - exchange(node, asm_node); - DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node)); - } - else { - DB((cg->mod, LEVEL_1, "ignored\n")); - } +void arm_init_transform(void) { + // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform"); }