X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_spec.pl;h=9201aeb163a13b8c4cec24389f244110ae4bc3d5;hb=3c3425a50a1d721b74a015c6812257e32feeac85;hp=2dc73687099aa878066750658775758ecb4fb343;hpb=1350645390c1ab5f39ab987d9c3dfb2b031e56ec;p=libfirm diff --git a/ir/be/arm/arm_spec.pl b/ir/be/arm/arm_spec.pl index 2dc736870..9201aeb16 100644 --- a/ir/be/arm/arm_spec.pl +++ b/ir/be/arm/arm_spec.pl @@ -1,7 +1,5 @@ -# Creation: 2006/02/13 # Arm Architecure Specification # Author: Matthias Braun, Michael Beck, Oliver Richter, Tobias Gneist -# $Id$ $arch = "arm"; @@ -10,38 +8,38 @@ $arch = "arm"; # $mode_gp = "mode_Iu"; $mode_flags = "mode_Bu"; -$mode_fp = "mode_E"; +$mode_fp = "mode_F"; # NOTE: Last entry of each class is the largest Firm-Mode a register can hold %reg_classes = ( gp => [ - { name => "r0" }, - { name => "r1" }, - { name => "r2" }, - { name => "r3" }, - { name => "r4" }, - { name => "r5" }, - { name => "r6" }, - { name => "r7" }, - { name => "r8" }, - { name => "r9" }, - { name => "r10" }, - { name => "r11" }, - { name => "r12" }, - { name => "sp" }, - { name => "lr" }, - { name => "pc" }, + { name => "r0", dwarf => 0 }, + { name => "r1", dwarf => 1 }, + { name => "r2", dwarf => 2 }, + { name => "r3", dwarf => 3 }, + { name => "r4", dwarf => 4 }, + { name => "r5", dwarf => 5 }, + { name => "r6", dwarf => 6 }, + { name => "r7", dwarf => 7 }, + { name => "r8", dwarf => 8 }, + { name => "r9", dwarf => 9 }, + { name => "r10", dwarf => 10 }, + { name => "r11", dwarf => 11 }, + { name => "r12", dwarf => 12 }, + { name => "sp", dwarf => 13 }, + { name => "lr", dwarf => 14 }, + { name => "pc", dwarf => 15 }, { mode => $mode_gp } ], fpa => [ - { name => "f0" }, - { name => "f1" }, - { name => "f2" }, - { name => "f3" }, - { name => "f4" }, - { name => "f5" }, - { name => "f6" }, - { name => "f7" }, + { name => "f0", dwarf => 96 }, + { name => "f1", dwarf => 97 }, + { name => "f2", dwarf => 98 }, + { name => "f3", dwarf => 99 }, + { name => "f4", dwarf => 100 }, + { name => "f5", dwarf => 101 }, + { name => "f6", dwarf => 102 }, + { name => "f7", dwarf => 103 }, { mode => $mode_fp } ], flags => [ @@ -50,47 +48,29 @@ $mode_fp = "mode_E"; ], ); -%emit_templates = ( - FM => "${arch}_emit_float_load_store_mode(node);", - AM => "${arch}_emit_float_arithmetic_mode(node);", - LM => "${arch}_emit_load_mode(node);", - SM => "${arch}_emit_store_mode(node);", - SO => "${arch}_emit_shifter_operand(node);", - S0 => "${arch}_emit_source_register(node, 0);", - SC => "${arch}_emit_symconst(node);", - S1 => "${arch}_emit_source_register(node, 1);", - S2 => "${arch}_emit_source_register(node, 2);", - S3 => "${arch}_emit_source_register(node, 3);", - S4 => "${arch}_emit_source_register(node, 4);", - D0 => "${arch}_emit_dest_register(node, 0);", - D1 => "${arch}_emit_dest_register(node, 1);", - D2 => "${arch}_emit_dest_register(node, 2);", - O => "${arch}_emit_offset(node);", -); - $default_attr_type = "arm_attr_t"; $default_copy_attr = "arm_copy_attr"; %init_attr = ( - arm_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);", + arm_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);", arm_SymConst_attr_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n". + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n". "\tinit_arm_SymConst_attributes(res, entity, symconst_offset);", - arm_CondJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);", - arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);", - arm_fConst_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);", + arm_CondJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);", + arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);", + arm_fConst_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);", arm_load_store_attr_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n". + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n". "\tinit_arm_load_store_attributes(res, ls_mode, entity, entity_sign, offset, is_frame_entity);", arm_shifter_operand_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n", + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n", arm_cmp_attr_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n", + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n", arm_farith_attr_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n". + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n". "\tinit_arm_farith_attributes(res, op_mode);", arm_CopyB_attr_t => - "\tinit_arm_attributes(res, irn_flags_, in_reqs, exec_units, n_res);\n". + "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n". "\tinit_arm_CopyB_attributes(res, size);", ); @@ -195,7 +175,7 @@ my %cmp_shifter_operand_constructors = ( Add => { irn_flags => [ "rematerializable" ], - emit => '. add %D0, %S0, %SO', + emit => 'add %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -204,21 +184,21 @@ Add => { Mul => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp", "gp" ], out => [ "!in_r1" ] }, - emit =>'. mul %D0, %S0, %S1', + emit => 'mul %D0, %S0, %S1', mode => $mode_gp, }, Smull => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp", "gp" ], out => [ "gp", "gp" ] }, - emit =>'. smull %D0, %D1, %S0, %S1', + emit => 'smull %D0, %D1, %S0, %S1', outs => [ "low", "high" ], }, Umull => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp", "gp" ], out => [ "gp", "gp" ] }, - emit =>'. umull %D0, %D1, %S0, %S1', + emit =>'umull %D0, %D1, %S0, %S1', outs => [ "low", "high" ], mode => $mode_gp, }, @@ -226,13 +206,13 @@ Umull => { Mla => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in_r1" ] }, - emit =>'. mla %D0, %S0, %S1, %S2', + emit =>'mla %D0, %S0, %S1, %S2', mode => $mode_gp, }, And => { irn_flags => [ "rematerializable" ], - emit => '. and %D0, %S0, %SO', + emit => 'and %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -240,7 +220,7 @@ And => { Or => { irn_flags => [ "rematerializable" ], - emit => '. orr %D0, %S0, %SO', + emit => 'orr %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -248,7 +228,7 @@ Or => { Eor => { irn_flags => [ "rematerializable" ], - emit => '. eor %D0, %S0, %SO', + emit => 'eor %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -256,7 +236,7 @@ Eor => { Bic => { irn_flags => [ "rematerializable" ], - emit => '. bic %D0, %S0, %SO', + emit => 'bic %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -264,7 +244,7 @@ Bic => { Sub => { irn_flags => [ "rematerializable" ], - emit => '. sub %D0, %S0, %SO', + emit => 'sub %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -272,7 +252,7 @@ Sub => { Rsb => { irn_flags => [ "rematerializable" ], - emit => '. rsb %D0, %S0, %SO', + emit => 'rsb %D0, %S0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%binop_shifter_operand_constructors, @@ -281,7 +261,7 @@ Rsb => { Mov => { irn_flags => [ "rematerializable" ], arity => "variable", - emit => '. mov %D0, %SO', + emit => 'mov %D0, %O', mode => $mode_gp, attr_type => "arm_shifter_operand_t", constructors => \%unop_shifter_operand_constructors, @@ -291,7 +271,7 @@ Mvn => { irn_flags => [ "rematerializable" ], attr_type => "arm_shifter_operand_t", arity => "variable", - emit => '. mvn %D0, %SO', + emit => 'mvn %D0, %O', mode => $mode_gp, constructors => \%unop_shifter_operand_constructors, }, @@ -299,7 +279,7 @@ Mvn => { Clz => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit =>'. clz %D0, %S0', + emit => 'clz %D0, %S0', mode => $mode_gp, }, @@ -312,9 +292,9 @@ LinkMovPC => { attr_type => "arm_shifter_operand_t", attr => "arm_shift_modifier_t shift_modifier, unsigned char immediate_value, unsigned char immediate_rot", custominit => "init_arm_shifter_operand(res, immediate_value, shift_modifier, immediate_rot);\n". - "\tarch_irn_add_flags(res, arch_irn_flags_modify_flags);", - emit => ". mov lr, pc\n". - ". mov pc, %SO", + "\tarch_add_irn_flags(res, arch_irn_flags_modify_flags);", + emit => "mov lr, pc\n". + "mov pc, %O", }, # mov lr, pc\n ldr pc, XXX -- This combination is used for calls to function @@ -325,9 +305,9 @@ LinkLdrPC => { out_arity => "variable", attr_type => "arm_load_store_attr_t", attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity", - custominit => "arch_irn_add_flags(res, arch_irn_flags_modify_flags);", - emit => ". mov lr, pc\n". - ". ldr pc, %SO", + custominit => "arch_add_irn_flags(res, arch_irn_flags_modify_flags);", + emit => "mov lr, pc\n". + "ldr pc, %O", }, Bl => { @@ -336,8 +316,8 @@ Bl => { out_arity => "variable", attr_type => "arm_SymConst_attr_t", attr => "ir_entity *entity, int symconst_offset", - custominit => "arch_irn_add_flags(res, arch_irn_flags_modify_flags);", - emit => '. bl %SC', + custominit => "arch_add_irn_flags(res, arch_irn_flags_modify_flags);", + emit => 'bl %I', }, # this node produces ALWAYS an empty (tempary) gp reg and cannot be CSE'd @@ -345,7 +325,7 @@ EmptyReg => { op_flags => [ "constlike" ], irn_flags => [ "rematerializable" ], reg_req => { out => [ "gp" ] }, - emit => '. /* %D0 now available for calculations */', + emit => '/* %D0 now available for calculations */', cmp_attr => 'return 1;', mode => $mode_gp, }, @@ -379,7 +359,7 @@ SymConst => { Cmp => { irn_flags => [ "rematerializable", "modify_flags" ], - emit => '. cmp %S0, %SO', + emit => 'cmp %S0, %O', mode => $mode_flags, attr_type => "arm_cmp_attr_t", constructors => \%cmp_shifter_operand_constructors, @@ -387,14 +367,14 @@ Cmp => { Tst => { irn_flags => [ "rematerializable", "modify_flags" ], - emit => '. tst %S0, %SO', + emit => 'tst %S0, %O', mode => $mode_flags, attr_type => "arm_cmp_attr_t", constructors => \%cmp_shifter_operand_constructors, }, B => { - op_flags => [ "labeled", "cfopcode", "forking" ], + op_flags => [ "cfopcode", "forking" ], state => "pinned", mode => "mode_T", reg_req => { in => [ "flags" ], out => [ "none", "none" ] }, @@ -412,55 +392,54 @@ Jmp => { }, SwitchJmp => { - op_flags => [ "labeled", "cfopcode", "forking" ], + op_flags => [ "cfopcode", "forking" ], state => "pinned", mode => "mode_T", - attr => "int n_projs, long def_proj_num", - init_attr => "\tset_arm_SwitchJmp_n_projs(res, n_projs);\n". - "\tset_arm_SwitchJmp_default_proj_num(res, def_proj_num);\n". - "\tinfo->out_infos = NULL;", + attr => "const ir_switch_table *table", + init_attr => "init_arm_SwitchJmp_attributes(res, table);", reg_req => { in => [ "gp" ], out => [ "none" ] }, + out_arity => "variable", attr_type => "arm_SwitchJmp_attr_t", }, Ldr => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], state => "exc_pinned", ins => [ "ptr", "mem" ], outs => [ "res", "M" ], reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, - emit => '. ldr%LM %D0, [%S0, #%O]', + emit => 'ldr%ML %D0, [%S0, #%o]', attr_type => "arm_load_store_attr_t", attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity", }, Str => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], state => "exc_pinned", ins => [ "ptr", "val", "mem" ], outs => [ "M" ], reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, - emit => '. str%SM %S1, [%S0, #%O]', + emit => 'str%MS %S1, [%S0, #%o]', mode => "mode_M", attr_type => "arm_load_store_attr_t", attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity", }, StoreStackM4Inc => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], irn_flags => [ "rematerializable" ], state => "exc_pinned", reg_req => { in => [ "sp", "gp", "gp", "gp", "gp", "none" ], out => [ "sp:I|S", "none" ] }, - emit => '. stmfd %S0!, {%S1, %S2, %S3, %S4}', + emit => 'stmfd %S0!, {%S1, %S2, %S3, %S4}', outs => [ "ptr", "M" ], }, LoadStackM3Epilogue => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], irn_flags => [ "rematerializable" ], state => "exc_pinned", reg_req => { in => [ "sp", "none" ], out => [ "r11:I", "sp:I|S", "pc:I", "none" ] }, - emit => '. ldmfd %S0, {%D0, %D1, %D2}', + emit => 'ldmfd %S0, {%D0, %D1, %D2}', outs => [ "res0", "res1", "res2", "M" ], }, @@ -469,7 +448,7 @@ LoadStackM3Epilogue => { Adf => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] }, - emit => '. adf%AM %D0, %S0, %S1', + emit => 'adf%MA %D0, %S0, %S1', attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", mode => $mode_fp, @@ -478,7 +457,7 @@ Adf => { Muf => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] }, - emit =>'. muf%AM %D0, %S0, %S1', + emit => 'muf%MA %D0, %S0, %S1', attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", mode => $mode_fp, @@ -487,7 +466,7 @@ Muf => { Suf => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] }, - emit => '. suf%AM %D0, %S0, %S1', + emit => 'suf%MA %D0, %S0, %S1', attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", mode => $mode_fp, @@ -495,7 +474,7 @@ Suf => { Dvf => { reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa", "none" ] }, - emit =>'. dvf%AM %D0, %S0, %S1', + emit => 'dvf%MA %D0, %S0, %S1', outs => [ "res", "M" ], attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", @@ -505,7 +484,7 @@ Dvf => { Mvf => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "fpa" ], out => [ "fpa" ] }, - emit => '. mvf%AM %S0, %D0', + emit => 'mvf%MA %S0, %D0', attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", mode => $mode_fp, @@ -514,7 +493,7 @@ Mvf => { FltX => { irn_flags => [ "rematerializable" ], reg_req => { in => [ "gp" ], out => [ "fpa" ] }, - emit => '. flt%AM %D0, %S0', + emit => 'flt%MA %D0, %S0', attr_type => "arm_farith_attr_t", attr => "ir_mode *op_mode", mode => $mode_fp, @@ -527,28 +506,28 @@ Cmfe => { attr => "bool ins_permuted", init_attr => "init_arm_cmp_attr(res, ins_permuted, false);", reg_req => { in => [ "fpa", "fpa" ], out => [ "flags" ] }, - emit => '. cmfe %S0, %S1', + emit => 'cmfe %S0, %S1', }, Ldf => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], state => "exc_pinned", ins => [ "ptr", "mem" ], outs => [ "res", "M" ], reg_req => { in => [ "gp", "none" ], out => [ "fpa", "none" ] }, - emit => '. ldf%FM %D0, [%S0, #%O]', + emit => 'ldf%MF %D0, [%S0, #%o]', attr_type => "arm_load_store_attr_t", attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity", }, Stf => { - op_flags => [ "labeled" ], + op_flags => [ "uses_memory" ], state => "exc_pinned", ins => [ "ptr", "val", "mem" ], outs => [ "M" ], mode => "mode_M", reg_req => { in => [ "gp", "fpa", "none" ], out => [ "none" ] }, - emit => '. stf%FM %S1, [%S0, #%O]', + emit => 'stf%MF %S1, [%S0, #%o]', attr_type => "arm_load_store_attr_t", attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity", },