X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_new_nodes.c;h=fc9e27ab805b818a73767e8d6499329dd658db3f;hb=ef63002fcb03a29f1b4e041c067d0fa8546bed96;hp=161e475ea117772fd3139b07bd0c6d9a0b152576;hpb=7f81d2a2c9293cf34e4db08fc402a5c33ef919eb;p=libfirm diff --git a/ir/be/arm/arm_new_nodes.c b/ir/be/arm/arm_new_nodes.c index 161e475ea..fc9e27ab8 100644 --- a/ir/be/arm/arm_new_nodes.c +++ b/ir/be/arm/arm_new_nodes.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -25,9 +25,7 @@ * @author Oliver Richter, Tobias Gneist * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include @@ -38,85 +36,38 @@ #include "ircons_t.h" #include "iropt_t.h" #include "irop.h" -#include "firm_common_t.h" #include "irvrfy_t.h" #include "irprintf.h" #include "xmalloc.h" -#include "../bearch_t.h" +#include "../bearch.h" #include "arm_nodes_attr.h" #include "arm_new_nodes.h" -#include "gen_arm_regalloc_if_t.h" +#include "arm_optimize.h" #include "../beabi.h" #include "bearch_arm_t.h" /** - * Returns the shift modifier string. + * Return the fpa immediate from the encoding. */ -const char *arm_shf_mod_name(arm_shift_modifier mod) { - static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" }; - return names[mod]; -} - -/*********************************************************************************** - * _ _ _ __ - * | | (_) | | / _| - * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___ - * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \ - * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/ - * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___| - * | | - * |_| - ***********************************************************************************/ - -/** - * Dumps the register requirements for either in or out. - */ -static void dump_reg_req(FILE *F, const ir_node *node, - const arch_register_req_t **reqs, int inout) { - char *dir = inout ? "out" : "in"; - int max = inout ? get_arm_n_res(node) : get_irn_arity(node); - char buf[1024]; - int i; - - memset(buf, 0, sizeof(buf)); - - if (reqs) { - for (i = 0; i < max; i++) { - fprintf(F, "%sreq #%d =", dir, i); - - if (reqs[i]->type == arch_register_req_type_none) { - fprintf(F, " n/a"); - } - - if (reqs[i]->type & arch_register_req_type_normal) { - fprintf(F, " %s", reqs[i]->cls->name); - } - - if (reqs[i]->type & arch_register_req_type_limited) { - fprintf(F, " %s", - arch_register_req_format(buf, sizeof(buf), reqs[i], node)); - } - - if (reqs[i]->type & arch_register_req_type_should_be_same) { - ir_fprintf(F, " same as %+F", get_irn_n(node, reqs[i]->other_same)); - } - - if (reqs[i]->type & arch_register_req_type_should_be_different) { - ir_fprintf(F, " different from %+F", get_irn_n(node, reqs[i]->other_different)); - } - - fprintf(F, "\n"); - } - - fprintf(F, "\n"); - } else { - fprintf(F, "%sreq = N/A\n", dir); - } +const char *arm_get_fpa_imm_name(long imm_value) +{ + static const char *fpa_imm[] = { + "0", + "1", + "2", + "3", + "4", + "5", + "10", + "0.5" + }; + return fpa_imm[imm_value]; } + /** * Dumper interface for dumping arm nodes in vcg. * @param n the node to dump @@ -124,14 +75,10 @@ static void dump_reg_req(FILE *F, const ir_node *node, * @param reason indicates which kind of information should be dumped * @return 0 on success or != 0 on failure */ -static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { +static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) +{ ir_mode *mode = NULL; - int bad = 0; - int i; - arm_attr_t *attr = get_arm_attr(n); - const arch_register_req_t **reqs; - const arch_register_t **slots; - arm_shift_modifier mod; + //arm_attr_t *attr = get_arm_attr(n); switch (reason) { case dump_node_opcode_txt: @@ -150,474 +97,423 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { break; case dump_node_nodeattr_txt: - mod = ARM_GET_SHF_MOD(attr); - if (ARM_HAS_SHIFT(mod)) { - fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value)); - } - else if (mod == ARM_SHF_IMM) { - /* immediate */ - fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value)); - } + /* TODO: dump shift modifiers */ break; case dump_node_info_txt: - fprintf(F, "=== arm attr begin ===\n"); - - /* dump IN requirements */ - if (get_irn_arity(n) > 0) { - reqs = get_arm_in_req_all(n); - dump_reg_req(F, n, reqs, 0); - } - - /* dump OUT requirements */ - if (ARR_LEN(attr->slots) > 0) { - reqs = get_arm_out_req_all(n); - dump_reg_req(F, n, reqs, 1); - } - - /* dump assigned registers */ - slots = get_arm_slots(n); - if (slots && ARR_LEN(attr->slots) > 0) { - for (i = 0; i < ARR_LEN(attr->slots); i++) { - if (slots[i]) { - fprintf(F, "reg #%d = %s\n", i, slots[i]->name); - } - else { - fprintf(F, "reg #%d = n/a\n", i); - } - } - } - fprintf(F, "\n"); - - /* dump n_res */ - fprintf(F, "n_res = %d\n", get_arm_n_res(n)); - - /* dump flags */ - fprintf(F, "flags ="); - if (attr->flags == arch_irn_flags_none) { - fprintf(F, " none"); - } - else { - if (attr->flags & arch_irn_flags_dont_spill) { - fprintf(F, " unspillable"); - } - if (attr->flags & arch_irn_flags_rematerializable) { - fprintf(F, " remat"); - } - if (attr->flags & arch_irn_flags_ignore) { - fprintf(F, " ignore"); - } - } - fprintf(F, " (%d)\n", attr->flags); - - if (get_arm_value(n)) { - if (is_arm_CopyB(n)) { - fprintf(F, "size = %lu\n", get_tarval_long(get_arm_value(n))); + arch_dump_reqs_and_registers(F, n); + + if (is_arm_CopyB(n)) { + //fprintf(F, "size = %lu\n", get_arm_imm_value(n)); + } else { + /* TODO */ +#if 0 + long v = get_arm_imm_value(n); + if (ARM_GET_FPA_IMM(attr)) { + fprintf(F, "immediate float value = %s\n", arm_get_fpa_imm_name(v)); } else { - if (mode_is_float(get_irn_mode(n))) { - fprintf(F, "float value = (%f)\n", (double) get_tarval_double(get_arm_value(n))); - } else if (mode_is_int(get_irn_mode(n))) { - long v = get_tarval_long(get_arm_value(n)); - fprintf(F, "long value = %ld (0x%08lx)\n", v, v); - } else if (mode_is_reference(get_irn_mode(n))) { - fprintf(F, "pointer\n"); - } else { - assert(0 && "unbehandelter Typ im const-Knoten"); - } + fprintf(F, "immediate value = %ld (0x%08lx)\n", v, v); } +#endif } - if (get_arm_proj_num(n) >= 0) { - fprintf(F, "proj_num = (%d)\n", get_arm_proj_num(n)); - } - /* TODO: dump all additional attributes */ - fprintf(F, "=== arm attr end ===\n"); - /* end of: case dump_node_info_txt */ +#if 0 + if (is_arm_CmpBra(n) && get_arm_CondJmp_proj_num(n) >= 0) { + fprintf(F, "proj_num = (%d)\n", get_arm_CondJmp_proj_num(n)); + } +#endif break; } - return bad; -} - + return 0; +} -/*************************************************************************************************** - * _ _ _ __ _ _ _ _ - * | | | | | | / / | | | | | | | | - * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___ - * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __| - * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \ - * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/ - * __/ | - * |___/ - ***************************************************************************************************/ -/** - * Wraps get_irn_generic_attr() as it takes no const ir_node, so we need to do a cast. - * Firm was made by people hating const :-( - */ -arm_attr_t *get_arm_attr(const ir_node *node) { +/* Returns the attributes of a generic Arm node. */ +arm_attr_t *get_arm_attr(ir_node *node) +{ assert(is_arm_irn(node) && "need arm node to get attributes"); - return (arm_attr_t *)get_irn_generic_attr((ir_node *)node); + return get_irn_generic_attr(node); } -/** - * Returns the argument register requirements of a arm node. - */ -const arch_register_req_t **get_arm_in_req_all(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->in_req; +const arm_attr_t *get_arm_attr_const(const ir_node *node) +{ + assert(is_arm_irn(node) && "need arm node to get attributes"); + return get_irn_generic_attr_const(node); } /** - * Returns the result register requirements of an arm node. + * Returns the attributes of an ARM SymConst node. */ -const arch_register_req_t **get_arm_out_req_all(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->out_req; +arm_SymConst_attr_t *get_arm_SymConst_attr(ir_node *node) +{ + assert(is_arm_SymConst(node) || is_arm_FrameAddr(node)); + return get_irn_generic_attr(node); } -/** - * Returns the argument register requirement at position pos of an arm node. - */ -const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); - return attr->in_req[pos]; +const arm_SymConst_attr_t *get_arm_SymConst_attr_const(const ir_node *node) +{ + assert(is_arm_SymConst(node) || is_arm_FrameAddr(node)); + return get_irn_generic_attr_const(node); } -/** - * Returns the result register requirement at position pos of an arm node. - */ -const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); - return attr->out_req[pos]; -} +static const arm_fpaConst_attr_t *get_arm_fpaConst_attr_const(const ir_node *node) +{ + const arm_attr_t *attr = get_arm_attr_const(node); + const arm_fpaConst_attr_t *fpa_attr = CONST_CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); -/** - * Sets the OUT register requirements at position pos. - */ -void set_arm_req_out(ir_node *node, const arch_register_req_t *req, int pos) { - arm_attr_t *attr = get_arm_attr(node); - attr->out_req[pos] = req; + return fpa_attr; } -/** - * Sets the complete OUT requirements of node. - */ -void set_arm_req_out_all(ir_node *node, const arch_register_req_t **reqs) { - arm_attr_t *attr = get_arm_attr(node); - attr->out_req = reqs; -} +static arm_fpaConst_attr_t *get_arm_fpaConst_attr(ir_node *node) +{ + arm_attr_t *attr = get_arm_attr(node); + arm_fpaConst_attr_t *fpa_attr = CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); -/** - * Sets the IN register requirements at position pos. - */ -void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos) { - arm_attr_t *attr = get_arm_attr(node); - attr->in_req[pos] = req; + return fpa_attr; } -/** - * Returns the register flag of an arm node. - */ -arch_irn_flags_t get_arm_flags(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->flags; +/* Returns the attributes of a CondJmp node. */ +arm_CondJmp_attr_t *get_arm_CondJmp_attr(ir_node *node) +{ + assert(is_arm_B(node)); + return get_irn_generic_attr(node); } -/** - * Sets the register flag of an arm node. - */ -void set_arm_flags(const ir_node *node, arch_irn_flags_t flags) { - arm_attr_t *attr = get_arm_attr(node); - attr->flags = flags; +const arm_CondJmp_attr_t *get_arm_CondJmp_attr_const(const ir_node *node) +{ + assert(is_arm_B(node)); + return get_irn_generic_attr_const(node); } -/** - * Returns the result register slots of an arm node. - */ -const arch_register_t **get_arm_slots(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->slots; +/* Returns the attributes of a SwitchJmp node. */ +arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr(ir_node *node) +{ + assert(is_arm_SwitchJmp(node)); + return get_irn_generic_attr(node); } -/** - * Returns the name of the OUT register at position pos. - */ -const char *get_arm_out_reg_name(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); - - assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); - assert(attr->slots[pos] && "No register assigned"); - - return arch_register_get_name(attr->slots[pos]); +const arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr_const(const ir_node *node) +{ + assert(is_arm_SwitchJmp(node)); + return get_irn_generic_attr_const(node); } /** - * Returns the index of the OUT register at position pos within its register class. + * Returns the argument register requirements of a arm node. */ -int get_arm_out_regnr(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); - - assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); - assert(attr->slots[pos] && "No register assigned"); - - return arch_register_get_index(attr->slots[pos]); +const arch_register_req_t **get_arm_in_req_all(const ir_node *node) +{ + const arm_attr_t *attr = get_arm_attr_const(node); + return attr->in_req; } /** - * Returns the OUT register at position pos. + * Returns the argument register requirement at position pos of an arm node. */ -const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); - - assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); - assert(attr->slots[pos] && "No register assigned"); - - return attr->slots[pos]; +const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) +{ + const arm_attr_t *attr = get_arm_attr_const(node); + return attr->in_req[pos]; } /** - * Returns the number of results. + * Sets the IN register requirements at position pos. */ -int get_arm_n_res(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return ARR_LEN(attr->slots); +void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos) +{ + arm_attr_t *attr = get_arm_attr(node); + attr->in_req[pos] = req; } + /** - * Returns the tarvalue + * Returns the fpaConst value */ -tarval *get_arm_value(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->value; +tarval *get_fpaConst_value(const ir_node *node) +{ + const arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr_const(node); + return attr->tv; } /** - * Sets the tarvalue + * Sets the tarval value */ -void set_arm_value(ir_node *node, tarval *tv) { - arm_attr_t *attr = get_arm_attr(node); - attr->value = tv; +void set_fpaConst_value(ir_node *node, tarval *tv) +{ + arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr(node); + attr->tv = tv; } /** * Returns the proj num */ -int get_arm_proj_num(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +int get_arm_CondJmp_proj_num(const ir_node *node) +{ + const arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr_const(node); return attr->proj_num; } /** * Sets the proj num */ -void set_arm_proj_num(ir_node *node, int proj_num) { - arm_attr_t *attr = get_arm_attr(node); - attr->proj_num = proj_num; -} - -/** - * Returns the SymConst label - */ -ident *get_arm_symconst_id(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->symconst_id; -} - -/** - * Sets the SymConst label - */ -void set_arm_symconst_id(ir_node *node, ident *symconst_id) { - arm_attr_t *attr = get_arm_attr(node); - attr->symconst_id = symconst_id; +void set_arm_CondJmp_proj_num(ir_node *node, int proj_num) +{ + arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr(node); + attr->proj_num = proj_num; } - /** - * Returns the number of projs. + * Returns the number of projs of a SwitchJmp. */ -int get_arm_n_projs(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +int get_arm_SwitchJmp_n_projs(const ir_node *node) +{ + const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node); return attr->n_projs; } /** * Sets the number of projs. */ -void set_arm_n_projs(ir_node *node, int n_projs) { - arm_attr_t *attr = get_arm_attr(node); +void set_arm_SwitchJmp_n_projs(ir_node *node, int n_projs) +{ + arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node); attr->n_projs = n_projs; } /** * Returns the default_proj_num. */ -long get_arm_default_proj_num(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +long get_arm_SwitchJmp_default_proj_num(const ir_node *node) +{ + const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node); return attr->default_proj_num; } /** * Sets the default_proj_num. */ -void set_arm_default_proj_num(ir_node *node, long default_proj_num) { - arm_attr_t *attr = get_arm_attr(node); +void set_arm_SwitchJmp_default_proj_num(ir_node *node, long default_proj_num) +{ + arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node); attr->default_proj_num = default_proj_num; } -/** - * Gets the shift modifier attribute. - */ -arm_shift_modifier get_arm_shift_modifier(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return ARM_GET_SHF_MOD(attr); -} - /* Set the ARM machine node attributes to default values. */ -void init_arm_attributes(ir_node *node, int flags, const arch_register_req_t ** in_reqs, - const arch_register_req_t ** out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) { +static void init_arm_attributes(ir_node *node, int flags, + const arch_register_req_t ** in_reqs, + const be_execution_unit_t ***execution_units, + int n_res) +{ ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); arm_attr_t *attr = get_arm_attr(node); + backend_info_t *info; + (void) execution_units; + arch_irn_set_flags(node, flags); attr->in_req = in_reqs; - attr->out_req = out_reqs; - attr->flags = flags; - attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE; - attr->value = NULL; - attr->proj_num = -42; - attr->symconst_id = NULL; - attr->n_projs = 0; - attr->default_proj_num = 0; + attr->instr_fl = 0; + + info = be_get_info(node); + info->out_infos = NEW_ARR_D(reg_out_info_t, obst, n_res); + memset(info->out_infos, 0, n_res * sizeof(info->out_infos[0])); +} + +static void init_arm_load_store_attributes(ir_node *res, ir_mode *ls_mode, + ir_entity *entity, + int entity_sign, long offset, + bool is_frame_entity) +{ + arm_load_store_attr_t *attr = get_irn_generic_attr(res); + attr->load_store_mode = ls_mode; + attr->entity = entity; + attr->entity_sign = entity_sign; + attr->is_frame_entity = is_frame_entity; + attr->offset = offset; + attr->base.is_load_store = true; +} - attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res); - memset(attr->slots, 0, n_res * sizeof(attr->slots[0])); +static void init_arm_shifter_operand(ir_node *res, unsigned immediate_value, + arm_shift_modifier shift_modifier, + unsigned shift_immediate) +{ + arm_shifter_operand_t *attr = get_irn_generic_attr(res); + attr->immediate_value = immediate_value; + attr->shift_modifier = shift_modifier; + attr->shift_immediate = shift_immediate; } -static int arm_comp_condJmp(arm_attr_t *attr_a, arm_attr_t *attr_b) { +static void init_arm_cmp_attr(ir_node *res, bool ins_permuted, bool is_unsigned) +{ + arm_cmp_attr_t *attr = get_irn_generic_attr(res); + attr->ins_permuted = ins_permuted; + attr->is_unsigned = is_unsigned; +} + +static void init_arm_SymConst_attributes(ir_node *res, ir_entity *entity) +{ + arm_SymConst_attr_t *attr = get_irn_generic_attr(res); + attr->entity = entity; + attr->fp_offset = 0; +} + +static void init_arm_CopyB_attributes(ir_node *res, unsigned size) +{ + arm_CopyB_attr_t *attr = get_irn_generic_attr(res); + attr->size = size; +} + +static int cmp_attr_arm(ir_node *a, ir_node *b) +{ + arm_attr_t *attr_a = get_irn_generic_attr(a); + arm_attr_t *attr_b = get_irn_generic_attr(b); + return attr_a->instr_fl != attr_b->instr_fl; +} + +static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) +{ + const arm_SymConst_attr_t *attr_a; + const arm_SymConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_irn_generic_attr_const(a); + attr_b = get_irn_generic_attr_const(b); + return attr_a->entity != attr_b->entity + || attr_a->fp_offset != attr_b->fp_offset; +} + +static int cmp_attr_arm_CopyB(ir_node *a, ir_node *b) +{ + const arm_CopyB_attr_t *attr_a; + const arm_CopyB_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_irn_generic_attr_const(a); + attr_b = get_irn_generic_attr_const(b); + return attr_a->size != attr_b->size; +} + +static int cmp_attr_arm_CondJmp(ir_node *a, ir_node *b) +{ + (void) a; + (void) b; + /* never identical */ return 1; } +static int cmp_attr_arm_SwitchJmp(ir_node *a, ir_node *b) +{ + (void) a; + (void) b; + /* never identical */ + return 1; +} -/*************************************************************************************** - * _ _ _ - * | | | | | | - * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___ - * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __| - * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \ - * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/ - * - ***************************************************************************************/ +static int cmp_attr_arm_fpaConst(ir_node *a, ir_node *b) +{ + const arm_fpaConst_attr_t *attr_a; + const arm_fpaConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_arm_fpaConst_attr_const(a); + attr_b = get_arm_fpaConst_attr_const(b); + + return attr_a->tv != attr_b->tv; +} -#ifdef BIT -#undef BIT -#endif -#define BIT(x) (1 << (x % 32)) - -static unsigned arm_req_sp_limited[] = { BIT(REG_SP) }; -static const arch_register_req_t _arm_req_sp = { - arch_register_req_type_limited, - &arm_reg_classes[CLASS_arm_gp], - arm_req_sp_limited, - -1, - -1 -}; - -/* construct Store: Store(ptr, val, mem) = ST ptr,val */ -ir_node *new_r_arm_StoreStackMInc(ir_graph *irg, ir_node *block, ir_node *mem, - ir_node *sp, int n_regs, ir_node **regs, - ir_mode *mode) { - ir_node *res; - ir_node *in[16]; - int flags = 0; - static const arch_register_req_t *_in_req_arm_StoreStackM4Inc[] = - { - &arm_StoreStackM4Inc_reg_req_in_0, - &arm_StoreStackM4Inc_reg_req_in_1, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - }; - assert(n_regs <= 15); - - in[0] = mem; - in[1] = sp; - memcpy(&in[2], regs, n_regs * sizeof(in[0])); - res = new_ir_node(NULL, irg, block, op_arm_StoreStackM4Inc, mode, 2 + n_regs, in); - flags |= arch_irn_flags_rematerializable; /* op can be easily recalculated */ - - /* init node attributes */ - init_arm_attributes(res, flags, _in_req_arm_StoreStackM4Inc, NULL, NULL, 0, 1); - - res = optimize_node(res); - irn_vrfy_irg(res, irg); - - return res; -} - -/************************************************ - * ___ _ _ _ * - * / _ \ _ __ | |_(_)_ __ ___ (_)_______ _ __ * - * | | | | '_ \| __| | '_ ` _ \| |_ / _ \ '__| * - * | |_| | |_) | |_| | | | | | | |/ / __/ | * - * \___/| .__/ \__|_|_| |_| |_|_/___\___|_| * - * |_| * - ************************************************/ - -typedef struct _opt_tuple { - ir_op *op_imm_left; /**< immediate is left */ - ir_op *op_imm_right; /**< immediate is right */ - ir_op *op_shf_left; /**< shift operand on left */ - ir_op *op_shf_right; /**< shift operand on right */ -} opt_tuple; - -//static const opt_tuple *opt_ops[iro_arm_last]; - -void arm_set_optimizers(void) { - /* -#define STD(op) p_##op = { op_arm_##op##_i, op_arm_##op##_i, op_arm_##op, op_arm_##op } -#define LEFT(op) p_##op = { op_arm_##op##_i, NULL, op_arm_##op, NULL } -#define SET(op) opt_ops[iro_arm_##op] = &p_##op; - - static const opt_tuple - STD(Add), - STD(And), - STD(Or), - STD(Eor), - LEFT(Bic), - LEFT(Shl), - LEFT(Shr), - LEFT(Shrs), - p_Sub = { op_arm_Sub_i, op_arm_Rsb_i, op_arm_Sub, op_arm_Rsb }, - - memset(opt_ops, 0, sizeof(opt_ops)); - SET(Add); - SET(And); - SET(Or); - SET(Eor); - SET(Sub); - SET(Bic); - SET(Shl); - SET(Shr); - SET(Shrs); - */ +arm_load_store_attr_t *get_arm_load_store_attr(ir_node *node) +{ + return (arm_load_store_attr_t*) get_irn_generic_attr(node); } +const arm_load_store_attr_t *get_arm_load_store_attr_const(const ir_node *node) +{ + return (const arm_load_store_attr_t*) get_irn_generic_attr_const(node); +} + +arm_shifter_operand_t *get_arm_shifter_operand_attr(ir_node *node) +{ + return (arm_shifter_operand_t*) get_irn_generic_attr(node); +} + +static int cmp_attr_arm_load_store(ir_node *a, ir_node *b) +{ + const arm_load_store_attr_t *attr_a; + const arm_load_store_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_arm_load_store_attr(a); + attr_b = get_arm_load_store_attr(b); + if (attr_a->entity != attr_b->entity + || attr_a->entity_sign != attr_b->entity_sign + || attr_a->offset != attr_b->offset) + return 1; + + return 0; +} + +static int cmp_attr_arm_shifter_operand(ir_node *a, ir_node *b) +{ + const arm_shifter_operand_t *attr_a; + const arm_shifter_operand_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_arm_shifter_operand_attr(a); + attr_b = get_arm_shifter_operand_attr(b); + if (attr_a->shift_modifier != attr_b->shift_modifier + || attr_a->immediate_value != attr_b->immediate_value + || attr_a->shift_immediate != attr_b->shift_immediate) + return 1; + + return 0; +} + +static int cmp_attr_arm_cmp(ir_node *a, ir_node *b) +{ + const arm_cmp_attr_t *attr_a; + const arm_cmp_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_irn_generic_attr_const(a); + attr_b = get_irn_generic_attr_const(b); + if (attr_a->ins_permuted != attr_b->ins_permuted + || attr_a->is_unsigned != attr_b->is_unsigned) + return 1; + return 0; +} + +/** copies the ARM attributes of a node. */ +static void arm_copy_attr(const ir_node *old_node, ir_node *new_node) +{ + ir_graph *irg = get_irn_irg(new_node); + struct obstack *obst = get_irg_obstack(irg); + const arm_attr_t *attr_old = get_arm_attr_const(old_node); + arm_attr_t *attr_new = get_arm_attr(new_node); + backend_info_t *old_info = be_get_info(old_node); + backend_info_t *new_info = be_get_info(new_node); + + /* copy the attributes */ + memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node))); + + /* copy out flags */ + new_info->out_infos = + DUP_ARR_D(reg_out_info_t, obst, old_info->out_infos); +} + + + /* Include the generated constructor functions */ #include "gen_arm_new_nodes.c.inl"