X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Farm_new_nodes.c;h=81f48dc5c650fce61ca6ee8c0ce7f8d144c7c61a;hb=fc2759fa267ba4b074c2ac570c1b9d47cc943612;hp=5ffd02010017793a44f3af4497973b47d86ef806;hpb=2adf84106c02caf097c2d6cf1764706bdc437bcc;p=libfirm diff --git a/ir/be/arm/arm_new_nodes.c b/ir/be/arm/arm_new_nodes.c index 5ffd02010..81f48dc5c 100644 --- a/ir/be/arm/arm_new_nodes.c +++ b/ir/be/arm/arm_new_nodes.c @@ -1,20 +1,34 @@ +/* + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + /** - * This file implements the creation of the architecture specific firm opcodes - * and the corresponding node constructors for the arm assembler irg. - * $Id$ + * @file + * @brief This file implements the creation of the architecture specific firm + * opcodes and the corresponding node constructors for the arm + * assembler irg. + * @author Oliver Richter, Tobias Gneist + * @version $Id$ */ #ifdef HAVE_CONFIG_H #include "config.h" #endif -#ifdef HAVE_MALLOC_H -#include -#endif - -#ifdef HAVE_ALLOCA_H -#include -#endif - #include #include "irprog_t.h" @@ -27,12 +41,13 @@ #include "firm_common_t.h" #include "irvrfy_t.h" #include "irprintf.h" +#include "xmalloc.h" -#include "../bearch.h" +#include "../bearch_t.h" #include "arm_nodes_attr.h" #include "arm_new_nodes.h" -#include "gen_arm_regalloc_if_t.h" +#include "arm_optimize.h" #include "../beabi.h" #include "bearch_arm_t.h" @@ -41,10 +56,27 @@ * Returns the shift modifier string. */ const char *arm_shf_mod_name(arm_shift_modifier mod) { - static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" }; + static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" }; return names[mod]; } +/** + * Return the fpa immediate from the encoding. + */ +const char *arm_get_fpa_imm_name(long imm_value) { + static const char *fpa_imm[] = { + "0", + "1", + "2", + "3", + "4", + "5", + "10", + "0.5" + }; + return fpa_imm[imm_value]; +} + /*********************************************************************************** * _ _ _ __ * | | (_) | | / _| @@ -86,11 +118,27 @@ static void dump_reg_req(FILE *F, const ir_node *node, } if (reqs[i]->type & arch_register_req_type_should_be_same) { - ir_fprintf(F, " same as %+F", get_irn_n(node, reqs[i]->other_same)); + const unsigned other = reqs[i]->other_same; + int i; + + ir_fprintf(F, " same as"); + for (i = 0; 1U << i <= other; ++i) { + if (other & (1U << i)) { + ir_fprintf(F, " %+F", get_irn_n(node, i)); + } + } } - if (reqs[i]->type & arch_register_req_type_should_be_different) { - ir_fprintf(F, " different from %+F", get_irn_n(node, reqs[i]->other_different)); + if (reqs[i]->type & arch_register_req_type_must_be_different) { + const unsigned other = reqs[i]->other_different; + int i; + + ir_fprintf(F, " different from"); + for (i = 0; 1U << i <= other; ++i) { + if (other & (1U << i)) { + ir_fprintf(F, " %+F", get_irn_n(node, i)); + } + } } fprintf(F, "\n"); @@ -137,11 +185,11 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { case dump_node_nodeattr_txt: mod = ARM_GET_SHF_MOD(attr); if (ARM_HAS_SHIFT(mod)) { - fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value)); + fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), attr->imm_value); } else if (mod == ARM_SHF_IMM) { /* immediate */ - fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value)); + fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->imm_value)); } break; @@ -155,15 +203,15 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } /* dump OUT requirements */ - if (attr->n_res > 0) { + if (ARR_LEN(attr->slots) > 0) { reqs = get_arm_out_req_all(n); dump_reg_req(F, n, reqs, 1); } /* dump assigned registers */ slots = get_arm_slots(n); - if (slots && attr->n_res > 0) { - for (i = 0; i < attr->n_res; i++) { + if (slots && ARR_LEN(attr->slots) > 0) { + for (i = 0; i < ARR_LEN(attr->slots); i++) { if (slots[i]) { fprintf(F, "reg #%d = %s\n", i, slots[i]->name); } @@ -195,24 +243,19 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, " (%d)\n", attr->flags); - if (get_arm_value(n)) { - if (is_arm_CopyB(n)) { - fprintf(F, "size = %lu\n", get_tarval_long(get_arm_value(n))); + if (is_arm_CopyB(n)) { + fprintf(F, "size = %lu\n", get_arm_imm_value(n)); + } else { + long v = get_arm_imm_value(n); + if (ARM_GET_FPA_IMM(attr)) { + fprintf(F, "immediate float value = %s\n", arm_get_fpa_imm_name(v)); } else { - if (mode_is_float(get_irn_mode(n))) { - fprintf(F, "float value = (%f)\n", (double) get_tarval_double(get_arm_value(n))); - } else if (mode_is_int(get_irn_mode(n))) { - long v = get_tarval_long(get_arm_value(n)); - fprintf(F, "long value = %ld (0x%08lx)\n", v, v); - } else if (mode_is_reference(get_irn_mode(n))) { - fprintf(F, "pointer\n"); - } else { - assert(0 && "unbehandelter Typ im const-Knoten"); - } + fprintf(F, "immediate value = %ld (0x%08lx)\n", v, v); } } - if (get_arm_proj_num(n) >= 0) { - fprintf(F, "proj_num = (%d)\n", get_arm_proj_num(n)); + + if (is_arm_CmpBra(n) && get_arm_CondJmp_proj_num(n) >= 0) { + fprintf(F, "proj_num = (%d)\n", get_arm_CondJmp_proj_num(n)); } /* TODO: dump all additional attributes */ @@ -236,20 +279,79 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { * |___/ ***************************************************************************************************/ +/* Returns the attributes of a generic Arm node. */ +arm_attr_t *get_arm_attr(ir_node *node) { + assert(is_arm_irn(node) && "need arm node to get attributes"); + return get_irn_generic_attr(node); +} + +const arm_attr_t *get_arm_attr_const(const ir_node *node) { + assert(is_arm_irn(node) && "need arm node to get attributes"); + return get_irn_generic_attr_const(node); +} + /** - * Wraps get_irn_generic_attr() as it takes no const ir_node, so we need to do a cast. - * Firm was made by people hating const :-( + * Returns the attributes of an ARM SymConst node. */ -arm_attr_t *get_arm_attr(const ir_node *node) { - assert(is_arm_irn(node) && "need arm node to get attributes"); - return (arm_attr_t *)get_irn_generic_attr((ir_node *)node); +arm_SymConst_attr_t *get_arm_SymConst_attr(ir_node *node) { + assert(is_arm_SymConst(node)); + return get_irn_generic_attr(node); +} + +const arm_SymConst_attr_t *get_arm_SymConst_attr_const(const ir_node *node) { + assert(is_arm_SymConst(node)); + return get_irn_generic_attr_const(node); +} + +static const arm_fpaConst_attr_t *get_arm_fpaConst_attr_const(const ir_node *node) { + const arm_attr_t *attr = get_arm_attr_const(node); + const arm_fpaConst_attr_t *fpa_attr = CONST_CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); + + return fpa_attr; +} + +static arm_fpaConst_attr_t *get_arm_fpaConst_attr(ir_node *node) { + arm_attr_t *attr = get_arm_attr(node); + arm_fpaConst_attr_t *fpa_attr = CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); + + return fpa_attr; +} + +static int is_arm_CondJmp(const ir_node *node) { + int code = get_arm_irn_opcode(node); + + return (code == iro_arm_CmpBra || code == iro_arm_fpaCmfBra || + code == iro_arm_fpaCnfBra || iro_arm_fpaCmfeBra || + code == iro_arm_fpaCnfeBra); +} + +/* Returns the attributes of a CondJmp node. */ +arm_CondJmp_attr_t *get_arm_CondJmp_attr(ir_node *node) { + assert(is_arm_CondJmp(node)); + return get_irn_generic_attr(node); +} + +const arm_CondJmp_attr_t *get_arm_CondJmp_attr_const(const ir_node *node) { + assert(is_arm_CondJmp(node)); + return get_irn_generic_attr_const(node); +} + +/* Returns the attributes of a SwitchJmp node. */ +arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr(ir_node *node) { + assert(is_arm_SwitchJmp(node)); + return get_irn_generic_attr(node); +} + +const arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr_const(const ir_node *node) { + assert(is_arm_SwitchJmp(node)); + return get_irn_generic_attr_const(node); } /** * Returns the argument register requirements of a arm node. */ const arch_register_req_t **get_arm_in_req_all(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->in_req; } @@ -257,7 +359,7 @@ const arch_register_req_t **get_arm_in_req_all(const ir_node *node) { * Returns the result register requirements of an arm node. */ const arch_register_req_t **get_arm_out_req_all(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->out_req; } @@ -265,7 +367,7 @@ const arch_register_req_t **get_arm_out_req_all(const ir_node *node) { * Returns the argument register requirement at position pos of an arm node. */ const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->in_req[pos]; } @@ -273,7 +375,7 @@ const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) { * Returns the result register requirement at position pos of an arm node. */ const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->out_req[pos]; } @@ -305,14 +407,14 @@ void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos) { * Returns the register flag of an arm node. */ arch_irn_flags_t get_arm_flags(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->flags; } /** * Sets the register flag of an arm node. */ -void set_arm_flags(const ir_node *node, arch_irn_flags_t flags) { +void set_arm_flags(ir_node *node, arch_irn_flags_t flags) { arm_attr_t *attr = get_arm_attr(node); attr->flags = flags; } @@ -321,7 +423,7 @@ void set_arm_flags(const ir_node *node, arch_irn_flags_t flags) { * Returns the result register slots of an arm node. */ const arch_register_t **get_arm_slots(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); return attr->slots; } @@ -329,10 +431,10 @@ const arch_register_t **get_arm_slots(const ir_node *node) { * Returns the name of the OUT register at position pos. */ const char *get_arm_out_reg_name(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < attr->n_res && "Invalid OUT position."); + assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return arch_register_get_name(attr->slots[pos]); @@ -342,10 +444,10 @@ const char *get_arm_out_reg_name(const ir_node *node, int pos) { * Returns the index of the OUT register at position pos within its register class. */ int get_arm_out_regnr(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < attr->n_res && "Invalid OUT position."); + assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return arch_register_get_index(attr->slots[pos]); @@ -355,210 +457,167 @@ int get_arm_out_regnr(const ir_node *node, int pos) { * Returns the OUT register at position pos. */ const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) { - arm_attr_t *attr = get_arm_attr(node); + const arm_attr_t *attr = get_arm_attr_const(node); assert(is_arm_irn(node) && "Not an arm node."); - assert(pos < attr->n_res && "Invalid OUT position."); + assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return attr->slots[pos]; } /** - * Sets the number of results. + * Sets the flags for the n'th out. */ -void set_arm_n_res(ir_node *node, int n_res) { +void set_arm_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) { arm_attr_t *attr = get_arm_attr(node); - attr->n_res = n_res; + assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position."); + attr->out_flags[pos] = flags; +} + +/** + * Gets the flags for the n'th out. + */ +arch_irn_flags_t get_arm_out_flags(const ir_node *node, int pos) { + const arm_attr_t *attr = get_arm_attr_const(node); + assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position."); + return attr->out_flags[pos]; } /** * Returns the number of results. */ int get_arm_n_res(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->n_res; + const arm_attr_t *attr = get_arm_attr_const(node); + return ARR_LEN(attr->slots); } + /** - * Returns the tarvalue + * Returns the immediate value */ -tarval *get_arm_value(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->value; +long get_arm_imm_value(const ir_node *node) { + const arm_attr_t *attr = get_arm_attr_const(node); + return attr->imm_value; } /** - * Sets the tarvalue + * Sets the tarval value */ -void set_arm_value(ir_node *node, tarval *tv) { +void set_arm_imm_value(ir_node *node, long imm_value) { arm_attr_t *attr = get_arm_attr(node); - attr->value = tv; + attr->imm_value = imm_value; +} + +/** + * Returns the fpaConst value + */ +tarval *get_fpaConst_value(const ir_node *node) { + const arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr_const(node); + return attr->tv; +} + +/** + * Sets the tarval value + */ +void set_fpaConst_value(ir_node *node, tarval *tv) { + arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr(node); + attr->tv = tv; } /** * Returns the proj num */ -int get_arm_proj_num(const ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +int get_arm_CondJmp_proj_num(const ir_node *node) { + const arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr_const(node); return attr->proj_num; } /** * Sets the proj num */ -void set_arm_proj_num(ir_node *node, int proj_num) { - arm_attr_t *attr = get_arm_attr(node); - attr->proj_num = proj_num; +void set_arm_CondJmp_proj_num(ir_node *node, int proj_num) { + arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr(node); + attr->proj_num = proj_num; } /** * Returns the SymConst label */ -const char *get_arm_symconst_label(ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); - return attr->symconst_label; +ident *get_arm_symconst_id(const ir_node *node) { + const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(node); + return attr->symconst_id; } /** * Sets the SymConst label */ -void set_arm_symconst_label(ir_node *node, const char *symconst_label) { - arm_attr_t *attr = get_arm_attr(node); - attr->symconst_label = symconst_label; +void set_arm_symconst_id(ir_node *node, ident *symconst_id) { + arm_SymConst_attr_t *attr = get_arm_SymConst_attr(node); + attr->symconst_id = symconst_id; } - /** - * Returns the number of projs. + * Returns the number of projs of a SwitchJmp. */ -int get_arm_n_projs(ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +int get_arm_SwitchJmp_n_projs(const ir_node *node) { + const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node); return attr->n_projs; } /** * Sets the number of projs. */ -void set_arm_n_projs(ir_node *node, int n_projs) { - arm_attr_t *attr = get_arm_attr(node); +void set_arm_SwitchJmp_n_projs(ir_node *node, int n_projs) { + arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node); attr->n_projs = n_projs; } /** * Returns the default_proj_num. */ -long get_arm_default_proj_num(ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +long get_arm_SwitchJmp_default_proj_num(const ir_node *node) { + const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node); return attr->default_proj_num; } /** * Sets the default_proj_num. */ -void set_arm_default_proj_num(ir_node *node, long default_proj_num) { - arm_attr_t *attr = get_arm_attr(node); +void set_arm_SwitchJmp_default_proj_num(ir_node *node, long default_proj_num) { + arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node); attr->default_proj_num = default_proj_num; } /** * Gets the shift modifier attribute. */ -arm_shift_modifier get_arm_shift_modifier(ir_node *node) { - arm_attr_t *attr = get_arm_attr(node); +arm_shift_modifier get_arm_shift_modifier(const ir_node *node) { + const arm_attr_t *attr = get_arm_attr_const(node); return ARM_GET_SHF_MOD(attr); } /* Set the ARM machine node attributes to default values. */ -void init_arm_attributes(ir_node *node, int flags, const arch_register_req_t ** in_reqs, - const arch_register_req_t ** out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) { - arm_attr_t *attr = get_arm_attr(node); +static void init_arm_attributes(ir_node *node, int flags, + const arch_register_req_t ** in_reqs, + const arch_register_req_t ** out_reqs, + const be_execution_unit_t ***execution_units, + int n_res) { + ir_graph *irg = get_irn_irg(node); + struct obstack *obst = get_irg_obstack(irg); + arm_attr_t *attr = get_arm_attr(node); + (void) execution_units; + attr->in_req = in_reqs; attr->out_req = out_reqs; - attr->n_res = n_res; attr->flags = flags; attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE; - attr->value = NULL; - attr->proj_num = -42; - attr->symconst_label = NULL; - attr->n_projs = 0; - attr->default_proj_num = 0; - - memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0])); -} - -static int arm_comp_condJmp(arm_attr_t *attr_a, arm_attr_t *attr_b) { - return 1; -} - + attr->imm_value = 0; -/*************************************************************************************** - * _ _ _ - * | | | | | | - * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___ - * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __| - * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \ - * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/ - * - ***************************************************************************************/ - -#ifdef BIT -#undef BIT -#endif -#define BIT(x) (1 << (x % 32)) - -static unsigned arm_req_sp_limited[] = { BIT(REG_SP) }; -static const arch_register_req_t _arm_req_sp = { - arch_register_req_type_limited, - &arm_reg_classes[CLASS_arm_gp], - arm_req_sp_limited, - -1, - -1 -}; - -/* construct Store: Store(ptr, val, mem) = ST ptr,val */ -ir_node *new_r_arm_StoreStackMInc(ir_graph *irg, ir_node *block, ir_node *mem, - ir_node *sp, int n_regs, ir_node **regs, - ir_mode *mode) { - ir_node *res; - ir_node *in[16]; - int flags = 0; - static const arch_register_req_t *_in_req_arm_StoreStackM4Inc[] = - { - &arm_StoreStackM4Inc_reg_req_in_0, - &arm_StoreStackM4Inc_reg_req_in_1, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - &arm_StoreStackM4Inc_reg_req_in_2, - }; - - assert(n_regs <= 15); - - in[0] = mem; - in[1] = sp; - memcpy(&in[2], regs, n_regs * sizeof(in[0])); - res = new_ir_node(NULL, irg, block, op_arm_StoreStackM4Inc, mode, 2 + n_regs, in); - flags |= arch_irn_flags_rematerializable; /* op can be easily recalculated */ - - /* init node attributes */ - init_arm_attributes(res, flags, _in_req_arm_StoreStackM4Inc, NULL, NULL, 0, 1); - - res = optimize_node(res); - irn_vrfy_irg(res, irg); + attr->out_flags = NEW_ARR_D(int, obst, n_res); + memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0])); - return res; + attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res); + memset(attr->slots, 0, n_res * sizeof(attr->slots[0])); } /************************************************ @@ -609,6 +668,70 @@ void arm_set_optimizers(void) { */ } +static int cmp_attr_arm(ir_node *a, ir_node *b) { + arm_attr_t *attr_a = get_irn_generic_attr(a); + arm_attr_t *attr_b = get_irn_generic_attr(b); + return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value); +} + +static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) { + const arm_SymConst_attr_t *attr_a; + const arm_SymConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_irn_generic_attr_const(a); + attr_b = get_irn_generic_attr_const(b); + return attr_a->symconst_id != attr_b->symconst_id; +} + +static int cmp_attr_arm_CondJmp(ir_node *a, ir_node *b) { + (void) a; + (void) b; + /* never identical */ + return 1; +} + +static int cmp_attr_arm_SwitchJmp(ir_node *a, ir_node *b) { + (void) a; + (void) b; + /* never identical */ + return 1; +} + +static int cmp_attr_arm_fpaConst(ir_node *a, ir_node *b) { + const arm_fpaConst_attr_t *attr_a; + const arm_fpaConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_arm_fpaConst_attr_const(a); + attr_b = get_arm_fpaConst_attr_const(b); + + return attr_a->tv != attr_b->tv; +} + +/** copies the ARM attributes of a node. */ +static void arm_copy_attr(const ir_node *old_node, ir_node *new_node) { + ir_graph *irg = get_irn_irg(new_node); + struct obstack *obst = get_irg_obstack(irg); + const arm_attr_t *attr_old = get_arm_attr_const(old_node); + arm_attr_t *attr_new = get_arm_attr(new_node); + + /* copy the attributes */ + memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node))); + + /* copy out flags */ + attr_new->out_flags = + DUP_ARR_D(int, obst, attr_old->out_flags); + /* copy register assignments */ + attr_new->slots = + DUP_ARR_D(arch_register_t*, obst, attr_old->slots); +} + + /* Include the generated constructor functions */ #include "gen_arm_new_nodes.c.inl"