X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fppc32%2Fbearch_ppc32.c;h=f6234599bf5becc9d6e792c2835fa21c78986f50;hb=205396c4f4f5abe7abd6dc2350c8c398a7623afc;hp=7d9b5c6fc4ebb020911417fd3d01602af4f6bc12;hpb=23f4f75d3bf2982cfa7ba7c8afb5c9f92ed6f14c;p=libfirm diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c index 7d9b5c6fc..f6234599b 100644 --- a/ir/be/ppc32/bearch_ppc32.c +++ b/ir/be/ppc32/bearch_ppc32.c @@ -1,6 +1,5 @@ /* The main ppc backend driver file. */ /* $Id$ */ - #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -16,12 +15,16 @@ #include "bitset.h" #include "debug.h" -#include "../bearch.h" /* the general register allocator interface */ +#include "../bearch_t.h" /* the general register allocator interface */ #include "../benode_t.h" #include "../belower.h" #include "../besched_t.h" #include "../be.h" #include "../beabi.h" +#include "../bemachine.h" +#include "../bemodule.h" +#include "../beblocksched.h" +#include "../beirg_t.h" #include "pset.h" @@ -54,31 +57,26 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -static ir_node *my_skip_proj(const ir_node *n) { - while (is_Proj(n)) - n = get_Proj_pred(n); - return (ir_node *)n; -} - /** * Return register requirements for a ppc node. * If the node returns a tuple (mode_T) then the proj's * will be asked for this information. */ -static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) { - const ppc32_register_req_t *irn_req; +static const +arch_register_req_t *ppc32_get_irn_reg_req(const void *self, + const ir_node *irn, int pos) { long node_pos = pos == -1 ? 0 : pos; ir_mode *mode = get_irn_mode(irn); FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); if (is_Block(irn) || mode == mode_X || mode == mode_M) { DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn)); - return NULL; + return arch_no_register_req; } if (mode == mode_T && pos < 0) { DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn)); - return NULL; + return arch_no_register_req; } DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn)); @@ -88,66 +86,33 @@ static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_r /* of the node corresponding to the proj number */ if (pos == -1) { node_pos = ppc32_translate_proj_pos(irn); - } - else { + } else { node_pos = pos; } - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos)); } /* get requirements for our own nodes */ if (is_ppc32_irn(irn)) { + const arch_register_req_t *req; if (pos >= 0) { - irn_req = get_ppc32_in_req(irn, pos); - } - else { - irn_req = get_ppc32_out_req(irn, node_pos); + req = get_ppc32_in_req(irn, pos); + } else { + req = get_ppc32_out_req(irn, node_pos); } DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos)); - - memcpy(req, &(irn_req->req), sizeof(*req)); - - if (arch_register_req_is(&(irn_req->req), should_be_same)) { - assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI"); - req->other_same = get_irn_n(irn, irn_req->same_pos); - } - - if (arch_register_req_is(&(irn_req->req), should_be_different)) { - assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI"); - req->other_different = get_irn_n(irn, irn_req->different_pos); - } + return req; } - /* get requirements for FIRM nodes */ - else { - /* treat Phi like Const with default requirements */ - if (is_Phi(irn)) { - DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn)); - if (mode_is_float(mode)) { - memcpy(req, &(ppc32_default_req_ppc32_floating_point.req), sizeof(*req)); - } - else if (mode_is_int(mode) || mode_is_reference(mode)) { - memcpy(req, &(ppc32_default_req_ppc32_general_purpose.req), sizeof(*req)); - } - else if (mode == mode_T || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn)); - return NULL; - } - else { - assert(0 && "unsupported Phi-Mode"); - } - } - else { - DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn)); - req = NULL; - } - } + /* unknowns should be transformed by now */ + assert(!is_Unknown(irn)); - return req; + DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn)); + return arch_no_register_req; } static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { @@ -160,7 +125,7 @@ static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_registe } pos = ppc32_translate_proj_pos(irn); - irn = my_skip_proj(irn); + irn = skip_Proj(irn); } if (is_ppc32_irn(irn)) { @@ -186,7 +151,7 @@ static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node } pos = ppc32_translate_proj_pos(irn); - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); } if (is_ppc32_irn(irn)) { @@ -202,7 +167,7 @@ static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node } static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) { - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); if (is_cfop(irn)) { return arch_irn_class_branch; @@ -215,7 +180,7 @@ static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) { } static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) { - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); if (is_ppc32_irn(irn)) { return get_ppc32_flags(irn); @@ -227,12 +192,18 @@ static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) { return 0; } -static entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) { +static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) { if(!is_ppc32_irn(irn)) return NULL; if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL; return get_ppc32_frame_entity(irn); } +static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { + if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity) + return; + set_ppc32_frame_entity(irn, ent); +} + /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. @@ -241,6 +212,10 @@ static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) { set_ppc32_offset(irn, bias); } +static int ppc32_get_sp_bias(const void *self, const ir_node *irn) { + return 0; +} + typedef struct { const be_abi_call_t *call; @@ -279,10 +254,10 @@ static void ppc32_abi_done(void *self) static ir_type *ppc32_abi_get_between_type(void *self) { static ir_type *between_type = NULL; - static entity *old_bp_ent = NULL; + static ir_entity *old_bp_ent = NULL; if(!between_type) { - entity *ret_addr_ent; + ir_entity *ret_addr_ent; ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P); @@ -290,8 +265,8 @@ static ir_type *ppc32_abi_get_between_type(void *self) old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type); ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type); - set_entity_offset_bytes(old_bp_ent, 0); - set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type)); + set_entity_offset(old_bp_ent, 0); + set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type)); set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type)); } @@ -323,9 +298,9 @@ static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap isleaf = flags.bits.irg_is_leaf; if(flags.bits.try_omit_fp) - return &ppc32_general_purpose_regs[REG_R1]; + return &ppc32_gp_regs[REG_R1]; else - return &ppc32_general_purpose_regs[REG_R31]; + return &ppc32_gp_regs[REG_R31]; } /** @@ -359,7 +334,13 @@ static const arch_irn_ops_if_t ppc32_irn_ops_if = { ppc32_classify, ppc32_get_flags, ppc32_get_frame_entity, - ppc32_set_stack_bias + ppc32_set_frame_entity, + ppc32_set_stack_bias, + ppc32_get_sp_bias, + NULL, /* get_inverse */ + NULL, /* get_op_estimated_cost */ + NULL, /* possible_memory_operand */ + NULL, /* perform_memory_operand */ }; ppc32_irn_ops_t ppc32_irn_ops = { @@ -422,6 +403,7 @@ static void ppc32_prepare_graph(void *self) { irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg); be_dump(cg->irg, "-pretransformed", dump_ir_block_graph); + ppc32_register_transformers(); irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg); be_dump(cg->irg, "-transformed", dump_ir_block_graph); irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg); @@ -432,7 +414,7 @@ static void ppc32_prepare_graph(void *self) { /** * Called immediatly before emit phase. */ -static void ppc32_finish_irg(ir_graph *irg, ppc32_code_gen_t *cg) { +static void ppc32_finish_irg(void *self) { /* TODO: - fix offsets for nodes accessing stack - ... */ @@ -453,7 +435,7 @@ static void ppc32_before_sched(void *self) { */ static void ppc32_before_ra(void *self) { ppc32_code_gen_t *cg = self; - cg->blk_sched = sched_create_block_schedule(cg->irg); + cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq); } static void ppc32_transform_spill(ir_node *node, void *env) @@ -462,22 +444,21 @@ static void ppc32_transform_spill(ir_node *node, void *env) if(be_is_Spill(node)) { - ir_node *store, *proj; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_mode *mode = get_irn_mode(node); + ir_node *store, *proj; + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1); - if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose]) + if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) { store = new_rd_ppc32_Stw(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph), mode_T); + get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph)); } - else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point]) + else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) { store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph), mode_T); + get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph)); } else assert(0 && "Spill for register class not supported yet!"); @@ -499,21 +480,19 @@ static void ppc32_transform_spill(ir_node *node, void *env) { ir_node *load, *proj; const arch_register_t *reg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_mode *mode = get_irn_mode(node); + dbg_info *dbg = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_mode *mode = get_irn_mode(node); const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1); - if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose]) + if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) { - load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), mode_T); + load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1)); } - else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point]) + else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) { - load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), mode_T); + load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1)); } else assert(0 && "Reload for register class not supported yet!"); @@ -551,14 +530,13 @@ static void ppc32_after_ra(void *self) { static void ppc32_emit_and_done(void *self) { ppc32_code_gen_t *cg = self; ir_graph *irg = cg->irg; - FILE *out = cg->out; + FILE *out = cg->isa->out; if (cg->emit_decls) { - ppc32_gen_decls(cg->out); + ppc32_gen_decls(out); cg->emit_decls = 0; } - ppc32_finish_irg(irg, cg); dump_ir_block_graph_sched(irg, "-ppc-finished"); ppc32_gen_routine(out, irg, cg); @@ -575,7 +553,7 @@ static void ppc32_emit_and_done(void *self) { } } -int is_direct_entity(entity *ent); +int is_direct_entity(ir_entity *ent); /** * Collects all SymConsts which need to be accessed "indirectly" @@ -584,39 +562,40 @@ int is_direct_entity(entity *ent); * @param env the debug module */ void ppc32_collect_symconsts_walk(ir_node *node, void *env) { - ppc32_code_gen_t *cg = env; - if(get_irn_op(node)==op_SymConst) + if(get_irn_op(node) == op_SymConst) { - entity *ent = get_SymConst_entity(node); + ir_entity *ent = get_SymConst_entity(node); if(!is_direct_entity(ent)) pset_insert_ptr(symbol_pset, ent); } } -static void *ppc32_cg_init(FILE *F, const be_irg_t *birg); +static void *ppc32_cg_init(be_irg_t *birg); static const arch_code_generator_if_t ppc32_code_gen_if = { ppc32_cg_init, ppc32_before_abi, ppc32_prepare_graph, + NULL, /* spill */ ppc32_before_sched, /* before scheduling hook */ ppc32_before_ra, /* before register allocation hook */ ppc32_after_ra, + ppc32_finish_irg, ppc32_emit_and_done }; /** * Initializes the code generator. */ -static void *ppc32_cg_init(FILE *F, const be_irg_t *birg) { +static void *ppc32_cg_init(be_irg_t *birg) { ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa; ppc32_code_gen_t *cg = xmalloc(sizeof(*cg)); cg->impl = &ppc32_code_gen_if; cg->irg = birg->irg; cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024); - cg->out = F; cg->arch_env = birg->main_env->arch_env; + cg->isa = isa; cg->birg = birg; cg->area_size = 0; cg->area = NULL; @@ -662,25 +641,28 @@ static void *ppc32_cg_init(FILE *F, const be_irg_t *birg) { static ppc32_isa_t ppc32_isa_template = { &ppc32_isa_if, - &ppc32_general_purpose_regs[REG_R1], // stack pointer - &ppc32_general_purpose_regs[REG_R31], // base pointer - -1, // stack is decreasing - 0 // num codegens... ?? + &ppc32_gp_regs[REG_R1], // stack pointer + &ppc32_gp_regs[REG_R31], // base pointer + -1, // stack is decreasing + 0, // num codegens... ?? + NULL }; /** * Initializes the backend ISA and opens the output file. */ -static void *ppc32_init(void) { +static void *ppc32_init(FILE *file_handle) { static int inited = 0; ppc32_isa_t *isa; if(inited) return NULL; - isa = xcalloc(1, sizeof(*isa)); + isa = xmalloc(sizeof(*isa)); memcpy(isa, &ppc32_isa_template, sizeof(*isa)); + isa->out = file_handle; + ppc32_register_init(isa); ppc32_create_opcodes(); @@ -719,9 +701,9 @@ static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) */ const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) { if (mode_is_float(mode)) - return &ppc32_reg_classes[CLASS_ppc32_floating_point]; + return &ppc32_reg_classes[CLASS_ppc32_fp]; else - return &ppc32_reg_classes[CLASS_ppc32_general_purpose]; + return &ppc32_reg_classes[CLASS_ppc32_gp]; } @@ -741,7 +723,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca int fpregi = REG_F1; const arch_register_t *reg; - be_abi_call_flags_t call_flags = { 0, 0, 1, 0, 0, 0, 1 }; + be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } }; if(get_type_visibility(method_type)!=visibility_external_allocated) call_flags.bits.call_has_imm = 1; @@ -761,7 +743,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca { if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4; else gpregi += 2, stackparamsize=8; // mode == irm_D - reg = &ppc32_floating_point_regs[fpregi++]; + reg = &ppc32_fp_regs[fpregi++]; } else { @@ -773,7 +755,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca else { if(gpregi <= REG_R10) - reg = &ppc32_general_purpose_regs[gpregi++]; + reg = &ppc32_gp_regs[gpregi++]; else reg = NULL; stackparamsize=4; @@ -802,7 +784,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca mode = get_type_mode(tp); be_abi_call_res_reg(abi, 0, - mode_is_float(mode) ? &ppc32_floating_point_regs[REG_F1] : &ppc32_general_purpose_regs[REG_R3]); + mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]); } } @@ -834,22 +816,68 @@ list_sched_selector_t ppc32_sched_selector; /** * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded */ -static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self) { +static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t)); ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule; return &ppc32_sched_selector; } -#ifdef WITH_LIBCORE -static void ppc32_register_options(lc_opt_entry_t *ent) -{ +static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) { + return NULL; +} + +/** + * Returns the necessary byte alignment for storing a register of given class. + */ +static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { + ir_mode *mode = arch_register_class_mode(cls); + return get_mode_size_bytes(mode); +} + +static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) { + /* TODO */ + assert(0); + return NULL; +} + +static const be_machine_t *ppc32_get_machine(const void *self) { + /* TODO */ + assert(0); + return NULL; +} + +/** + * Return irp irgs in the desired order. + */ +static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) { + return NULL; +} + +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *ppc32_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on ARM */ + 31, /* shift would be ok */ + 0, /* SMUL is needed, only in Arch M*/ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ + }; + static backend_params p = { + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + 1, /* need dword lowering */ + NULL, /* but yet no creator function */ + NULL, /* context for create_intrinsic_fkt */ + }; + + p.dep_param = &ad; + return &p; } -#endif /* WITH_LIBCORE */ const arch_isa_if_t ppc32_isa_if = { -#ifdef WITH_LIBCORE - ppc32_register_options, -#endif ppc32_init, ppc32_done, ppc32_get_n_reg_class, @@ -859,4 +887,17 @@ const arch_isa_if_t ppc32_isa_if = { ppc32_get_irn_handler, ppc32_get_code_generator_if, ppc32_get_list_sched_selector, + ppc32_get_ilp_sched_selector, + ppc32_get_reg_class_alignment, + ppc32_get_libfirm_params, + ppc32_get_allowed_execution_units, + ppc32_get_machine, + ppc32_get_irg_list, }; + +void be_init_arch_ppc32(void) +{ + be_register_isa_if("ppc32", &ppc32_isa_if); +} + +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);