X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=202f57bc569eebc7f9bfb00226610fb3cfec85e8;hb=7d4dbfc7158613bdee5a2fa005ef06541eb1b81b;hp=2be20cf2c6093596923c07cec2ecee5b6538e2f9;hpb=f8cc15664f571aa7ef89d6f6bc8d5bd2b8ca7d53;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index 2be20cf2c..202f57bc5 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -52,8 +52,6 @@ #include "ia32_x87.h" #include "ia32_architecture.h" -#define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1)) - /** the debug handle */ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) @@ -78,23 +76,21 @@ typedef struct exchange_tmpl { * An entry on the simulated x87 stack. */ typedef struct st_entry { - int reg_idx; /**< the virtual register index of this stack value */ - ir_node *node; /**< the node that produced this value */ + int reg_idx; /**< the virtual register index of this stack value */ + ir_node *node; /**< the node that produced this value */ } st_entry; /** * The x87 state. */ typedef struct x87_state { - st_entry st[N_ia32_st_REGS]; /**< the register stack */ - int depth; /**< the current stack depth */ - int tos; /**< position of the tos */ - x87_simulator *sim; /**< The simulator. */ + st_entry st[N_ia32_st_REGS]; /**< the register stack */ + int depth; /**< the current stack depth */ + x87_simulator *sim; /**< The simulator. */ } x87_state; /** An empty state, used for blocks without fp instructions. */ -static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL }; -static x87_state *empty = (x87_state *)&_empty; +static x87_state empty = { { {0, NULL}, }, 0, NULL }; /** * Return values of the instruction simulator functions. @@ -125,8 +121,6 @@ typedef struct blk_state { x87_state *end; /**< state at the end or NULL if not assigned */ } blk_state; -#define PTR_TO_BLKSTATE(p) ((blk_state *)(p)) - /** liveness bitset for vfp registers. */ typedef unsigned char vfp_liveness; @@ -134,13 +128,12 @@ typedef unsigned char vfp_liveness; * The x87 simulator. */ struct x87_simulator { - struct obstack obst; /**< An obstack for fast allocating. */ - pmap *blk_states; /**< Map blocks to states. */ - be_lv_t *lv; /**< intrablock liveness. */ - vfp_liveness *live; /**< Liveness information. */ - unsigned n_idx; /**< The cached get_irg_last_idx() result. */ - waitq *worklist; /**< Worklist of blocks that must be processed. */ - ia32_isa_t *isa; /**< the ISA object */ + struct obstack obst; /**< An obstack for fast allocating. */ + pmap *blk_states; /**< Map blocks to states. */ + be_lv_t *lv; /**< intrablock liveness. */ + vfp_liveness *live; /**< Liveness information. */ + unsigned n_idx; /**< The cached get_irg_last_idx() result. */ + waitq *worklist; /**< Worklist of blocks that must be processed. */ }; /** @@ -155,6 +148,12 @@ static int x87_get_depth(const x87_state *state) return state->depth; } +static st_entry *x87_get_entry(x87_state *const state, int const pos) +{ + assert(0 <= pos && pos < state->depth); + return &state->st[N_ia32_st_REGS - state->depth + pos]; +} + /** * Return the virtual register index at st(pos). * @@ -165,25 +164,10 @@ static int x87_get_depth(const x87_state *state) */ static int x87_get_st_reg(const x87_state *state, int pos) { - assert(pos < state->depth); - return state->st[MASK_TOS(state->tos + pos)].reg_idx; + return x87_get_entry((x87_state*)state, pos)->reg_idx; } #ifdef DEBUG_libfirm -/** - * Return the node at st(pos). - * - * @param state the x87 state - * @param pos a stack position - * - * @return the IR node that produced the value at st(pos) - */ -static ir_node *x87_get_st_node(const x87_state *state, int pos) -{ - assert(pos < state->depth); - return state->st[MASK_TOS(state->tos + pos)].node; -} - /** * Dump the stack for debugging. * @@ -191,11 +175,9 @@ static ir_node *x87_get_st_node(const x87_state *state, int pos) */ static void x87_dump_stack(const x87_state *state) { - int i; - - for (i = state->depth - 1; i >= 0; --i) { - DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i), - x87_get_st_node(state, i))); + for (int i = state->depth; i-- != 0;) { + st_entry const *const entry = x87_get_entry((x87_state*)state, i); + DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node)); } DB((dbg, LEVEL_2, "<-- TOS\n")); } @@ -211,9 +193,9 @@ static void x87_dump_stack(const x87_state *state) */ static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) { - assert(0 < state->depth); - state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx; - state->st[MASK_TOS(state->tos + pos)].node = node; + st_entry *const entry = x87_get_entry(state, pos); + entry->reg_idx = reg_idx; + entry->node = node; DB((dbg, LEVEL_2, "After SET_REG: ")); DEBUG_ONLY(x87_dump_stack(state);) @@ -239,12 +221,11 @@ static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) */ static void x87_fxch(x87_state *state, int pos) { - st_entry entry; - assert(pos < state->depth); - - entry = state->st[MASK_TOS(state->tos + pos)]; - state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)]; - state->st[MASK_TOS(state->tos)] = entry; + st_entry *const a = x87_get_entry(state, pos); + st_entry *const b = x87_get_entry(state, 0); + st_entry const t = *a; + *a = *b; + *b = t; DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state);) @@ -261,11 +242,10 @@ static void x87_fxch(x87_state *state, int pos) */ static int x87_on_stack(const x87_state *state, int reg_idx) { - int i, tos = state->tos; - - for (i = 0; i < state->depth; ++i) - if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx) + for (int i = 0; i < state->depth; ++i) { + if (x87_get_st_reg(state, i) == reg_idx) return i; + } return -1; } @@ -281,9 +261,9 @@ static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) assert(state->depth < N_ia32_st_REGS && "stack overrun"); ++state->depth; - state->tos = MASK_TOS(state->tos - 1); - state->st[state->tos].reg_idx = reg_idx; - state->st[state->tos].node = node; + st_entry *const entry = x87_get_entry(state, 0); + entry->reg_idx = reg_idx; + entry->node = node; DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);) } @@ -294,7 +274,6 @@ static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) * @param state the x87 state * @param reg_idx the register vfp index * @param node the node that produces the value of the vfp register - * @param dbl_push if != 0 double pushes are allowed */ static void x87_push(x87_state *state, int reg_idx, ir_node *node) { @@ -313,7 +292,6 @@ static void x87_pop(x87_state *state) assert(state->depth > 0 && "stack underrun"); --state->depth; - state->tos = MASK_TOS(state->tos + 1); DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);) } @@ -326,7 +304,6 @@ static void x87_pop(x87_state *state) static void x87_emms(x87_state *state) { state->depth = 0; - state->tos = 0; } /** @@ -339,32 +316,16 @@ static void x87_emms(x87_state *state) */ static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) { - pmap_entry *entry = pmap_find(sim->blk_states, block); + blk_state *res = pmap_get(blk_state, sim->blk_states, block); - if (! entry) { - blk_state *bl_state = OALLOC(&sim->obst, blk_state); - bl_state->begin = NULL; - bl_state->end = NULL; + if (res == NULL) { + res = OALLOC(&sim->obst, blk_state); + res->begin = NULL; + res->end = NULL; - pmap_insert(sim->blk_states, block, bl_state); - return bl_state; + pmap_insert(sim->blk_states, block, res); } - return PTR_TO_BLKSTATE(entry->value); -} - -/** - * Creates a new x87 state. - * - * @param sim the x87 simulator handle - * - * @return a new x87 state - */ -static x87_state *x87_alloc_state(x87_simulator *sim) -{ - x87_state *res = OALLOC(&sim->obst, x87_state); - - res->sim = sim; return res; } @@ -378,8 +339,7 @@ static x87_state *x87_alloc_state(x87_simulator *sim) */ static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) { - x87_state *res = x87_alloc_state(sim); - + x87_state *const res = OALLOC(&sim->obst, x87_state); *res = *src; return res; } @@ -400,8 +360,6 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) if (mode == mode_T) { /* patch all Proj's */ - const ir_edge_t *edge; - foreach_out_edge(n, edge) { ir_node *proj = get_edge_src_irn(edge); if (is_Proj(proj)) { @@ -426,8 +384,6 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) */ static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) { - const ir_edge_t *edge; - assert(get_irn_mode(n) == mode_T && "Need mode_T node"); foreach_out_edge(n, edge) { @@ -464,36 +420,34 @@ static inline const arch_register_t *get_st_reg(int index) return &ia32_registers[REG_ST0 + index]; } -/* -------------- x87 perm --------------- */ - /** - * Creates a fxch for shuffle. - * - * @param state the x87 state - * @param pos parameter for fxch - * @param block the block were fxch is inserted + * Create a fxch node before another node. * - * Creates a new fxch node and reroute the user of the old node - * to the fxch. + * @param state the x87 state + * @param n the node after the fxch + * @param pos exchange st(pos) with st(0) * - * @return the fxch node + * @return the fxch */ -static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) +static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) { - ir_node *fxch; - ia32_x87_attr_t *attr; + x87_fxch(state, pos); - fxch = new_bd_ia32_fxch(NULL, block); - attr = get_ia32_x87_attr(fxch); + ir_node *const block = get_nodes_block(n); + ir_node *const fxch = new_bd_ia32_fxch(NULL, block); + ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch); attr->x87[0] = get_st_reg(pos); attr->x87[2] = get_st_reg(0); keep_alive(fxch); - x87_fxch(state, pos); + sched_add_before(n, fxch); + DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name)); return fxch; } +/* -------------- x87 perm --------------- */ + /** * Calculate the necessary permutations to reach dst_state. * @@ -503,41 +457,33 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) * Note that critical edges are removed here, so we need only * a shuffle if the current block has only one successor. * - * @param sim the simulator handle * @param block the current block * @param state the current x87 stack state, might be modified - * @param dst_block the destination block * @param dst_state destination state * * @return state */ -static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, - x87_state *state, ir_node *dst_block, - const x87_state *dst_state) +static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state) { int i, n_cycles, k, ri; unsigned cycles[4], all_mask; char cycle_idx[4][8]; - ir_node *fxch, *before, *after; - (void) sim; - (void) dst_block; assert(state->depth == dst_state->depth); /* Some mathematics here: - If we have a cycle of length n that includes the tos, - we need n-1 exchange operations. - We can always add the tos and restore it, so we need - n+1 exchange operations for a cycle not containing the tos. - So, the maximum of needed operations is for a cycle of 7 - not including the tos == 8. - This is the same number of ops we would need for using stores, - so exchange is cheaper (we save the loads). - On the other hand, we might need an additional exchange - in the next block to bring one operand on top, so the - number of ops in the first case is identical. - Further, no more than 4 cycles can exists (4 x 2). - */ + * If we have a cycle of length n that includes the tos, + * we need n-1 exchange operations. + * We can always add the tos and restore it, so we need + * n+1 exchange operations for a cycle not containing the tos. + * So, the maximum of needed operations is for a cycle of 7 + * not including the tos == 8. + * This is the same number of ops we would need for using stores, + * so exchange is cheaper (we save the loads). + * On the other hand, we might need an additional exchange + * in the next block to bring one operand on top, so the + * number of ops in the first case is identical. + * Further, no more than 4 cycles can exists (4 x 2). */ all_mask = (1 << (state->depth)) - 1; for (n_cycles = 0; all_mask; ++n_cycles) { @@ -597,91 +543,46 @@ static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, } #endif - after = NULL; - /* * Find the place node must be insert. * We have only one successor block, so the last instruction should * be a jump. */ - before = sched_last(block); + ir_node *const before = sched_last(block); assert(is_cfop(before)); /* now do the permutations */ for (ri = 0; ri < n_cycles; ++ri) { if ((cycles[ri] & 1) == 0) { /* this cycle does not include the tos */ - fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block); - if (after) - sched_add_after(after, fxch); - else - sched_add_before(before, fxch); - after = fxch; + x87_create_fxch(state, before, cycle_idx[ri][0]); } for (k = 1; cycle_idx[ri][k] != -1; ++k) { - fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block); - if (after) - sched_add_after(after, fxch); - else - sched_add_before(before, fxch); - after = fxch; + x87_create_fxch(state, before, cycle_idx[ri][k]); } if ((cycles[ri] & 1) == 0) { /* this cycle does not include the tos */ - fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block); - sched_add_after(after, fxch); + x87_create_fxch(state, before, cycle_idx[ri][0]); } } return state; } -/** - * Create a fxch node before another node. - * - * @param state the x87 state - * @param n the node after the fxch - * @param pos exchange st(pos) with st(0) - * - * @return the fxch - */ -static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) -{ - ir_node *fxch; - ia32_x87_attr_t *attr; - ir_node *block = get_nodes_block(n); - - x87_fxch(state, pos); - - fxch = new_bd_ia32_fxch(NULL, block); - attr = get_ia32_x87_attr(fxch); - attr->x87[0] = get_st_reg(pos); - attr->x87[2] = get_st_reg(0); - - keep_alive(fxch); - - sched_add_before(n, fxch); - DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name)); - return fxch; -} - /** * Create a fpush before node n. * * @param state the x87 state * @param n the node after the fpush * @param pos push st(pos) on stack - * @param op_idx replace input op_idx of n with the fpush result + * @param val the value to push */ -static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) +static void x87_create_fpush(x87_state *state, ir_node *n, int pos, ir_node *const val) { - ir_node *fpush, *pred = get_irn_n(n, op_idx); - ia32_x87_attr_t *attr; - const arch_register_t *out = x87_get_irn_register(pred); - - x87_push_dbl(state, arch_register_get_index(out), pred); + arch_register_t const *const out = x87_get_irn_register(val); + x87_push_dbl(state, arch_register_get_index(out), val); - fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n)); - attr = get_ia32_x87_attr(fpush); + ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n)); + ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush); attr->x87[0] = get_st_reg(pos); attr->x87[2] = get_st_reg(0); @@ -743,8 +644,6 @@ static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live) const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; if (get_irn_mode(irn) == mode_T) { - const ir_edge_t *edge; - foreach_out_edge(irn, edge) { ir_node *proj = get_edge_src_irn(edge); @@ -774,21 +673,18 @@ static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live) * Put all live virtual registers at the end of a block into a bitset. * * @param sim the simulator handle - * @param lv the liveness information * @param bl the block * * @return The live bitset at the end of this block */ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block) { - int i; vfp_liveness live = 0; const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; const be_lv_t *lv = sim->lv; - be_lv_foreach(lv, block, be_lv_state_end, i) { + be_lv_foreach(lv, block, be_lv_state_end, node) { const arch_register_t *reg; - const ir_node *node = be_lv_get_irn(lv, block, i); if (!arch_irn_consider_in_reg_alloc(cls, node)) continue; @@ -823,14 +719,12 @@ static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsi * Calculate the liveness for a whole block and cache it. * * @param sim the simulator handle - * @param lv the liveness handle * @param block the block */ static void update_liveness(x87_simulator *sim, ir_node *block) { vfp_liveness live = vfp_liveness_end_of_block(sim, block); unsigned idx; - ir_node *irn; /* now iterate through the block backward and cache the results */ sched_foreach_reverse(block, irn) { @@ -934,7 +828,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) if (op1_live_after) { /* Both operands are live: push the first one. This works even for op1 == op2. */ - x87_create_fpush(state, n, op1_idx, n_ia32_binary_right); + x87_create_fpush(state, n, op1_idx, op2); /* now do fxxx (tos=tos X op) */ op1_idx = 0; op2_idx += 1; @@ -1010,7 +904,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) /* second operand is an address mode */ if (op1_live_after) { /* first operand is live: push it here */ - x87_create_fpush(state, n, op1_idx, n_ia32_binary_left); + x87_create_fpush(state, n, op1_idx, op1); op1_idx = 0; } else { /* first operand is dead: bring it to tos */ @@ -1062,36 +956,29 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) */ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { - int op1_idx; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0)); - const arch_register_t *out = x87_get_irn_register(n); - ia32_x87_attr_t *attr; - unsigned live = vfp_live_args_after(sim, n, REGMASK(out)); - + arch_register_t const *const out = x87_get_irn_register(n); + unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name)); DEBUG_ONLY(vfp_dump_live(live);) - op1_idx = x87_on_stack(state, arch_register_get_index(op1)); - - if (is_vfp_live(arch_register_get_index(op1), live)) { + ir_node *const op1 = get_irn_n(n, 0); + arch_register_t const *const op1_reg = x87_get_irn_register(op1); + int const op1_reg_idx = arch_register_get_index(op1_reg); + int const op1_idx = x87_on_stack(state, op1_reg_idx); + if (is_vfp_live(op1_reg_idx, live)) { /* push the operand here */ - x87_create_fpush(state, n, op1_idx, 0); - op1_idx = 0; - } - else { + x87_create_fpush(state, n, op1_idx, op1); + } else { /* operand is dead, bring it to tos */ if (op1_idx != 0) { x87_create_fxch(state, n, op1_idx); - op1_idx = 0; } } x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op)); - attr = get_ia32_x87_attr(n); - attr->x87[0] = op1 = get_st_reg(0); - attr->x87[2] = out = get_st_reg(0); - DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name)); + ia32_x87_attr_t *const attr = get_ia32_x87_attr(n); + attr->x87[2] = attr->x87[0] = get_st_reg(0); + DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), attr->x87[2]->name)); return NO_NODE_ADDED; } @@ -1129,9 +1016,7 @@ static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos) */ static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) { - const ir_edge_t *edge, *ne; - - foreach_out_edge_safe(old_val, edge, ne) { + foreach_out_edge_safe(old_val, edge) { ir_node *user = get_edge_src_irn(edge); if (! user || user == store) @@ -1159,50 +1044,39 @@ static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node * */ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { - ir_node *val = get_irn_n(n, n_ia32_vfst_val); - const arch_register_t *op2 = x87_get_irn_register(val); - unsigned live = vfp_live_args_after(state->sim, n, 0); - int insn = NO_NODE_ADDED; - ia32_x87_attr_t *attr; - int op2_reg_idx, op2_idx, depth; - int live_after_node; - ir_mode *mode; - - op2_reg_idx = arch_register_get_index(op2); - op2_idx = x87_on_stack(state, op2_reg_idx); - live_after_node = is_vfp_live(arch_register_get_index(op2), live); + ir_node *const val = get_irn_n(n, n_ia32_vfst_val); + arch_register_t const *const op2 = x87_get_irn_register(val); DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); - assert(op2_idx >= 0); - - mode = get_ia32_ls_mode(n); - depth = x87_get_depth(state); + int insn = NO_NODE_ADDED; + int const op2_reg_idx = arch_register_get_index(op2); + int const op2_idx = x87_on_stack(state, op2_reg_idx); + unsigned const live = vfp_live_args_after(state->sim, n, 0); + int const live_after_node = is_vfp_live(op2_reg_idx, live); + assert(op2_idx >= 0); if (live_after_node) { - /* - Problem: fst doesn't support 96bit modes (spills), only fstp does - fist doesn't support 64bit mode, only fistp - Solution: - - stack not full: push value and fstp - - stack full: fstp value and load again - Note that we cannot test on mode_E, because floats might be 96bit ... - */ - if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) { - if (depth < N_ia32_st_REGS) { + /* Problem: fst doesn't support 80bit modes (spills), only fstp does + * fist doesn't support 64bit mode, only fistp + * Solution: + * - stack not full: push value and fstp + * - stack full: fstp value and load again + * Note that we cannot test on mode_E, because floats might be 80bit ... */ + ir_mode *const mode = get_ia32_ls_mode(n); + if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) { + if (x87_get_depth(state) < N_ia32_st_REGS) { /* ok, we have a free register: push + fstp */ - x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val); + x87_create_fpush(state, n, op2_idx, val); x87_pop(state); x87_patch_insn(n, op_p); } else { - ir_node *vfld, *mem, *block, *rproj, *mproj; - ir_graph *irg = get_irn_irg(n); - ir_node *nomem = get_irg_no_mem(irg); - /* stack full here: need fstp + load */ x87_pop(state); x87_patch_insn(n, op_p); - block = get_nodes_block(n); - vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n)); + ir_node *const block = get_nodes_block(n); + ir_graph *const irg = get_irn_irg(n); + ir_node *const nomem = get_irg_no_mem(irg); + ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, mode); /* copy all attributes */ set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); @@ -1211,11 +1085,11 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) set_ia32_op_type(vfld, ia32_AddrModeS); add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n)); set_ia32_am_sc(vfld, get_ia32_am_sc(n)); - set_ia32_ls_mode(vfld, get_ia32_ls_mode(n)); + set_ia32_ls_mode(vfld, mode); - rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res); - mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M); - mem = get_irn_Proj_for_mode(n, mode_M); + ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res); + ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M); + ir_node *const mem = get_irn_Proj_for_mode(n, mode_M); assert(mem && "Store memory not found"); @@ -1251,9 +1125,9 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) x87_patch_insn(n, op_p); } - attr = get_ia32_x87_attr(n); - attr->x87[1] = op2 = get_st_reg(0); - DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); + ia32_x87_attr_t *const attr = get_ia32_x87_attr(n); + attr->x87[1] = get_st_reg(0); + DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1]))); return insn; } @@ -1572,7 +1446,7 @@ static int sim_Fucom(x87_state *state, ir_node *n) case 0: dst = op_ia32_FucomFnstsw; break; case 1: dst = op_ia32_FucompFnstsw; break; case 2: dst = op_ia32_FucomppFnstsw; break; - default: panic("invalid popcount in sim_Fucom"); + default: panic("invalid popcount"); } for (i = 0; i < pops; ++i) { @@ -1587,10 +1461,10 @@ static int sim_Fucom(x87_state *state, ir_node *n) x87_pop(state); x87_create_fpop(state, sched_next(n), 1); break; - default: panic("invalid popcount in sim_Fucom"); + default: panic("invalid popcount"); } } else { - panic("invalid operation %+F in sim_FucomFnstsw", n); + panic("invalid operation %+F", n); } x87_patch_insn(n, dst); @@ -1758,33 +1632,23 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) */ static int sim_Copy(x87_state *state, ir_node *n) { - ir_node *pred; - const arch_register_t *out; - const arch_register_t *op1; - const arch_register_class_t *cls; - ir_node *node, *next; - int op1_idx, out_idx; - unsigned live; - - cls = arch_get_irn_reg_class(n); + arch_register_class_t const *const cls = arch_get_irn_reg_class(n); if (cls != &ia32_reg_classes[CLASS_ia32_vfp]) - return 0; + return NO_NODE_ADDED; - pred = get_irn_n(n, 0); - out = x87_get_irn_register(n); - op1 = x87_get_irn_register(pred); - live = vfp_live_args_after(state->sim, n, REGMASK(out)); + ir_node *const pred = be_get_Copy_op(n); + arch_register_t const *const op1 = x87_get_irn_register(pred); + arch_register_t const *const out = x87_get_irn_register(n); + unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, arch_register_get_name(op1), arch_register_get_name(out))); DEBUG_ONLY(vfp_dump_live(live);) - op1_idx = x87_on_stack(state, arch_register_get_index(op1)); - if (is_vfp_live(arch_register_get_index(op1), live)) { /* Operand is still live, a real copy. We need here an fpush that can hold a a register, so use the fpushCopy or recreate constants */ - node = create_Copy(state, n); + ir_node *const node = create_Copy(state, n); /* We have to make sure the old value doesn't go dead (which can happen * when we recreate constants). As the simulator expected that value in @@ -1792,7 +1656,7 @@ static int sim_Copy(x87_state *state, ir_node *n) * instruction, but we would have to rerun all the simulation to get * this correct... */ - next = sched_next(n); + ir_node *const next = sched_next(n); sched_remove(n); exchange(n, node); sched_add_before(next, node); @@ -1803,11 +1667,11 @@ static int sim_Copy(x87_state *state, ir_node *n) DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name)); } else { - out_idx = x87_on_stack(state, arch_register_get_index(out)); - + int const op1_idx = x87_on_stack(state, arch_register_get_index(op1)); + int const out_idx = x87_on_stack(state, arch_register_get_index(out)); if (out_idx >= 0 && out_idx != op1_idx) { /* Matze: out already on stack? how can this happen? */ - panic("invalid stack state in x87 simulator"); + panic("invalid stack state"); #if 0 /* op1 must be killed and placed where out is */ @@ -1838,13 +1702,13 @@ static int sim_Copy(x87_state *state, ir_node *n) #endif } else { /* just a virtual copy */ - x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx); + x87_set_st(state, arch_register_get_index(out), pred, op1_idx); /* don't remove the node to keep the verifier quiet :), the emitter won't emit any code for the node */ #if 0 sched_remove(n); DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n))); - exchange(n, get_unop_op(n)); + exchange(n, pred); #endif } } @@ -1858,8 +1722,6 @@ static int sim_Copy(x87_state *state, ir_node *n) */ static ir_node *get_call_result_proj(ir_node *call) { - const ir_edge_t *edge; - /* search the result proj */ foreach_out_edge(call, edge) { ir_node *proj = get_edge_src_irn(edge); @@ -1869,7 +1731,26 @@ static ir_node *get_call_result_proj(ir_node *call) return proj; } - return NULL; + panic("result Proj missing"); +} + +static int sim_Asm(x87_state *const state, ir_node *const n) +{ + (void)state; + + for (size_t i = get_irn_arity(n); i-- != 0;) { + arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i); + if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp]) + panic("cannot handle %+F with x87 constraints", n); + } + + for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) { + arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i); + if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp]) + panic("cannot handle %+F with x87 constraints", n); + } + + return NO_NODE_ADDED; } /** @@ -1882,38 +1763,24 @@ static ir_node *get_call_result_proj(ir_node *call) */ static int sim_Call(x87_state *state, ir_node *n) { - ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp; - ir_type *res_type; - ir_mode *mode; - ir_node *resproj; - const arch_register_t *reg; - DB((dbg, LEVEL_1, ">>> %+F\n", n)); /* at the begin of a call the x87 state should be empty */ assert(state->depth == 0 && "stack not empty before call"); - if (get_method_n_ress(call_tp) <= 0) - goto end_call; - - /* - * If the called function returns a float, it is returned in st(0). - * This even happens if the return value is NOT used. - * Moreover, only one return result is supported. - */ - res_type = get_method_res_type(call_tp, 0); - mode = get_type_mode(res_type); - - if (mode == NULL || !mode_is_float(mode)) - goto end_call; - - resproj = get_call_result_proj(n); - assert(resproj != NULL); - - reg = x87_get_irn_register(resproj); - x87_push(state, arch_register_get_index(reg), resproj); - -end_call: + ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp; + if (get_method_n_ress(call_tp) != 0) { + /* If the called function returns a float, it is returned in st(0). + * This even happens if the return value is NOT used. + * Moreover, only one return result is supported. */ + ir_type *const res_type = get_method_res_type(call_tp, 0); + ir_mode *const mode = get_type_mode(res_type); + if (mode && mode_is_float(mode)) { + ir_node *const resproj = get_call_result_proj(n); + arch_register_t const *const reg = x87_get_irn_register(resproj); + x87_push(state, arch_register_get_index(reg), resproj); + } + } DB((dbg, LEVEL_1, "Stack after: ")); DEBUG_ONLY(x87_dump_stack(state);) @@ -1930,30 +1797,23 @@ end_call: */ static int sim_Return(x87_state *state, ir_node *n) { - int n_res = be_Return_get_n_rets(n); - int i, n_float_res = 0; - +#ifdef DEBUG_libfirm /* only floating point return values must reside on stack */ - for (i = 0; i < n_res; ++i) { - ir_node *res = get_irn_n(n, n_be_Return_val + i); - + int n_float_res = 0; + int const n_res = be_Return_get_n_rets(n); + for (int i = 0; i < n_res; ++i) { + ir_node *const res = get_irn_n(n, n_be_Return_val + i); if (mode_is_float(get_irn_mode(res))) ++n_float_res; } assert(x87_get_depth(state) == n_float_res); +#endif /* pop them virtually */ - for (i = n_float_res - 1; i >= 0; --i) - x87_pop(state); - + x87_emms(state); return NO_NODE_ADDED; } -typedef struct perm_data_t { - const arch_register_t *in; - const arch_register_t *out; -} perm_data_t; - /** * Simulate a be_Perm. * @@ -1964,10 +1824,9 @@ typedef struct perm_data_t { */ static int sim_Perm(x87_state *state, ir_node *irn) { - int i, n; - ir_node *pred = get_irn_n(irn, 0); - int *stack_pos; - const ir_edge_t *edge; + int i, n; + ir_node *pred = get_irn_n(irn, 0); + int *stack_pos; /* handle only floating point Perms */ if (! mode_is_float(get_irn_mode(pred))) @@ -2008,15 +1867,12 @@ static int sim_Perm(x87_state *state, ir_node *irn) /** * Kill any dead registers at block start by popping them from the stack. * - * @param sim the simulator handle - * @param block the current block - * @param start_state the x87 state at the begin of the block - * - * @return the x87 state after dead register killed + * @param sim the simulator handle + * @param block the current block + * @param state the x87 state at the begin of the block */ -static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) +static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state) { - x87_state *state = start_state; ir_node *first_insn = sched_first(block); ir_node *keep = NULL; unsigned live = vfp_live_args_after(sim, block, 0); @@ -2033,9 +1889,6 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * } if (kill_mask) { - /* create a new state, will be changed */ - state = x87_clone_state(sim, state); - DB((dbg, LEVEL_1, "Killing deads:\n")); DEBUG_ONLY(vfp_dump_live(live);) DEBUG_ONLY(x87_dump_stack(state);) @@ -2053,7 +1906,7 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * sched_add_before(first_insn, keep); keep_alive(keep); x87_emms(state); - return state; + return; } } /* now kill registers */ @@ -2089,7 +1942,6 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * } keep_alive(keep); } - return state; } /** @@ -2103,7 +1955,6 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) ir_node *n, *next; blk_state *bl_state = x87_get_bl_state(sim, block); x87_state *state = bl_state->begin; - const ir_edge_t *edge; ir_node *start_block; assert(state != NULL); @@ -2115,10 +1966,10 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) DB((dbg, LEVEL_2, "State at Block begin:\n ")); DEBUG_ONLY(x87_dump_stack(state);) - /* at block begin, kill all dead registers */ - state = x87_kill_deads(sim, block, state); /* create a new state, will be changed */ state = x87_clone_state(sim, state); + /* at block begin, kill all dead registers */ + x87_kill_deads(sim, block, state); /* beware, n might change */ for (n = sched_first(block); !sched_is_end(n); n = next) { @@ -2176,7 +2027,7 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) If the successor has more than one possible input, then it must be the only one. */ - x87_shuffle(sim, block, state, succ, succ_state->begin); + x87_shuffle(block, state, succ_state->begin); } } bl_state->end = state; @@ -2211,8 +2062,9 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg) "x87 Simulator started for %+F\n", irg)); /* set the generic function pointer of instruction we must simulate */ - clear_irp_opcodes_generic_func(); + ir_clear_opcodes_generic_func(); + register_sim(op_ia32_Asm, sim_Asm); register_sim(op_ia32_Call, sim_Call); register_sim(op_ia32_vfld, sim_fld); register_sim(op_ia32_vfild, sim_fild); @@ -2279,15 +2131,14 @@ void ia32_x87_simulate_graph(ir_graph *irg) bl_state = x87_get_bl_state(&sim, start_block); /* start with the empty state */ - bl_state->begin = empty; - empty->sim = ∼ + empty.sim = ∼ + bl_state->begin = ∅ sim.worklist = new_waitq(); waitq_put(sim.worklist, start_block); - be_assure_liveness(irg); + be_assure_live_sets(irg); sim.lv = be_get_irg_liveness(irg); - be_liveness_assure_sets(sim.lv); /* Calculate the liveness for all nodes. We must precalculate this info, * because the simulator adds new nodes (possible before Phi nodes) which