X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=3ad3e9d3af2b5b81312ddcc052e09c9c263169df;hb=0fbcef83aa6060534172bb13e71cdadb04428806;hp=14678feb70560c57a41ec6f1f2ddd0c5ff5e5b1f;hpb=950a98725cc6e262a0297755665d4de1bb02c4a7;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 14678feb7..3ad3e9d3a 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -24,11 +24,10 @@ * @author Christian Wuerdig, Matthias Braun * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include +#include #include "irargs_t.h" #include "irnode_t.h" @@ -47,6 +46,7 @@ #include "irdom.h" #include "archop.h" #include "error.h" +#include "array_t.h" #include "height.h" #include "../benode_t.h" @@ -58,6 +58,7 @@ #include "../be_t.h" #include "bearch_ia32_t.h" +#include "ia32_common_transform.h" #include "ia32_nodes_attr.h" #include "ia32_transform.h" #include "ia32_new_nodes.h" @@ -93,10 +94,7 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -/** hold the current code generator during transformation */ -static ia32_code_gen_t *env_cg = NULL; static ir_node *initial_fpcw = NULL; -static heights_t *heights = NULL; extern ir_op *get_op_Mulh(void); @@ -125,9 +123,6 @@ typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg, typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op); -static ir_node *try_create_Immediate(ir_node *node, - char immediate_constraint_type); - static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type); @@ -135,173 +130,50 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, dbg_info *dbgi, ir_node *block, ir_node *op, ir_node *orig_node); -/** - * Return true if a mode can be stored in the GP register set - */ -static INLINE int mode_needs_gp_reg(ir_mode *mode) { - if(mode == mode_fpcw) - return 0; - if(get_mode_size_bits(mode) > 32) - return 0; - return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b; -} - -/** - * creates a unique ident by adding a number to a tag - * - * @param tag the tag string, must contain a %d if a number - * should be added - */ -static ident *unique_id(const char *tag) -{ - static unsigned id = 0; - char str[256]; - - snprintf(str, sizeof(str), tag, ++id); - return new_id_from_str(str); -} - -/** - * Get a primitive type for a mode. - */ -static ir_type *get_prim_type(pmap *types, ir_mode *mode) -{ - pmap_entry *e = pmap_find(types, mode); - ir_type *res; - - if (! e) { - char buf[64]; - snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode)); - res = new_type_primitive(new_id_from_str(buf), mode); - set_type_alignment_bytes(res, 16); - pmap_insert(types, mode, res); - } - else - res = e->value; - return res; -} - -/** - * Creates an immediate. - * - * @param symconst if set, create a SymConst immediate - * @param symconst_sign sign for the symconst - * @param val integer value for the immediate - */ -static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) -{ - ir_graph *irg = current_ir_graph; - ir_node *start_block = get_irg_start_block(irg); - ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, - symconst, symconst_sign, val); - arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - - return immediate; -} - -/** - * Get an atomic entity that is initialized with a tarval forming - * a given constant. - * - * @param cnst the node representing the constant - */ -static ir_entity *create_float_const_entity(ir_node *cnst) +/** Return non-zero is a node represents the 0 constant. */ +static bool is_Const_0(ir_node *node) { - ia32_isa_t *isa = env_cg->isa; - tarval *key = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, key); - ir_entity *res; - ir_graph *rem; - - if (e == NULL) { - tarval *tv = key; - ir_mode *mode = get_tarval_mode(tv); - ir_type *tp; - - if (! ia32_cg_config.use_sse2) { - /* try to reduce the mode to produce smaller sized entities */ - if (mode != mode_F) { - if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { - mode = mode_F; - tv = tarval_convert_to(tv, mode); - } else if (mode != mode_D) { - if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { - mode = mode_D; - tv = tarval_convert_to(tv, mode); - } - } - } - } - - if (mode == get_irn_mode(cnst)) { - /* mode was not changed */ - tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = get_prim_type(isa->types, mode); - } else - tp = get_prim_type(isa->types, mode); - - res = new_entity(get_glob_type(), unique_id(".LC%u"), tp); - - set_entity_ld_ident(res, get_entity_ident(res)); - set_entity_visibility(res, visibility_local); - set_entity_variability(res, variability_constant); - set_entity_allocation(res, allocation_static); - - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - set_atomic_ent_value(res, new_Const_type(tv, tp)); - current_ir_graph = rem; - - pmap_insert(isa->tv_ent, key, res); - } else { - res = e->value; - } - - return res; -} - -static int is_Const_0(ir_node *node) { return is_Const(node) && is_Const_null(node); } -static int is_Const_1(ir_node *node) { +/** Return non-zero is a node represents the 1 constant. */ +static bool is_Const_1(ir_node *node) +{ return is_Const(node) && is_Const_one(node); } -static int is_Const_Minus_1(ir_node *node) { +/** Return non-zero is a node represents the -1 constant. */ +static bool is_Const_Minus_1(ir_node *node) +{ return is_Const(node) && is_Const_all_one(node); } /** * returns true if constant can be created with a simple float command */ -static int is_simple_x87_Const(ir_node *node) +static bool is_simple_x87_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); - if (tarval_is_null(tv) || tarval_is_one(tv)) - return 1; + return true; /* TODO: match all the other float constants */ - return 0; + return false; } /** * returns true if constant can be created with a simple float command */ -static int is_simple_sse_Const(ir_node *node) +static bool is_simple_sse_Const(ir_node *node) { - tarval *tv = get_Const_tarval(node); + tarval *tv = get_Const_tarval(node); ir_mode *mode = get_tarval_mode(tv); if (mode == mode_F) - return 1; + return true; if (tarval_is_null(tv) || tarval_is_one(tv)) - return 1; + return true; if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | @@ -309,18 +181,19 @@ static int is_simple_sse_Const(ir_node *node) (get_tarval_sub_bits(tv, 2) << 16) | (get_tarval_sub_bits(tv, 3) << 24); if (val == 0) - /* really a 32bit constant */ - return 1; + /* lower 32bit are zero, really a 32bit constant */ + return true; } /* TODO: match all the other float constants */ - return 0; + return false; } /** * Transforms a Const. */ -static ir_node *gen_Const(ir_node *node) { +static ir_node *gen_Const(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *old_block = get_nodes_block(node); ir_node *block = be_transform_node(old_block); @@ -420,18 +293,11 @@ static ir_node *gen_Const(ir_node *node) { } } end: - /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet. - * So add a dependency to the initial frame pointer calculation to - * avoid that situation. - */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(load, get_irg_frame(irg)); - } - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + + be_dep_on_frame(load); return res; - } else { + } else { /* non-float mode */ ir_node *cnst; tarval *tv = get_Const_tarval(node); long val; @@ -447,11 +313,7 @@ end: cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node)); - /* see above */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(cnst, get_irg_frame(irg)); - } - + be_dep_on_frame(cnst); return cnst; } } @@ -459,7 +321,8 @@ end: /** * Transforms a SymConst. */ -static ir_node *gen_SymConst(ir_node *node) { +static ir_node *gen_SymConst(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *old_block = get_nodes_block(node); ir_node *block = be_transform_node(old_block); @@ -480,27 +343,22 @@ static ir_node *gen_SymConst(ir_node *node) { } else { ir_entity *entity; - if(get_SymConst_kind(node) != symconst_addr_ent) { + if (get_SymConst_kind(node) != symconst_addr_ent) { panic("backend only support symconst_addr_ent (at %+F)", node); } entity = get_SymConst_entity(node); cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0); } - /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet - */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(cnst, get_irg_frame(irg)); - } - SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node)); + be_dep_on_frame(cnst); return cnst; } /* Generates an entity for a known FP const (used for FP Neg + Abs) */ -ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { +ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) +{ static const struct { const char *tp_name; const char *ent_name; @@ -562,19 +420,6 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { return ent_cache[kct]; } -#ifndef NDEBUG -/** - * Prints the old node name on cg obst and returns a pointer to it. - */ -const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { - ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa; - - lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn); - obstack_1grow(isa->name_obst, 0); - return obstack_finish(isa->name_obst); -} -#endif /* NDEBUG */ - /** * return true if the node is a Proj(Load) and could be used in source address * mode for another node. Will return only true if the @p other node is not @@ -582,49 +427,50 @@ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { * input here, for unary operations use NULL). */ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, - ir_node *other, ir_node *other2) + ir_node *other, ir_node *other2, match_flags_t flags) { - ir_mode *mode = get_irn_mode(node); ir_node *load; long pn; /* float constants are always available */ - if (is_Const(node) && mode_is_float(mode)) { - if (ia32_cg_config.use_sse2) { - if (is_simple_sse_Const(node)) - return 0; - } else { - if (is_simple_x87_Const(node)) + if (is_Const(node)) { + ir_mode *mode = get_irn_mode(node); + if (mode_is_float(mode)) { + if (ia32_cg_config.use_sse2) { + if (is_simple_sse_Const(node)) + return 0; + } else { + if (is_simple_x87_Const(node)) + return 0; + } + if (get_irn_n_edges(node) > 1) return 0; + return 1; } - if (get_irn_n_edges(node) > 1) - return 0; - return 1; } - if(!is_Proj(node)) + if (!is_Proj(node)) return 0; load = get_Proj_pred(node); pn = get_Proj_proj(node); - if(!is_Load(load) || pn != pn_Load_res) + if (!is_Load(load) || pn != pn_Load_res) return 0; - if(get_nodes_block(load) != block) + if (get_nodes_block(load) != block) return 0; /* we only use address mode if we're the only user of the load */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1)) return 0; /* in some edge cases with address mode we might reach the load normally * and through some AM sequence, if it is already materialized then we * can't create an AM node from it */ - if(be_is_transformed(node)) + if (be_is_transformed(node)) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if(other != NULL && get_nodes_block(other) == block - && heights_reachable_in_block(heights, other, load)) + if (other != NULL && prevents_AM(block, load, other)) return 0; - if(other2 != NULL && get_nodes_block(other2) == block - && heights_reachable_in_block(heights, other2, load)) + + if (other2 != NULL && prevents_AM(block, load, other2)) return 0; return 1; @@ -635,6 +481,7 @@ struct ia32_address_mode_t { ia32_address_t addr; ir_mode *ls_mode; ir_node *mem_proj; + ir_node *am_node; ia32_op_type_t op_type; ir_node *new_op1; ir_node *new_op2; @@ -645,12 +492,13 @@ struct ia32_address_mode_t { static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *noreg_gp; /* construct load address */ memset(addr, 0, sizeof(addr[0])); ia32_create_address_mode(addr, ptr, /*force=*/0); + noreg_gp = ia32_new_NoReg_gp(env_cg); addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; addr->mem = be_transform_node(mem); @@ -684,6 +532,7 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) am->pinned = get_irn_pinned(load); am->ls_mode = get_Load_mode(load); am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M); + am->am_node = node; /* construct load address */ ia32_create_address_mode(addr, ptr, /*force=*/0); @@ -698,23 +547,28 @@ static void set_address(ir_node *node, const ia32_address_t *addr) set_ia32_am_scale(node, addr->scale); set_ia32_am_sc(node, addr->symconst_ent); set_ia32_am_offs_int(node, addr->offset); - if(addr->symconst_sign) + if (addr->symconst_sign) set_ia32_am_sc_sign(node); - if(addr->use_frame) + if (addr->use_frame) set_ia32_use_frame(node); set_ia32_frame_ent(node, addr->frame_entity); } +/** + * Apply attributes of a given address mode to a node. + */ static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am) { set_address(node, &am->addr); set_ia32_op_type(node, am->op_type); set_ia32_ls_mode(node, am->ls_mode); - if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) { - set_irn_pinned(node, am->pinned); + if (am->pinned == op_pin_state_pinned) { + /* beware: some nodes are already pinned and did not allow to change the state */ + if (get_irn_pinned(node) != op_pin_state_pinned) + set_irn_pinned(node, op_pin_state_pinned); } - if(am->commutative) + if (am->commutative) set_ia32_commutative(node); } @@ -731,31 +585,31 @@ static int is_downconv(const ir_node *node) ir_mode *src_mode; ir_mode *dest_mode; - if(!is_Conv(node)) + if (!is_Conv(node)) return 0; /* we only want to skip the conv when we're the only user * (not optimal but for now...) */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) > 1) return 0; src_mode = get_irn_mode(get_Conv_op(node)); dest_mode = get_irn_mode(node); - return mode_needs_gp_reg(src_mode) - && mode_needs_gp_reg(dest_mode) + return ia32_mode_needs_gp_reg(src_mode) + && ia32_mode_needs_gp_reg(dest_mode) && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode); } /* Skip all Down-Conv's on a given node and return the resulting node. */ -ir_node *ia32_skip_downconv(ir_node *node) { +ir_node *ia32_skip_downconv(ir_node *node) +{ while (is_downconv(node)) node = get_Conv_op(node); return node; } -#if 0 static ir_node *create_upconv(ir_node *node, ir_node *orig_node) { ir_mode *mode = get_irn_mode(node); @@ -763,7 +617,7 @@ static ir_node *create_upconv(ir_node *node, ir_node *orig_node) ir_mode *tgt_mode; dbg_info *dbgi; - if(mode_is_signed(mode)) { + if (mode_is_signed(mode)) { tgt_mode = mode_Is; } else { tgt_mode = mode_Iu; @@ -773,7 +627,6 @@ static ir_node *create_upconv(ir_node *node, ir_node *orig_node) return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node); } -#endif /** * matches operands of a node into ia32 addressing/operand modes. This covers @@ -790,16 +643,14 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, ir_node *op1, ir_node *op2, ir_node *other_op, match_flags_t flags) { - ia32_address_t *addr = &am->addr; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *new_op1; - ir_node *new_op2; - ir_mode *mode = get_irn_mode(op2); + ia32_address_t *addr = &am->addr; + ir_mode *mode = get_irn_mode(op2); + int mode_bits = get_mode_size_bits(mode); + ir_node *noreg_gp, *new_op1, *new_op2; int use_am; unsigned commutative; int use_am_and_immediates; int use_immediate; - int mode_bits = get_mode_size_bits(mode); memset(am, 0, sizeof(am[0])); @@ -842,11 +693,12 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, new_op2 = try_create_Immediate(op2, 0); } + noreg_gp = ia32_new_NoReg_gp(env_cg); if (new_op2 == NULL && - use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) { + use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { build_address(am, op2); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(mode_is_float(mode)) { + if (mode_is_float(mode)) { new_op2 = ia32_new_NoReg_vfp(env_cg); } else { new_op2 = noreg_gp; @@ -854,7 +706,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, am->op_type = ia32_AddrModeS; } else if (commutative && (new_op2 == NULL || use_am_and_immediates) && use_am && - ia32_use_source_address_mode(block, op1, op2, other_op)) { + ia32_use_source_address_mode(block, op1, op2, other_op, flags)) { ir_node *noreg; build_address(am, op1); @@ -864,7 +716,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, noreg = noreg_gp; } - if(new_op2 != NULL) { + if (new_op2 != NULL) { new_op1 = noreg; } else { new_op1 = be_transform_node(op2); @@ -873,26 +725,25 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { - if(flags & match_try_am) { + am->op_type = ia32_Normal; + + if (flags & match_try_am) { am->new_op1 = NULL; am->new_op2 = NULL; - am->op_type = ia32_Normal; return; } new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(new_op2 == NULL) + if (new_op2 == NULL) new_op2 = be_transform_node(op2); - am->op_type = ia32_Normal; - am->ls_mode = get_irn_mode(op2); - if(flags & match_mode_neutral) - am->ls_mode = mode_Iu; + am->ls_mode = + (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2)); } - if(addr->base == NULL) + if (addr->base == NULL) addr->base = noreg_gp; - if(addr->index == NULL) + if (addr->index == NULL) addr->index = noreg_gp; - if(addr->mem == NULL) + if (addr->mem == NULL) addr->mem = new_NoMem(); am->new_op1 = new_op1; @@ -902,23 +753,21 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) { - ir_graph *irg = current_ir_graph; ir_mode *mode; ir_node *load; - if(am->mem_proj == NULL) + if (am->mem_proj == NULL) return node; /* we have to create a mode_T so the old MemProj can attach to us */ mode = get_irn_mode(node); load = get_Proj_pred(am->mem_proj); - mark_irn_visited(load); be_set_transformed_node(load, node); - if(mode != mode_T) { + if (mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res); + return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -927,6 +776,7 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) /** * Construct a standard binary operation, set AM and immediate if required. * + * @param node The original node for which the binop is created * @param op1 The first operand * @param op2 The second operand * @param func The node constructor function @@ -935,22 +785,24 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_func *func, match_flags_t flags) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); + if (!(flags & match_am_and_immediates) && + (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))) + set_ia32_am_support(new_node, ia32_am_none); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); new_node = fix_mem_proj(new_node, &am); @@ -982,25 +834,26 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, match_flags_t flags) { ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left); ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right); ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags); - ir_node *new_eflags = be_transform_node(eflags); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_node, *new_eflags; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, op1, op2, NULL, flags); + match_arguments(&am, src_block, op1, op2, eflags, flags); - new_node = func(dbgi, irg, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, new_eflags); + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); + new_eflags = be_transform_node(eflags); + new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_eflags); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); + if (!(flags & match_am_and_immediates) && + (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))) + set_ia32_am_support(new_node, ia32_am_none); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); new_node = fix_mem_proj(new_node, &am); @@ -1011,7 +864,7 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, static ir_node *get_fpcw(void) { ir_node *fpcw; - if(initial_fpcw != NULL) + if (initial_fpcw != NULL) return initial_fpcw; fpcw = be_abi_get_ignore_irn(env_cg->birg->abi, @@ -1030,28 +883,35 @@ static ir_node *get_fpcw(void) * @return The constructed ia32 node. */ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_float_func *func, - match_flags_t flags) + construct_binop_float_func *func) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_mode *mode = get_irn_mode(node); - ir_node *new_node; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + ia32_x87_attr_t *attr; + /* All operations are considered commutative, because there are reverse + * variants */ + match_flags_t flags = match_commutative; - /* cannot use addresmode with long double on x87 */ - if (get_mode_size_bits(mode) > 64) - flags &= ~match_am; + /* cannot use address mode with long double on x87 */ + if (get_mode_size_bits(mode) <= 64) + flags |= match_am; + block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, get_fpcw()); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, get_fpcw()); set_am_attributes(new_node, &am); + attr = get_ia32_x87_attr(new_node); + attr->attr.data.ins_permuted = am.ins_permuted; + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); new_node = fix_mem_proj(new_node, &am); @@ -1071,34 +931,37 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_shift_func *func, match_flags_t flags) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_op1; - ir_node *new_op2; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op1, *new_op2, *new_node; assert(! mode_is_float(get_irn_mode(node))); assert(flags & match_immediate); assert((flags & ~(match_mode_neutral | match_immediate)) == 0); - if(flags & match_mode_neutral) { - op1 = ia32_skip_downconv(op1); + if (flags & match_mode_neutral) { + op1 = ia32_skip_downconv(op1); + new_op1 = be_transform_node(op1); } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { - panic("right shifting of non-32bit values not supported, yet"); + new_op1 = create_upconv(op1, node); + } else { + new_op1 = be_transform_node(op1); } - new_op1 = be_transform_node(op1); /* the shift amount can be any mode that is bigger than 5 bits, since all * other bits are ignored anyway */ while (is_Conv(op2) && get_irn_n_edges(op2) == 1) { - op2 = get_Conv_op(op2); + ir_node *const op = get_Conv_op(op2); + if (mode_is_float(get_irn_mode(op))) + break; + op2 = op; assert(get_mode_size_bits(get_irn_mode(op2)) >= 5); } new_op2 = create_immediate_or_transform(op2, 0); - new_node = func(dbgi, irg, new_block, new_op1, new_op2); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); /* lowered shift instruction may have a dependency operand, handle it here */ @@ -1122,20 +985,19 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, match_flags_t flags) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_op; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op, *new_node; assert(flags == 0 || flags == match_mode_neutral); - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op = ia32_skip_downconv(op); } - new_op = be_transform_node(op); - new_node = func(dbgi, irg, new_block, new_op); + new_op = be_transform_node(op); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -1145,29 +1007,32 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_graph *irg = current_ir_graph; - ir_node *base = addr->base; - ir_node *index = addr->index; - ir_node *res; + ir_node *base, *index, *res; - if(base == NULL) { + base = addr->base; + if (base == NULL) { base = ia32_new_NoReg_gp(env_cg); } else { base = be_transform_node(base); } - if(index == NULL) { + index = addr->index; + if (index == NULL) { index = ia32_new_NoReg_gp(env_cg); } else { index = be_transform_node(index); } - res = new_rd_ia32_Lea(dbgi, irg, block, base, index); + res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index); set_address(res, addr); return res; } +/** + * Returns non-zero if a given address mode has a symbolic or + * numerical offset != 0. + */ static int am_has_immediates(const ia32_address_t *addr) { return addr->offset != 0 || addr->symconst_ent != NULL @@ -1179,16 +1044,13 @@ static int am_has_immediates(const ia32_address_t *addr) * * @return the created ia32 Add node */ -static ir_node *gen_Add(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *op1 = get_Add_left(node); - ir_node *op2 = get_Add_right(node); - ir_mode *mode = get_irn_mode(node); - ir_node *new_node; - ir_node *add_immediate_op; +static ir_node *gen_Add(ir_node *node) +{ + ir_mode *mode = get_irn_mode(node); + ir_node *op1 = get_Add_left(node); + ir_node *op2 = get_Add_right(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node, *add_immediate_op; ia32_address_t addr; ia32_address_mode_t am; @@ -1197,8 +1059,7 @@ static ir_node *gen_Add(ir_node *node) { return gen_binop(node, op1, op2, new_rd_ia32_xAdd, match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, - match_commutative | match_am); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd); } ia32_mark_non_am(node); @@ -1216,23 +1077,29 @@ static ir_node *gen_Add(ir_node *node) { memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, node, /*force=*/1); add_immediate_op = NULL; + + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + /* a constant? */ - if(addr.base == NULL && addr.index == NULL) { + if (addr.base == NULL && addr.index == NULL) { + ir_graph *irg = current_ir_graph; new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent, addr.symconst_sign, addr.offset); - add_irn_dep(new_node, get_irg_frame(irg)); + be_dep_on_frame(new_node); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); return new_node; } /* add with immediate? */ - if(addr.index == NULL) { + if (addr.index == NULL) { add_immediate_op = addr.base; - } else if(addr.base == NULL && addr.scale == 0) { + } else if (addr.base == NULL && addr.scale == 0) { add_immediate_op = addr.index; } - if(add_immediate_op != NULL) { - if(!am_has_immediates(&addr)) { + if (add_immediate_op != NULL) { + if (!am_has_immediates(&addr)) { #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n", node); @@ -1251,6 +1118,7 @@ static ir_node *gen_Add(ir_node *node) { /* construct an Add with source address mode */ if (am.op_type == ia32_AddrModeS) { + ir_graph *irg = current_ir_graph; ia32_address_t *am_addr = &am.addr; new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base, am_addr->index, am_addr->mem, am.new_op1, @@ -1274,7 +1142,8 @@ static ir_node *gen_Add(ir_node *node) { * * @return the created ia32 Mul node */ -static ir_node *gen_Mul(ir_node *node) { +static ir_node *gen_Mul(ir_node *node) +{ ir_node *op1 = get_Mul_left(node); ir_node *op2 = get_Mul_right(node); ir_mode *mode = get_irn_mode(node); @@ -1284,8 +1153,7 @@ static ir_node *gen_Mul(ir_node *node) { return gen_binop(node, op1, op2, new_rd_ia32_xMul, match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, - match_commutative | match_am); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul); } return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative | match_am | match_mode_neutral | @@ -1301,58 +1169,34 @@ static ir_node *gen_Mul(ir_node *node) { */ static ir_node *gen_Mulh(ir_node *node) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *op1 = get_Mulh_left(node); - ir_node *op2 = get_Mulh_right(node); - ir_node *proj_res_high; - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - assert(!mode_is_float(mode) && "Mulh with float not supported"); - assert(get_mode_size_bits(mode) == 32); - - match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *op1 = get_Mulh_left(node); + ir_node *op2 = get_Mulh_right(node); + ir_mode *mode = get_irn_mode(node); + ir_node *new_node; + ir_node *proj_res_high; if (mode_is_signed(mode)) { - new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2); + new_node = gen_binop(node, op1, op2, new_rd_ia32_IMul1OP, match_commutative | match_am); + proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, + mode_Iu, pn_ia32_IMul1OP_res_high); } else { - new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2); + new_node = gen_binop(node, op1, op2, new_rd_ia32_Mul, match_commutative | match_am); + proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, + mode_Iu, pn_ia32_Mul_res_high); } - - set_am_attributes(new_node, &am); - /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - assert(get_irn_mode(new_node) == mode_T); - - fix_mem_proj(new_node, &am); - - assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high); - proj_res_high = new_rd_Proj(dbgi, irg, block, new_node, - mode_Iu, pn_ia32_IMul1OP_res_high); - return proj_res_high; } - - /** * Creates an ia32 And. * * @return The created ia32 And node */ -static ir_node *gen_And(ir_node *node) { +static ir_node *gen_And(ir_node *node) +{ ir_node *op1 = get_And_left(node); ir_node *op2 = get_And_right(node); assert(! mode_is_float(get_irn_mode(node))); @@ -1368,7 +1212,7 @@ static ir_node *gen_And(ir_node *node) { ir_mode *src_mode; ir_node *res; - if(v == 0xFF) { + if (v == 0xFF) { src_mode = mode_Bu; } else { assert(v == 0xFFFF); @@ -1379,7 +1223,6 @@ static ir_node *gen_And(ir_node *node) { return res; } } - return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative | match_mode_neutral | match_am | match_immediate); @@ -1392,7 +1235,8 @@ static ir_node *gen_And(ir_node *node) { * * @return The created ia32 Or node */ -static ir_node *gen_Or(ir_node *node) { +static ir_node *gen_Or(ir_node *node) +{ ir_node *op1 = get_Or_left(node); ir_node *op2 = get_Or_right(node); @@ -1408,7 +1252,8 @@ static ir_node *gen_Or(ir_node *node) { * * @return The created ia32 Eor node */ -static ir_node *gen_Eor(ir_node *node) { +static ir_node *gen_Eor(ir_node *node) +{ ir_node *op1 = get_Eor_left(node); ir_node *op2 = get_Eor_right(node); @@ -1423,7 +1268,8 @@ static ir_node *gen_Eor(ir_node *node) { * * @return The created ia32 Sub node */ -static ir_node *gen_Sub(ir_node *node) { +static ir_node *gen_Sub(ir_node *node) +{ ir_node *op1 = get_Sub_left(node); ir_node *op2 = get_Sub_right(node); ir_mode *mode = get_irn_mode(node); @@ -1432,11 +1278,10 @@ static ir_node *gen_Sub(ir_node *node) { if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, - match_am); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub); } - if(is_Const(op2)) { + if (is_Const(op2)) { ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n", node); } @@ -1445,6 +1290,49 @@ static ir_node *gen_Sub(ir_node *node) { | match_am | match_immediate); } +static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, + ir_node *const src_val, + ir_node *const src_mem, + ir_node *const am_mem) +{ + if (is_NoMem(am_mem)) { + return be_transform_node(src_mem); + } else if (is_Proj(src_val) && + is_Proj(src_mem) && + get_Proj_pred(src_val) == get_Proj_pred(src_mem)) { + /* avoid memory loop */ + return am_mem; + } else if (is_Proj(src_val) && is_Sync(src_mem)) { + ir_node *const ptr_pred = get_Proj_pred(src_val); + int const arity = get_Sync_n_preds(src_mem); + int n = 0; + ir_node ** ins; + int i; + + NEW_ARR_A(ir_node*, ins, arity + 1); + + for (i = arity - 1; i >= 0; --i) { + ir_node *const pred = get_Sync_pred(src_mem, i); + + /* avoid memory loop */ + if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred) + continue; + + ins[n++] = be_transform_node(pred); + } + + ins[n++] = am_mem; + + return new_r_Sync(irg, block, n, ins); + } else { + ir_node *ins[2]; + + ins[0] = be_transform_node(src_mem); + ins[1] = am_mem; + return new_r_Sync(irg, block, 2, ins); + } +} + /** * Generates an ia32 DivMod with additional infrastructure for the * register allocator if needed. @@ -1494,21 +1382,11 @@ static ir_node *create_Div(ir_node *node) /* Beware: We don't need a Sync, if the memory predecessor of the Div node is the memory of the consumed address. We can have only the second op as address in Div nodes, so check only op2. */ - if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) { - new_mem = be_transform_node(mem); - if(!is_NoMem(addr->mem)) { - ir_node *in[2]; - in[0] = new_mem; - in[1] = addr->mem; - new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in); - } - } else { - new_mem = addr->mem; - } + new_mem = transform_AM_mem(irg, block, op2, mem, addr->mem); if (mode_is_signed(mode)) { ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); - add_irn_dep(produceval, get_irg_frame(irg)); + be_dep_on_frame(produceval); sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1, produceval); @@ -1517,7 +1395,7 @@ static ir_node *create_Div(ir_node *node) am.new_op1, sign_extension); } else { sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); - add_irn_dep(sign_extension, get_irg_frame(irg)); + be_dep_on_frame(sign_extension); new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, addr->index, new_mem, am.new_op2, @@ -1535,15 +1413,18 @@ static ir_node *create_Div(ir_node *node) } -static ir_node *gen_Mod(ir_node *node) { +static ir_node *gen_Mod(ir_node *node) +{ return create_Div(node); } -static ir_node *gen_Div(ir_node *node) { +static ir_node *gen_Div(ir_node *node) +{ return create_Div(node); } -static ir_node *gen_DivMod(ir_node *node) { +static ir_node *gen_DivMod(ir_node *node) +{ return create_Div(node); } @@ -1556,13 +1437,13 @@ static ir_node *gen_DivMod(ir_node *node) { */ static ir_node *gen_Quot(ir_node *node) { - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); + ir_node *op1 = get_Quot_left(node); + ir_node *op2 = get_Quot_right(node); if (ia32_cg_config.use_sse2) { return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); } else { - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv); } } @@ -1572,7 +1453,8 @@ static ir_node *gen_Quot(ir_node *node) * * @return The created ia32 Shl node */ -static ir_node *gen_Shl(ir_node *node) { +static ir_node *gen_Shl(ir_node *node) +{ ir_node *left = get_Shl_left(node); ir_node *right = get_Shl_right(node); @@ -1585,7 +1467,8 @@ static ir_node *gen_Shl(ir_node *node) { * * @return The created ia32 Shr node */ -static ir_node *gen_Shr(ir_node *node) { +static ir_node *gen_Shr(ir_node *node) +{ ir_node *left = get_Shr_left(node); ir_node *right = get_Shr_right(node); @@ -1599,15 +1482,16 @@ static ir_node *gen_Shr(ir_node *node) { * * @return The created ia32 Shrs node */ -static ir_node *gen_Shrs(ir_node *node) { +static ir_node *gen_Shrs(ir_node *node) +{ ir_node *left = get_Shrs_left(node); ir_node *right = get_Shrs_right(node); ir_mode *mode = get_irn_mode(node); - if(is_Const(right) && mode == mode_Is) { + if (is_Const(right) && mode == mode_Is) { tarval *tv = get_Const_tarval(right); long val = get_tarval_long(tv); - if(val == 31) { + if (val == 31) { /* this is a sign extension */ ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -1615,28 +1499,28 @@ static ir_node *gen_Shrs(ir_node *node) { ir_node *op = left; ir_node *new_op = be_transform_node(op); ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block); - add_irn_dep(pval, get_irg_frame(irg)); + be_dep_on_frame(pval); return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval); } } /* 8 or 16 bit sign extension? */ - if(is_Const(right) && is_Shl(left) && mode == mode_Is) { + if (is_Const(right) && is_Shl(left) && mode == mode_Is) { ir_node *shl_left = get_Shl_left(left); ir_node *shl_right = get_Shl_right(left); - if(is_Const(shl_right)) { + if (is_Const(shl_right)) { tarval *tv1 = get_Const_tarval(right); tarval *tv2 = get_Const_tarval(shl_right); - if(tv1 == tv2 && tarval_is_long(tv1)) { + if (tv1 == tv2 && tarval_is_long(tv1)) { long val = get_tarval_long(tv1); - if(val == 16 || val == 24) { + if (val == 16 || val == 24) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_mode *src_mode; ir_node *res; - if(val == 24) { + if (val == 24) { src_mode = mode_Bs; } else { assert(val == 16); @@ -1657,20 +1541,21 @@ static ir_node *gen_Shrs(ir_node *node) { /** - * Creates an ia32 RotL. + * Creates an ia32 Rol. * * @param op1 The first operator * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { +static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) +{ return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate); } /** - * Creates an ia32 RotR. + * Creates an ia32 Ror. * NOTE: There is no RotR with immediate because this would always be a RotL * "imm-mode_size_bits" which can be pre-calculated. * @@ -1678,7 +1563,8 @@ static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { +static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) +{ return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate); } @@ -1689,16 +1575,17 @@ static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { * * @return The created ia32 RotL or RotR node */ -static ir_node *gen_Rot(ir_node *node) { +static ir_node *gen_Rotl(ir_node *node) +{ ir_node *rotate = NULL; - ir_node *op1 = get_Rot_left(node); - ir_node *op2 = get_Rot_right(node); + ir_node *op1 = get_Rotl_left(node); + ir_node *op2 = get_Rotl_right(node); - /* Firm has only Rot (which is a RotL), so we are looking for a right (op2) + /* Firm has only RotL, so we are looking for a right (op2) operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e", that means we can create a RotR instead of an Add and a RotL */ - if (get_irn_op(op2) == op_Add) { + if (is_Add(op2)) { ir_node *add = op2; ir_node *left = get_Add_left(add); ir_node *right = get_Add_right(add); @@ -1707,19 +1594,19 @@ static ir_node *gen_Rot(ir_node *node) { ir_mode *mode = get_irn_mode(node); long bits = get_mode_size_bits(mode); - if (get_irn_op(left) == op_Minus && - tarval_is_long(tv) && - get_tarval_long(tv) == bits && - bits == 32) + if (is_Minus(left) && + tarval_is_long(tv) && + get_tarval_long(tv) == bits && + bits == 32) { DB((dbg, LEVEL_1, "RotL into RotR ... ")); - rotate = gen_RotR(node, op1, get_Minus_op(left)); + rotate = gen_Ror(node, op1, get_Minus_op(left)); } } } if (rotate == NULL) { - rotate = gen_RotL(node, op1, op2); + rotate = gen_Rol(node, op1, op2); } return rotate; @@ -1779,7 +1666,8 @@ static ir_node *gen_Minus(ir_node *node) * * @return The created ia32 Not node */ -static ir_node *gen_Not(ir_node *node) { +static ir_node *gen_Not(ir_node *node) +{ ir_node *op = get_Not_op(node); assert(get_irn_mode(node) != mode_b); /* should be lowered already */ @@ -1844,7 +1732,7 @@ static ir_node *gen_Abs(ir_node *node) sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, new_op, pval); - add_irn_dep(pval, get_irg_frame(irg)); + be_dep_on_frame(pval); SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node)); xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp, @@ -1859,9 +1747,28 @@ static ir_node *gen_Abs(ir_node *node) return new_node; } +/** + * Create a bt instruction for x & (1 << n) and place it into the block of cmp. + */ +static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) +{ + dbg_info *dbgi = get_irn_dbg_info(cmp); + ir_node *block = get_nodes_block(cmp); + ir_node *new_block = be_transform_node(block); + ir_node *op1 = be_transform_node(x); + ir_node *op2 = be_transform_node(n); + + return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2); +} + +/** + * Transform a node returning a "flag" result. + * + * @param node the node to transform + * @param pnc_out the compare mode to use + */ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) { - ir_graph *irg = current_ir_graph; ir_node *flags; ir_node *new_op; ir_node *noreg; @@ -1870,11 +1777,48 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) dbg_info *dbgi; /* we have a Cmp as input */ - if(is_Proj(node)) { + if (is_Proj(node)) { ir_node *pred = get_Proj_pred(node); - if(is_Cmp(pred)) { + if (is_Cmp(pred)) { + pn_Cmp pnc = get_Proj_proj(node); + if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) { + ir_node *l = get_Cmp_left(pred); + ir_node *r = get_Cmp_right(pred); + if (is_And(l)) { + ir_node *la = get_And_left(l); + ir_node *ra = get_And_right(l); + if (is_Shl(la)) { + ir_node *c = get_Shl_left(la); + if (is_Const_1(c) && (is_Const_0(r) || r == la)) { + /* (1 << n) & ra) */ + ir_node *n = get_Shl_right(la); + flags = gen_bt(pred, ra, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == la) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + if (is_Shl(ra)) { + ir_node *c = get_Shl_left(ra); + if (is_Const_1(c) && (is_Const_0(r) || r == ra)) { + /* la & (1 << n)) */ + ir_node *n = get_Shl_right(ra); + flags = gen_bt(pred, la, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == ra) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + } + } flags = be_transform_node(pred); - *pnc_out = get_Proj_proj(node); + *pnc_out = pnc; return flags; } } @@ -1885,8 +1829,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) new_op = be_transform_node(node); noreg = ia32_new_NoReg_gp(env_cg); nomem = new_NoMem(); - flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem, - new_op, new_op, 0, 0); + flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem, + new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); *pnc_out = pn_Cmp_Lg; return flags; } @@ -1896,7 +1840,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) * * @return the created ia32 Load node */ -static ir_node *gen_Load(ir_node *node) { +static ir_node *gen_Load(ir_node *node) +{ ir_node *old_block = get_nodes_block(node); ir_node *block = be_transform_node(old_block); ir_node *ptr = get_Load_ptr(node); @@ -1918,13 +1863,13 @@ static ir_node *gen_Load(ir_node *node) { base = addr.base; index = addr.index; - if(base == NULL) { + if (base == NULL) { base = noreg; } else { base = be_transform_node(base); } - if(index == NULL) { + if (index == NULL) { index = noreg; } else { index = be_transform_node(index); @@ -1944,7 +1889,7 @@ static ir_node *gen_Load(ir_node *node) { assert(mode != mode_b); /* create a conv node with address mode for smaller modes */ - if(get_mode_size_bits(mode) < 32) { + if (get_mode_size_bits(mode) < 32) { new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem, noreg, mode); } else { @@ -1958,19 +1903,13 @@ static ir_node *gen_Load(ir_node *node) { set_ia32_ls_mode(new_node, mode); set_address(new_node, &addr); - if(get_irn_pinned(node) == op_pin_state_floats) { + if (get_irn_pinned(node) == op_pin_state_floats) { add_ia32_flags(new_node, arch_irn_flags_rematerializable); } - /* make sure we are scheduled behind the initial IncSP/Barrier - * to avoid spills being placed before it - */ - if (block == get_irg_start_block(irg)) { - add_irn_dep(new_node, get_irg_frame(irg)); - } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + be_dep_on_frame(new_node); return new_node; } @@ -1979,30 +1918,49 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, { ir_node *load; - if(!is_Proj(node)) + if (!is_Proj(node)) return 0; /* we only use address mode if we're the only user of the load */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) > 1) return 0; load = get_Proj_pred(node); - if(!is_Load(load)) + if (!is_Load(load)) return 0; - if(get_nodes_block(load) != block) + if (get_nodes_block(load) != block) return 0; - /* Store should be attached to the load */ - if(!is_Proj(mem) || get_Proj_pred(mem) != load) - return 0; /* store should have the same pointer as the load */ - if(get_Load_ptr(load) != ptr) + if (get_Load_ptr(load) != ptr) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if(other != NULL && get_nodes_block(other) == block - && heights_reachable_in_block(heights, other, load)) + if (other != NULL && + get_nodes_block(other) == block && + heights_reachable_in_block(heights, other, load)) { return 0; + } + + if (is_Sync(mem)) { + int i; + + for (i = get_Sync_n_preds(mem) - 1; i >= 0; --i) { + ir_node *const pred = get_Sync_pred(mem, i); + + if (is_Proj(pred) && get_Proj_pred(pred) == load) + continue; + + if (get_nodes_block(pred) == block && + heights_reachable_in_block(heights, pred, load)) { + return 0; + } + } + } else { + /* Store should be attached to the load */ + if (!is_Proj(mem) || get_Proj_pred(mem) != load) + return 0; + } return 1; } @@ -2018,8 +1976,10 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_graph *irg = current_ir_graph; dbg_info *dbgi; + ir_node *new_mem; ir_node *new_node; ir_node *new_op; + ir_node *mem_proj; int commutative; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; @@ -2029,30 +1989,32 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, assert(flags & match_immediate); /* there is no destam node without... */ commutative = (flags & match_commutative) != 0; - if(use_dest_am(src_block, op1, mem, ptr, op2)) { + if (use_dest_am(src_block, op1, mem, ptr, op2)) { build_address(&am, op1); new_op = create_immediate_or_transform(op2, 0); - } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) { + } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) { build_address(&am, op2); new_op = create_immediate_or_transform(op1, 0); } else { return NULL; } - if(addr->base == NULL) + if (addr->base == NULL) addr->base = noreg_gp; - if(addr->index == NULL) + if (addr->index == NULL) addr->index = noreg_gp; - if(addr->mem == NULL) + if (addr->mem == NULL) addr->mem = new_NoMem(); - dbgi = get_irn_dbg_info(node); - block = be_transform_node(src_block); - if(get_mode_size_bits(mode) == 8) { + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); + new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem); + + if (get_mode_size_bits(mode) == 8) { new_node = func8bit(dbgi, irg, block, addr->base, addr->index, - addr->mem, new_op); + new_mem, new_op); } else { - new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, + new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem, new_op); } set_address(new_node, addr); @@ -2060,6 +2022,10 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, set_ia32_ls_mode(new_node, mode); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); + mem_proj = be_transform_node(am.mem_proj); + be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); + return new_node; } @@ -2067,35 +2033,43 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_unop_dest_func *func) { - ir_graph *irg = current_ir_graph; - ir_node *src_block = get_nodes_block(node); - ir_node *block; + ir_graph *irg = current_ir_graph; + ir_node *src_block = get_nodes_block(node); + ir_node *block; dbg_info *dbgi; - ir_node *new_node; + ir_node *new_mem; + ir_node *new_node; + ir_node *mem_proj; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); - if(!use_dest_am(src_block, op, mem, ptr, NULL)) + if (!use_dest_am(src_block, op, mem, ptr, NULL)) return NULL; build_address(&am, op); dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem); + new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem); + new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem); set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); + mem_proj = be_transform_node(am.mem_proj); + be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); + return new_node; } -static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { +static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) +{ ir_mode *mode = get_irn_mode(node); - ir_node *psi_true = get_Psi_val(node, 0); - ir_node *psi_default = get_Psi_default(node); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); ir_graph *irg; ir_node *cond; ir_node *new_mem; @@ -2108,12 +2082,12 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { pn_Cmp pnc; ia32_address_t addr; - if(get_mode_size_bits(mode) != 8) + if (get_mode_size_bits(mode) != 8) return NULL; - if(is_Const_1(psi_true) && is_Const_0(psi_default)) { + if (is_Const_1(mux_true) && is_Const_0(mux_false)) { negated = 0; - } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { + } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) { negated = 1; } else { return NULL; @@ -2125,7 +2099,7 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); - cond = get_Psi_cond(node, 0); + cond = get_Mux_sel(node); flags = get_flags_node(cond, &pnc); new_mem = be_transform_node(mem); new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base, @@ -2138,7 +2112,8 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { return new_node; } -static ir_node *try_create_dest_am(ir_node *node) { +static ir_node *try_create_dest_am(ir_node *node) +{ ir_node *val = get_Store_value(node); ir_node *mem = get_Store_mem(node); ir_node *ptr = get_Store_ptr(node); @@ -2149,18 +2124,20 @@ static ir_node *try_create_dest_am(ir_node *node) { ir_node *new_node; /* handle only GP modes for now... */ - if(!mode_needs_gp_reg(mode)) + if (!ia32_mode_needs_gp_reg(mode)) return NULL; - while(1) { + for (;;) { /* store must be the only user of the val node */ - if(get_irn_n_edges(val) > 1) + if (get_irn_n_edges(val) > 1) return NULL; /* skip pointless convs */ - if(is_Conv(val)) { + if (is_Conv(val)) { ir_node *conv_op = get_Conv_op(val); ir_mode *pred_mode = get_irn_mode(conv_op); - if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) { + if (!ia32_mode_needs_gp_reg(pred_mode)) + break; + if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) { val = conv_op; continue; } @@ -2169,18 +2146,18 @@ static ir_node *try_create_dest_am(ir_node *node) { } /* value must be in the same block */ - if(get_nodes_block(node) != get_nodes_block(val)) + if (get_nodes_block(node) != get_nodes_block(val)) return NULL; - switch(get_irn_opcode(val)) { + switch (get_irn_opcode(val)) { case iro_Add: op1 = get_Add_left(val); op2 = get_Add_right(val); - if(is_Const_1(op2)) { + if (is_Const_1(op2)) { new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_IncMem); break; - } else if(is_Const_Minus_1(op2)) { + } else if (is_Const_Minus_1(op2)) { new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_DecMem); break; @@ -2193,9 +2170,8 @@ static ir_node *try_create_dest_am(ir_node *node) { case iro_Sub: op1 = get_Sub_left(val); op2 = get_Sub_right(val); - if(is_Const(op2)) { - ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C" - "found\n"); + if (is_Const(op2)) { + ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n"); } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, @@ -2247,15 +2223,15 @@ static ir_node *try_create_dest_am(ir_node *node) { new_rd_ia32_SarMem, new_rd_ia32_SarMem, match_dest_am | match_immediate); break; - case iro_Rot: - op1 = get_Rot_left(val); - op2 = get_Rot_right(val); + case iro_Rotl: + op1 = get_Rotl_left(val); + op2 = get_Rotl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, new_rd_ia32_RolMem, new_rd_ia32_RolMem, match_dest_am | match_immediate); break; /* TODO: match ROR patterns... */ - case iro_Psi: + case iro_Mux: new_node = try_create_SetMem(val, ptr, mem); break; case iro_Minus: @@ -2272,8 +2248,8 @@ static ir_node *try_create_dest_am(ir_node *node) { return NULL; } - if(new_node != NULL) { - if(get_irn_pinned(new_node) != op_pin_state_pinned && + if (new_node != NULL) { + if (get_irn_pinned(new_node) != op_pin_state_pinned && get_irn_pinned(node) == op_pin_state_pinned) { set_irn_pinned(new_node, op_pin_state_pinned); } @@ -2282,62 +2258,141 @@ static ir_node *try_create_dest_am(ir_node *node) { return new_node; } -static int is_float_to_int32_conv(const ir_node *node) +static int is_float_to_int_conv(const ir_node *node) { ir_mode *mode = get_irn_mode(node); ir_node *conv_op; ir_mode *conv_mode; - if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode)) + if (mode != mode_Is && mode != mode_Hs) return 0; - if(!is_Conv(node)) + if (!is_Conv(node)) return 0; conv_op = get_Conv_op(node); conv_mode = get_irn_mode(conv_op); - if(!mode_is_float(conv_mode)) + if (!mode_is_float(conv_mode)) return 0; return 1; } /** - * Transforms a Store. + * Transform a Store(floatConst). * * @return the created ia32 Store node */ -static ir_node *gen_Store(ir_node *node) +static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) +{ + ir_mode *mode = get_irn_mode(cns); + unsigned size = get_mode_size_bytes(mode); + tarval *tv = get_Const_tarval(cns); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *ptr = get_Store_ptr(node); + ir_node *mem = get_Store_mem(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + int ofs = 0; + size_t i = 0; + ir_node *ins[4]; + ia32_address_t addr; + + assert(size % 4 == 0); + assert(size <= 16); + + build_address_ptr(&addr, ptr, mem); + + do { + unsigned val = + get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8) | + (get_tarval_sub_bits(tv, ofs + 2) << 16) | + (get_tarval_sub_bits(tv, ofs + 3) << 24); + ir_node *imm = create_Immediate(NULL, 0, val); + + ir_node *new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, imm); + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode_Iu); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + ins[i++] = new_node; + + size -= 4; + ofs += 4; + addr.offset += 4; + } while (size != 0); + + return i == 1 ? ins[0] : new_rd_Sync(dbgi, irg, new_block, i, ins); +} + +/** + * Generate a vfist or vfisttp instruction. + */ +static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, + ir_node *mem, ir_node *val, ir_node **fist) +{ + ir_node *new_node; + + if (ia32_cg_config.use_fisttp) { + /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied + if other users exists */ + const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; + ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val); + ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res); + be_new_Keep(reg_class, irg, block, 1, &value); + + new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M); + *fist = vfisttp; + } else { + ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + + /* do a fist */ + new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode); + *fist = new_node; + } + return new_node; +} +/** + * Transforms a normal Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_normal_Store(ir_node *node) { + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); - ir_node *val = get_Store_value(node); ir_node *mem = get_Store_mem(node); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_irn_mode(val); - ir_node *new_val; - ir_node *new_node; + ir_node *new_val, *new_node, *store; ia32_address_t addr; /* check for destination address mode */ new_node = try_create_dest_am(node); - if(new_node != NULL) + if (new_node != NULL) return new_node; /* construct store address */ memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, ptr, /*force=*/0); - if(addr.base == NULL) { + if (addr.base == NULL) { addr.base = noreg; } else { addr.base = be_transform_node(addr.base); } - if(addr.index == NULL) { + if (addr.index == NULL) { addr.index = noreg; } else { addr.index = be_transform_node(addr.index); @@ -2345,10 +2400,13 @@ static ir_node *gen_Store(ir_node *node) addr.mem = be_transform_node(mem); if (mode_is_float(mode)) { - /* convs (and strict-convs) before stores are unnecessary if the mode - is the same */ - while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { - val = get_Conv_op(val); + /* Convs (and strict-Convs) before stores are unnecessary if the mode + is the same. */ + while (is_Conv(val) && mode == get_irn_mode(val)) { + ir_node *op = get_Conv_op(val); + if (!mode_is_float(get_irn_mode(op))) + break; + val = op; } new_val = be_transform_node(val); if (ia32_cg_config.use_sse2) { @@ -2358,19 +2416,22 @@ static ir_node *gen_Store(ir_node *node) new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - } else if(is_float_to_int32_conv(val)) { - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + store = new_node; + } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) { val = get_Conv_op(val); - /* convs (and strict-convs) before stores are unnecessary if the mode - is the same */ - while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { - val = get_Conv_op(val); + /* TODO: is this optimisation still necessary at all (middleend)? */ + /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */ + while (is_Conv(val)) { + ir_node *op = get_Conv_op(val); + if (!mode_is_float(get_irn_mode(op))) + break; + if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val))) + break; + val = op; } - new_val = be_transform_node(val); - - new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base, - addr.index, addr.mem, new_val, trunc_mode); + new_val = be_transform_node(val); + new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2382,18 +2443,49 @@ static ir_node *gen_Store(ir_node *node) new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val); } + store = new_node; } - set_irn_pinned(new_node, get_irn_pinned(node)); - set_ia32_op_type(new_node, ia32_AddrModeD); - set_ia32_ls_mode(new_node, mode); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode); - set_address(new_node, &addr); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + set_address(store, &addr); + SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node)); return new_node; } +/** + * Transforms a Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_Store(ir_node *node) +{ + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); + + if (mode_is_float(mode) && is_Const(val)) { + int transform; + + /* we are storing a floating point constant */ + if (ia32_cg_config.use_sse2) { + transform = !is_simple_sse_Const(val); + } else { + transform = !is_simple_x87_Const(val); + } + if (transform) + return gen_float_const_Store(node, val); + } + return gen_normal_Store(node); +} + +/** + * Transforms a Switch. + * + * @return the created ia32 SwitchJmp node + */ static ir_node *create_Switch(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -2413,16 +2505,16 @@ static ir_node *create_Switch(ir_node *node) foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); long pn = get_Proj_proj(proj); - if(pn == default_pn) + if (pn == default_pn) continue; - if(pn < switch_min) + if (pn < switch_min) switch_min = pn; - if(pn > switch_max) + if (pn > switch_max) switch_max = pn; } - if((unsigned) (switch_max - switch_min) > 256000) { + if ((unsigned) (switch_max - switch_min) > 256000) { panic("Size of switch %+F bigger than 256000", node); } @@ -2446,7 +2538,8 @@ static ir_node *create_Switch(ir_node *node) /** * Transform a Cond node. */ -static ir_node *gen_Cond(ir_node *node) { +static ir_node *gen_Cond(ir_node *node) +{ ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_graph *irg = current_ir_graph; @@ -2461,7 +2554,7 @@ static ir_node *gen_Cond(ir_node *node) { return create_Switch(node); } - /* we get flags from a cmp */ + /* we get flags from a Cmp */ flags = get_flags_node(sel, &pnc); new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); @@ -2470,56 +2563,12 @@ static ir_node *gen_Cond(ir_node *node) { return new_node; } - - -/** - * Transforms a CopyB node. - * - * @return The transformed node. - */ -static ir_node *gen_CopyB(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *src = get_CopyB_src(node); - ir_node *new_src = be_transform_node(src); - ir_node *dst = get_CopyB_dst(node); - ir_node *new_dst = be_transform_node(dst); - ir_node *mem = get_CopyB_mem(node); - ir_node *new_mem = be_transform_node(mem); - ir_node *res = NULL; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - int size = get_type_size_bytes(get_CopyB_type(node)); - int rem; - - /* If we have to copy more than 32 bytes, we use REP MOVSx and */ - /* then we need the size explicitly in ECX. */ - if (size >= 32 * 4) { - rem = size & 0x3; /* size % 4 */ - size >>= 2; - - res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size); - add_irn_dep(res, get_irg_frame(irg)); - - res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem); - } else { - if(size == 0) { - ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n", - node); - } - res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size); - } - - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - - return res; -} - static ir_node *gen_be_Copy(ir_node *node) { ir_node *new_node = be_duplicate_node(node); ir_mode *mode = get_irn_mode(new_node); - if (mode_needs_gp_reg(mode)) { + if (ia32_mode_needs_gp_reg(mode)) { set_irn_mode(new_node, mode_Iu); } @@ -2538,14 +2587,14 @@ static ir_node *create_Fucom(ir_node *node) ir_node *new_right; ir_node *new_node; - if(ia32_cg_config.use_fucomi) { + if (ia32_cg_config.use_fucomi) { new_right = be_transform_node(right); new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0); set_ia32_commutative(new_node); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } else { - if(ia32_cg_config.use_ftst && is_Const_0(right)) { + if (ia32_cg_config.use_ftst && is_Const_0(right)) { new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0); } else { @@ -2593,10 +2642,10 @@ static ir_node *create_Ucomi(ir_node *node) } /** - * helper function: checks wether all Cmp projs are Lg or Eq which is needed + * helper function: checks whether all Cmp projs are Lg or Eq which is needed * to fold an and into a test node */ -static int can_fold_test_and(ir_node *node) +static bool can_fold_test_and(ir_node *node) { const ir_edge_t *edge; @@ -2604,13 +2653,90 @@ static int can_fold_test_and(ir_node *node) foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); pn_Cmp pnc = get_Proj_proj(proj); - if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) - return 0; + if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) + return false; } - return 1; + return true; +} + +/** + * returns true if it is assured, that the upper bits of a node are "clean" + * which means for a 16 or 8 bit value, that the upper bits in the register + * are 0 for unsigned and a copy of the last significant bit for signed + * numbers. + */ +static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode) +{ + assert(ia32_mode_needs_gp_reg(mode)); + if (get_mode_size_bits(mode) >= 32) + return true; + + if (is_Proj(transformed_node)) + return upper_bits_clean(get_Proj_pred(transformed_node), mode); + + if (is_ia32_Conv_I2I(transformed_node) + || is_ia32_Conv_I2I8Bit(transformed_node)) { + ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node); + if (mode_is_signed(smaller_mode) != mode_is_signed(mode)) + return false; + if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode)) + return false; + + return true; + } + + if (is_ia32_Shr(transformed_node) && !mode_is_signed(mode)) { + ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count); + if (is_ia32_Immediate(right) || is_ia32_Const(right)) { + const ia32_immediate_attr_t *attr + = get_ia32_immediate_attr_const(right); + if (attr->symconst == 0 + && (unsigned) attr->offset >= (32 - get_mode_size_bits(mode))) { + return true; + } + } + return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode); + } + + if (is_ia32_And(transformed_node) && !mode_is_signed(mode)) { + ir_node *right = get_irn_n(transformed_node, n_ia32_And_right); + if (is_ia32_Immediate(right) || is_ia32_Const(right)) { + const ia32_immediate_attr_t *attr + = get_ia32_immediate_attr_const(right); + if (attr->symconst == 0 + && (unsigned) attr->offset + <= (0xffffffff >> (32 - get_mode_size_bits(mode)))) { + return true; + } + } + /* TODO recurse? */ + } + + /* TODO recurse on Or, Xor, ... if appropriate? */ + + if (is_ia32_Immediate(transformed_node) + || is_ia32_Const(transformed_node)) { + const ia32_immediate_attr_t *attr + = get_ia32_immediate_attr_const(transformed_node); + if (mode_is_signed(mode)) { + long shifted = attr->offset >> (get_mode_size_bits(mode) - 1); + if (shifted == 0 || shifted == -1) + return true; + } else { + unsigned long shifted = (unsigned long) attr->offset; + shifted >>= get_mode_size_bits(mode); + if (shifted == 0) + return true; + } + } + + return false; } +/** + * Generate code for a Cmp. + */ static ir_node *gen_Cmp(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -2625,7 +2751,7 @@ static ir_node *gen_Cmp(ir_node *node) ia32_address_t *addr = &am.addr; int cmp_unsigned; - if(mode_is_float(cmp_mode)) { + if (mode_is_float(cmp_mode)) { if (ia32_cg_config.use_sse2) { return create_Ucomi(node); } else { @@ -2633,66 +2759,46 @@ static ir_node *gen_Cmp(ir_node *node) } } - assert(mode_needs_gp_reg(cmp_mode)); + assert(ia32_mode_needs_gp_reg(cmp_mode)); - /* we prefer the Test instruction where possible except cases where - * we can use SourceAM */ + /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */ cmp_unsigned = !mode_is_signed(cmp_mode); - if (is_Const_0(right)) { - if (is_And(left) && - get_irn_n_edges(left) == 1 && - can_fold_test_and(node)) { - /* Test(and_left, and_right) */ - ir_node *and_left = get_And_left(left); - ir_node *and_right = get_And_right(left); - ir_mode *mode = get_irn_mode(and_left); - - match_arguments(&am, block, and_left, and_right, NULL, - match_commutative | - match_am | match_8bit_am | match_16bit_am | - match_am_and_immediates | match_immediate | - match_8bit | match_16bit); - if (get_mode_size_bits(mode) == 8) { - new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, - cmp_unsigned); - } else { - new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, cmp_unsigned); - } + if (is_Const_0(right) && + is_And(left) && + get_irn_n_edges(left) == 1 && + can_fold_test_and(node)) { + /* Test(and_left, and_right) */ + ir_node *and_left = get_And_left(left); + ir_node *and_right = get_And_right(left); + + /* matze: code here used mode instead of cmd_mode, I think it is always + * the same as cmp_mode, but I leave this here to see if this is really + * true... + */ + assert(get_irn_mode(and_left) == cmp_mode); + + match_arguments(&am, block, and_left, and_right, NULL, + match_commutative | + match_am | match_8bit_am | match_16bit_am | + match_am_and_immediates | match_immediate | + match_8bit | match_16bit); + + /* use 32bit compare mode if possible since the opcode is smaller */ + if (upper_bits_clean(am.new_op1, cmp_mode) && + upper_bits_clean(am.new_op2, cmp_mode)) { + cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; + } + + if (get_mode_size_bits(cmp_mode) == 8) { + new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); } else { - match_arguments(&am, block, NULL, left, NULL, - match_am | match_8bit_am | match_16bit_am | - match_8bit | match_16bit); - if (am.op_type == ia32_AddrModeS) { - /* Cmp(AM, 0) */ - ir_node *imm_zero = try_create_Immediate(right, 0); - if (get_mode_size_bits(cmp_mode) == 8) { - new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - imm_zero, am.ins_permuted, - cmp_unsigned); - } else { - new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - imm_zero, am.ins_permuted, cmp_unsigned); - } - } else { - /* Test(left, left) */ - if (get_mode_size_bits(cmp_mode) == 8) { - new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - am.new_op2, am.ins_permuted, - cmp_unsigned); - } else { - new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - am.new_op2, am.ins_permuted, - cmp_unsigned); - } - } + new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); } } else { /* Cmp(left, right) */ @@ -2700,6 +2806,12 @@ static ir_node *gen_Cmp(ir_node *node) match_commutative | match_am | match_8bit_am | match_16bit_am | match_am_and_immediates | match_immediate | match_8bit | match_16bit); + /* use 32bit compare mode if possible since the opcode is smaller */ + if (upper_bits_clean(am.new_op1, cmp_mode) && + upper_bits_clean(am.new_op2, cmp_mode)) { + cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; + } + if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op1, @@ -2712,7 +2824,6 @@ static ir_node *gen_Cmp(ir_node *node) } } set_am_attributes(new_node, &am); - assert(cmp_mode != NULL); set_ia32_ls_mode(new_node, cmp_mode); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -2729,15 +2840,15 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *val_true = get_Psi_val(node, 0); - ir_node *val_false = get_Psi_default(node); + ir_node *val_true = get_Mux_true(node); + ir_node *val_false = get_Mux_false(node); ir_node *new_node; match_flags_t match_flags; ia32_address_mode_t am; ia32_address_t *addr; assert(ia32_cg_config.use_cmov); - assert(mode_needs_gp_reg(get_irn_mode(val_true))); + assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true))); addr = &am.addr; @@ -2758,8 +2869,9 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, return new_node; } - - +/** + * Creates a ia32 Setcc instruction. + */ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, ir_node *flags, pn_Cmp pnc, ir_node *orig_node, int ins_permuted) @@ -2774,7 +2886,7 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); /* we might need to conv the result up */ - if(get_mode_size_bits(mode) > 8) { + if (get_mode_size_bits(mode) > 8) { new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, new_node, mode_Bu); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); @@ -2784,43 +2896,145 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, } /** - * Transforms a Psi node into CMov. + * Create instruction for an unsigned Difference or Zero. + */ +static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) +{ + ir_graph *irg = current_ir_graph; + ir_mode *mode = get_irn_mode(psi); + ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem; + dbg_info *dbgi; + + new_node = gen_binop(psi, a, b, new_rd_ia32_Sub, + match_mode_neutral | match_am | match_immediate | match_two_users); + + block = get_nodes_block(new_node); + + if (is_Proj(new_node)) { + sub = get_Proj_pred(new_node); + assert(is_ia32_Sub(sub)); + } else { + sub = new_node; + set_irn_mode(sub, mode_T); + new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res); + } + eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + + dbgi = get_irn_dbg_info(psi); + noreg = ia32_new_NoReg_gp(env_cg); + tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block); + nomem = new_NoMem(); + sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags); + + new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb); + set_ia32_commutative(new_node); + return new_node; +} + +/** + * Transforms a Mux node into CMov. * * @return The transformed node. */ -static ir_node *gen_Psi(ir_node *node) +static ir_node *gen_Mux(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *psi_true = get_Psi_val(node, 0); - ir_node *psi_default = get_Psi_default(node); - ir_node *cond = get_Psi_cond(node, 0); - ir_node *flags = NULL; - ir_node *new_node; - pn_Cmp pnc; + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *cond = get_Mux_sel(node); + ir_mode *mode = get_irn_mode(node); + pn_Cmp pnc; - assert(get_Psi_n_conds(node) == 1); assert(get_irn_mode(cond) == mode_b); - assert(mode_needs_gp_reg(get_irn_mode(node))); - flags = get_flags_node(cond, &pnc); + /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */ + if (mode_is_float(mode)) { + ir_node *cmp = get_Proj_pred(cond); + ir_node *cmp_left = get_Cmp_left(cmp); + ir_node *cmp_right = get_Cmp_right(cmp); + pn_Cmp pnc = get_Proj_proj(cond); + + if (ia32_cg_config.use_sse2) { + if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) { + if (cmp_left == mux_true && cmp_right == mux_false) { + /* Mux(a <= b, a, b) => MIN */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + match_commutative | match_am | match_two_users); + } else if (cmp_left == mux_false && cmp_right == mux_true) { + /* Mux(a <= b, b, a) => MAX */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + match_commutative | match_am | match_two_users); + } + } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) { + if (cmp_left == mux_true && cmp_right == mux_false) { + /* Mux(a >= b, a, b) => MAX */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + match_commutative | match_am | match_two_users); + } else if (cmp_left == mux_false && cmp_right == mux_true) { + /* Mux(a >= b, b, a) => MIN */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + match_commutative | match_am | match_two_users); + } + } + } + panic("cannot transform floating point Mux"); - if(is_Const_1(psi_true) && is_Const_0(psi_default)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0); - } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); } else { - new_node = create_CMov(node, cond, flags, pnc); + ir_node *flags; + ir_node *new_node; + + assert(ia32_mode_needs_gp_reg(mode)); + + if (is_Proj(cond)) { + ir_node *cmp = get_Proj_pred(cond); + if (is_Cmp(cmp)) { + ir_node *cmp_left = get_Cmp_left(cmp); + ir_node *cmp_right = get_Cmp_right(cmp); + pn_Cmp pnc = get_Proj_proj(cond); + + /* check for unsigned Doz first */ + if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) && + is_Const_0(mux_false) && is_Sub(mux_true) && + get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) { + /* Mux(a >=u b, a - b, 0) unsigned Doz */ + return create_Doz(node, cmp_left, cmp_right); + } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) && + is_Const_0(mux_true) && is_Sub(mux_false) && + get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) { + /* Mux(a <=u b, 0, a - b) unsigned Doz */ + return create_Doz(node, cmp_left, cmp_right); + } + } + } + + flags = get_flags_node(cond, &pnc); + + if (is_Const(mux_true) && is_Const(mux_false)) { + /* both are const, good */ + if (is_Const_1(mux_true) && is_Const_0(mux_false)) { + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); + } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) { + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1); + } else { + /* Not that simple. */ + goto need_cmov; + } + } else { +need_cmov: + new_node = create_CMov(node, cond, flags, pnc); + } + return new_node; } - return new_node; } /** * Create a conversion from x87 state register to general purpose. */ -static ir_node *gen_x87_fp_to_gp(ir_node *node) { +static ir_node *gen_x87_fp_to_gp(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); ir_node *new_op = be_transform_node(op); @@ -2828,14 +3042,10 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *trunc_mode = ia32_new_Fpu_truncate(cg); ir_mode *mode = get_irn_mode(node); - ir_node *fist, *load; - - /* do a fist */ - fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, - new_NoMem(), new_op, trunc_mode); + ir_node *fist, *load, *mem; + mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -2843,7 +3053,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { assert(get_mode_size_bits(mode) <= 32); /* exception we can only store signed 32 bit integers, so for unsigned we store a 64bit (signed) integer and load the lower bits */ - if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) { + if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) { set_ia32_ls_mode(fist, mode_Ls); } else { set_ia32_ls_mode(fist, mode_Is); @@ -2851,13 +3061,13 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node)); /* do a Load */ - load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist); + load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem); set_irn_pinned(load, op_pin_state_floats); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_ls_mode(load, mode_Is); - if(get_ia32_ls_mode(fist) == mode_Ls) { + if (get_ia32_ls_mode(fist) == mode_Ls) { ia32_attr_t *attr = get_ia32_attr(load); attr->data.need_64bit_stackent = 1; } else { @@ -2870,7 +3080,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { } /** - * Creates a x87 strict Conv by placing a Sore and a Load + * Creates a x87 strict Conv by placing a Store and a Load */ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) { @@ -2902,7 +3112,8 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) /** * Create a conversion from general purpose to x87 register */ -static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { +static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; @@ -2918,12 +3129,12 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { ir_node *new_node; int src_bits; - /* fild can use source AM if the operand is a signed 32bit integer */ - if (src_mode == mode_Is) { + /* fild can use source AM if the operand is a signed 16bit or 32bit integer */ + if (src_mode == mode_Is || src_mode == mode_Hs) { ia32_address_mode_t am; match_arguments(&am, src_block, NULL, op, NULL, - match_am | match_try_am); + match_am | match_try_am | match_16bit | match_16bit_am); if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; @@ -2940,7 +3151,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { return new_node; } } - if(new_op == NULL) { + if (new_op == NULL) { new_op = be_transform_node(op); } @@ -2973,7 +3184,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { set_ia32_ls_mode(store, mode_Iu); /* exception for 32bit unsigned, do a 64bit spill+load */ - if(!mode_is_signed(mode)) { + if (!mode_is_signed(mode)) { ir_node *in[2]; /* store a zero */ ir_node *zero_const = create_Immediate(NULL, 0, 0); @@ -3035,7 +3246,7 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, } #ifdef DEBUG_libfirm - if(is_Const(op)) { + if (is_Const(op)) { ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n", op); } @@ -3044,6 +3255,17 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, match_arguments(&am, block, NULL, op, NULL, match_8bit | match_16bit | match_am | match_8bit_am | match_16bit_am); + + if (upper_bits_clean(am.new_op2, smaller_mode)) { + /* unnecessary conv. in theory it shouldn't have been AM */ + assert(is_ia32_NoReg_GP(addr->base)); + assert(is_ia32_NoReg_GP(addr->index)); + assert(is_NoMem(addr->mem)); + assert(am.addr.offset == 0); + assert(am.addr.symconst_ent == NULL); + return am.new_op2; + } + if (smaller_bits == 8) { new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op2, @@ -3067,7 +3289,8 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, * * @return The created ia32 Conv node */ -static ir_node *gen_Conv(ir_node *node) { +static ir_node *gen_Conv(ir_node *node) +{ ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *op = get_Conv_op(node); @@ -3106,7 +3329,7 @@ static ir_node *gen_Conv(ir_node *node) { new_op = be_transform_node(op); /* we convert from float ... */ if (mode_is_float(tgt_mode)) { - if(src_mode == mode_E && tgt_mode == mode_D + if (src_mode == mode_E && tgt_mode == mode_D && !get_Conv_strict(node)) { DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); return new_op; @@ -3119,7 +3342,7 @@ static ir_node *gen_Conv(ir_node *node) { nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { - if(get_Conv_strict(node)) { + if (get_Conv_strict(node)) { res = gen_x87_strict_conv(tgt_mode, new_op); SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node)); return res; @@ -3150,14 +3373,27 @@ static ir_node *gen_Conv(ir_node *node) { set_ia32_ls_mode(res, tgt_mode); } else { res = gen_x87_gp_to_fp(node, src_mode); - if(get_Conv_strict(node)) { - res = gen_x87_strict_conv(tgt_mode, res); - SET_IA32_ORIG_NODE(get_Proj_pred(res), - ia32_get_old_node_name(env_cg, node)); + if (get_Conv_strict(node)) { + /* The strict-Conv is only necessary, if the int mode has more bits + * than the float mantissa */ + size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); + size_t float_mantissa; + /* FIXME There is no way to get the mantissa size of a mode */ + switch (get_mode_size_bits(tgt_mode)) { + case 32: float_mantissa = 23 + 1; break; // + 1 for implicit 1 + case 64: float_mantissa = 52 + 1; break; + case 80: + case 96: float_mantissa = 64; break; + default: float_mantissa = 0; break; + } + if (float_mantissa < int_mantissa) { + res = gen_x87_strict_conv(tgt_mode, res); + SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node)); + } } return res; } - } else if(tgt_mode == mode_b) { + } else if (tgt_mode == mode_b) { /* mode_b lowering already took care that we only have 0/1 values */ DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); @@ -3178,135 +3414,6 @@ static ir_node *gen_Conv(ir_node *node) { return res; } -static int check_immediate_constraint(long val, char immediate_constraint_type) -{ - switch (immediate_constraint_type) { - case 0: - return 1; - case 'I': - return val >= 0 && val <= 32; - case 'J': - return val >= 0 && val <= 63; - case 'K': - return val >= -128 && val <= 127; - case 'L': - return val == 0xff || val == 0xffff; - case 'M': - return val >= 0 && val <= 3; - case 'N': - return val >= 0 && val <= 255; - case 'O': - return val >= 0 && val <= 127; - default: - break; - } - panic("Invalid immediate constraint found"); - return 0; -} - -static ir_node *try_create_Immediate(ir_node *node, - char immediate_constraint_type) -{ - int minus = 0; - tarval *offset = NULL; - int offset_sign = 0; - long val = 0; - ir_entity *symconst_ent = NULL; - int symconst_sign = 0; - ir_mode *mode; - ir_node *cnst = NULL; - ir_node *symconst = NULL; - ir_node *new_node; - - mode = get_irn_mode(node); - if(!mode_is_int(mode) && !mode_is_reference(mode)) { - return NULL; - } - - if(is_Minus(node)) { - minus = 1; - node = get_Minus_op(node); - } - - if(is_Const(node)) { - cnst = node; - symconst = NULL; - offset_sign = minus; - } else if(is_SymConst(node)) { - cnst = NULL; - symconst = node; - symconst_sign = minus; - } else if(is_Add(node)) { - ir_node *left = get_Add_left(node); - ir_node *right = get_Add_right(node); - if(is_Const(left) && is_SymConst(right)) { - cnst = left; - symconst = right; - symconst_sign = minus; - offset_sign = minus; - } else if(is_SymConst(left) && is_Const(right)) { - cnst = right; - symconst = left; - symconst_sign = minus; - offset_sign = minus; - } - } else if(is_Sub(node)) { - ir_node *left = get_Sub_left(node); - ir_node *right = get_Sub_right(node); - if(is_Const(left) && is_SymConst(right)) { - cnst = left; - symconst = right; - symconst_sign = !minus; - offset_sign = minus; - } else if(is_SymConst(left) && is_Const(right)) { - cnst = right; - symconst = left; - symconst_sign = minus; - offset_sign = !minus; - } - } else { - return NULL; - } - - if(cnst != NULL) { - offset = get_Const_tarval(cnst); - if(tarval_is_long(offset)) { - val = get_tarval_long(offset); - } else { - ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a " - "long?\n", cnst); - return NULL; - } - - if(!check_immediate_constraint(val, immediate_constraint_type)) - return NULL; - } - if(symconst != NULL) { - if(immediate_constraint_type != 0) { - /* we need full 32bits for symconsts */ - return NULL; - } - - /* unfortunately the assembler/linker doesn't support -symconst */ - if(symconst_sign) - return NULL; - - if(get_SymConst_kind(symconst) != symconst_addr_ent) - return NULL; - symconst_ent = get_SymConst_entity(symconst); - } - if(cnst == NULL && symconst == NULL) - return NULL; - - if(offset_sign && offset != NULL) { - offset = tarval_neg(offset); - } - - new_node = create_Immediate(symconst_ent, symconst_sign, val); - - return new_node; -} - static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type) { @@ -3317,487 +3424,11 @@ static ir_node *create_immediate_or_transform(ir_node *node, return new_node; } -static const arch_register_req_t no_register_req = { - arch_register_req_type_none, - NULL, /* regclass */ - NULL, /* limit bitset */ - 0, /* same pos */ - 0 /* different pos */ -}; - -/** - * An assembler constraint. - */ -typedef struct constraint_t constraint_t; -struct constraint_t { - int is_in; - int n_outs; - const arch_register_req_t **out_reqs; - - const arch_register_req_t *req; - unsigned immediate_possible; - char immediate_type; -}; - -static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) -{ - int immediate_possible = 0; - char immediate_type = 0; - unsigned limited = 0; - const arch_register_class_t *cls = NULL; - ir_graph *irg = current_ir_graph; - struct obstack *obst = get_irg_obstack(irg); - arch_register_req_t *req; - unsigned *limited_ptr = NULL; - int p; - int same_as = -1; - - /* TODO: replace all the asserts with nice error messages */ - - if(*c == 0) { - /* a memory constraint: no need to do anything in backend about it - * (the dependencies are already respected by the memory edge of - * the node) */ - constraint->req = &no_register_req; - return; - } - - while(*c != 0) { - switch(*c) { - case ' ': - case '\t': - case '\n': - break; - - case 'a': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX; - break; - case 'b': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EBX; - break; - case 'c': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ECX; - break; - case 'd': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDX; - break; - case 'D': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDI; - break; - case 'S': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ESI; - break; - case 'Q': - case 'q': /* q means lower part of the regs only, this makes no - * difference to Q for us (we only assigne whole registers) */ - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX; - break; - case 'A': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EDX; - break; - case 'l': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI | - 1 << REG_EBP; - break; - - case 'R': - case 'r': - case 'p': - assert(cls == NULL); - cls = &ia32_reg_classes[CLASS_ia32_gp]; - break; - - case 'f': - case 't': - case 'u': - /* TODO: mark values so the x87 simulator knows about t and u */ - assert(cls == NULL); - cls = &ia32_reg_classes[CLASS_ia32_vfp]; - break; - - case 'Y': - case 'x': - assert(cls == NULL); - /* TODO: check that sse2 is supported */ - cls = &ia32_reg_classes[CLASS_ia32_xmm]; - break; - - case 'I': - case 'J': - case 'K': - case 'L': - case 'M': - case 'N': - case 'O': - assert(!immediate_possible); - immediate_possible = 1; - immediate_type = *c; - break; - case 'n': - case 'i': - assert(!immediate_possible); - immediate_possible = 1; - break; - - case 'g': - assert(!immediate_possible && cls == NULL); - immediate_possible = 1; - cls = &ia32_reg_classes[CLASS_ia32_gp]; - break; - - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - assert(constraint->is_in && "can only specify same constraint " - "on input"); - - sscanf(c, "%d%n", &same_as, &p); - if(same_as >= 0) { - c += p; - continue; - } - break; - - case 'm': - /* memory constraint no need to do anything in backend about it - * (the dependencies are already respected by the memory edge of - * the node) */ - constraint->req = &no_register_req; - return; - - case 'E': /* no float consts yet */ - case 'F': /* no float consts yet */ - case 's': /* makes no sense on x86 */ - case 'X': /* we can't support that in firm */ - case 'o': - case 'V': - case '<': /* no autodecrement on x86 */ - case '>': /* no autoincrement on x86 */ - case 'C': /* sse constant not supported yet */ - case 'G': /* 80387 constant not supported yet */ - case 'y': /* we don't support mmx registers yet */ - case 'Z': /* not available in 32 bit mode */ - case 'e': /* not available in 32 bit mode */ - panic("unsupported asm constraint '%c' found in (%+F)", - *c, current_ir_graph); - break; - default: - panic("unknown asm constraint '%c' found in (%+F)", *c, - current_ir_graph); - break; - } - ++c; - } - - if(same_as >= 0) { - const arch_register_req_t *other_constr; - - assert(cls == NULL && "same as and register constraint not supported"); - assert(!immediate_possible && "same as and immediate constraint not " - "supported"); - assert(same_as < constraint->n_outs && "wrong constraint number in " - "same_as constraint"); - - other_constr = constraint->out_reqs[same_as]; - - req = obstack_alloc(obst, sizeof(req[0])); - req->cls = other_constr->cls; - req->type = arch_register_req_type_should_be_same; - req->limited = NULL; - req->other_same = 1U << pos; - req->other_different = 0; - - /* switch constraints. This is because in firm we have same_as - * constraints on the output constraints while in the gcc asm syntax - * they are specified on the input constraints */ - constraint->req = other_constr; - constraint->out_reqs[same_as] = req; - constraint->immediate_possible = 0; - return; - } - - if(immediate_possible && cls == NULL) { - cls = &ia32_reg_classes[CLASS_ia32_gp]; - } - assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]); - assert(cls != NULL); - - if(immediate_possible) { - assert(constraint->is_in - && "immediate make no sense for output constraints"); - } - /* todo: check types (no float input on 'r' constrained in and such... */ - - if(limited != 0) { - req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); - limited_ptr = (unsigned*) (req+1); - } else { - req = obstack_alloc(obst, sizeof(req[0])); - } - memset(req, 0, sizeof(req[0])); - - if(limited != 0) { - req->type = arch_register_req_type_limited; - *limited_ptr = limited; - req->limited = limited_ptr; - } else { - req->type = arch_register_req_type_normal; - } - req->cls = cls; - - constraint->req = req; - constraint->immediate_possible = immediate_possible; - constraint->immediate_type = immediate_type; -} - -static void parse_clobber(ir_node *node, int pos, constraint_t *constraint, - const char *clobber) -{ - ir_graph *irg = get_irn_irg(node); - struct obstack *obst = get_irg_obstack(irg); - const arch_register_t *reg = NULL; - int c; - size_t r; - arch_register_req_t *req; - const arch_register_class_t *cls; - unsigned *limited; - - (void) pos; - - /* TODO: construct a hashmap instead of doing linear search for clobber - * register */ - for(c = 0; c < N_CLASSES; ++c) { - cls = & ia32_reg_classes[c]; - for(r = 0; r < cls->n_regs; ++r) { - const arch_register_t *temp_reg = arch_register_for_index(cls, r); - if(strcmp(temp_reg->name, clobber) == 0 - || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { - reg = temp_reg; - break; - } - } - if(reg != NULL) - break; - } - if(reg == NULL) { - panic("Register '%s' mentioned in asm clobber is unknown\n", clobber); - return; - } - - assert(reg->index < 32); - - limited = obstack_alloc(obst, sizeof(limited[0])); - *limited = 1 << reg->index; - - req = obstack_alloc(obst, sizeof(req[0])); - memset(req, 0, sizeof(req[0])); - req->type = arch_register_req_type_limited; - req->cls = cls; - req->limited = limited; - - constraint->req = req; - constraint->immediate_possible = 0; - constraint->immediate_type = 0; -} - -static int is_memory_op(const ir_asm_constraint *constraint) -{ - ident *id = constraint->constraint; - const char *str = get_id_str(id); - const char *c; - - for(c = str; *c != '\0'; ++c) { - if(*c == 'm') - return 1; - } - - return 0; -} - -/** - * generates code for a ASM node - */ -static ir_node *gen_ASM(ir_node *node) -{ - int i, arity; - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node **in; - ir_node *new_node; - int out_arity; - int n_out_constraints; - int n_clobbers; - const arch_register_req_t **out_reg_reqs; - const arch_register_req_t **in_reg_reqs; - ia32_asm_reg_t *register_map; - unsigned reg_map_size = 0; - struct obstack *obst; - const ir_asm_constraint *in_constraints; - const ir_asm_constraint *out_constraints; - ident **clobbers; - constraint_t parsed_constraint; - - arity = get_irn_arity(node); - in = alloca(arity * sizeof(in[0])); - memset(in, 0, arity * sizeof(in[0])); - - n_out_constraints = get_ASM_n_output_constraints(node); - n_clobbers = get_ASM_n_clobbers(node); - out_arity = n_out_constraints + n_clobbers; - /* hack to keep space for mem proj */ - if(n_clobbers > 0) - out_arity += 1; - - in_constraints = get_ASM_input_constraints(node); - out_constraints = get_ASM_output_constraints(node); - clobbers = get_ASM_clobbers(node); - - /* construct output constraints */ - obst = get_irg_obstack(irg); - out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0])); - parsed_constraint.out_reqs = out_reg_reqs; - parsed_constraint.n_outs = n_out_constraints; - parsed_constraint.is_in = 0; - - for(i = 0; i < out_arity; ++i) { - const char *c; - - if(i < n_out_constraints) { - const ir_asm_constraint *constraint = &out_constraints[i]; - c = get_id_str(constraint->constraint); - parse_asm_constraint(i, &parsed_constraint, c); - - if(constraint->pos > reg_map_size) - reg_map_size = constraint->pos; - - out_reg_reqs[i] = parsed_constraint.req; - } else if(i < out_arity - 1) { - ident *glob_id = clobbers [i - n_out_constraints]; - assert(glob_id != NULL); - c = get_id_str(glob_id); - parse_clobber(node, i, &parsed_constraint, c); - - out_reg_reqs[i+1] = parsed_constraint.req; - } - } - if(n_clobbers > 1) - out_reg_reqs[n_out_constraints] = &no_register_req; - - /* construct input constraints */ - in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); - parsed_constraint.is_in = 1; - for(i = 0; i < arity; ++i) { - const ir_asm_constraint *constraint = &in_constraints[i]; - ident *constr_id = constraint->constraint; - const char *c = get_id_str(constr_id); - - parse_asm_constraint(i, &parsed_constraint, c); - in_reg_reqs[i] = parsed_constraint.req; - - if(constraint->pos > reg_map_size) - reg_map_size = constraint->pos; - - if(parsed_constraint.immediate_possible) { - ir_node *pred = get_irn_n(node, i); - char imm_type = parsed_constraint.immediate_type; - ir_node *immediate = try_create_Immediate(pred, imm_type); - - if(immediate != NULL) { - in[i] = immediate; - } - } - } - reg_map_size++; - - register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size); - memset(register_map, 0, reg_map_size * sizeof(register_map[0])); - - for(i = 0; i < n_out_constraints; ++i) { - const ir_asm_constraint *constraint = &out_constraints[i]; - unsigned pos = constraint->pos; - - assert(pos < reg_map_size); - register_map[pos].use_input = 0; - register_map[pos].valid = 1; - register_map[pos].memory = is_memory_op(constraint); - register_map[pos].inout_pos = i; - register_map[pos].mode = constraint->mode; - } - - /* transform inputs */ - for(i = 0; i < arity; ++i) { - const ir_asm_constraint *constraint = &in_constraints[i]; - unsigned pos = constraint->pos; - ir_node *pred = get_irn_n(node, i); - ir_node *transformed; - - assert(pos < reg_map_size); - register_map[pos].use_input = 1; - register_map[pos].valid = 1; - register_map[pos].memory = is_memory_op(constraint); - register_map[pos].inout_pos = i; - register_map[pos].mode = constraint->mode; - - if(in[i] != NULL) - continue; - - transformed = be_transform_node(pred); - in[i] = transformed; - } - - new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity, - get_ASM_text(node), register_map); - - set_ia32_out_req_all(new_node, out_reg_reqs); - set_ia32_in_req_all(new_node, in_reg_reqs); - - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - return new_node; -} - /** * Transforms a FrameAddr into an ia32 Add. */ -static ir_node *gen_be_FrameAddr(ir_node *node) { +static ir_node *gen_be_FrameAddr(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = be_get_FrameAddr_frame(node); ir_node *new_op = be_transform_node(op); @@ -3807,7 +3438,7 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { ir_node *new_node; new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); - set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node)); + set_ia32_frame_ent(new_node, arch_get_frame_entity(node)); set_ia32_use_frame(new_node); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -3818,7 +3449,8 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { /** * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return. */ -static ir_node *gen_be_Return(ir_node *node) { +static ir_node *gen_be_Return(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *ret_val = get_irn_n(node, be_pos_Return_val); ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem); @@ -3911,7 +3543,6 @@ static ir_node *gen_be_Return(ir_node *node) { copy_node_attr(barrier, new_barrier); be_duplicate_deps(barrier, new_barrier); be_set_transformed_node(barrier, new_barrier); - mark_irn_visited(barrier); /* transform normally */ return be_duplicate_node(node); @@ -3925,7 +3556,8 @@ static ir_node *gen_be_AddSP(ir_node *node) ir_node *sz = get_irn_n(node, be_pos_AddSP_size); ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am); + return gen_binop(node, sp, sz, new_rd_ia32_SubSP, + match_am | match_immediate); } /** @@ -3936,59 +3568,27 @@ static ir_node *gen_be_SubSP(ir_node *node) ir_node *sz = get_irn_n(node, be_pos_SubSP_size); ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am); -} - -/** - * This function just sets the register for the Unknown node - * as this is not done during register allocation because Unknown - * is an "ignore" node. - */ -static ir_node *gen_Unknown(ir_node *node) { - ir_mode *mode = get_irn_mode(node); - - if (mode_is_float(mode)) { - if (ia32_cg_config.use_sse2) { - return ia32_new_Unknown_xmm(env_cg); - } else { - /* Unknown nodes are buggy in x87 simulator, use zero for now... */ - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_irg_start_block(irg); - ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block); - - /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet. - * So add a dependency to the initial frame pointer calculation to - * avoid that situation. - */ - add_irn_dep(ret, get_irg_frame(irg)); - return ret; - } - } else if (mode_needs_gp_reg(mode)) { - return ia32_new_Unknown_gp(env_cg); - } else { - panic("unsupported Unknown-Mode"); - } - return NULL; + return gen_binop(node, sp, sz, new_rd_ia32_AddSP, + match_am | match_immediate); } /** * Change some phi modes */ -static ir_node *gen_Phi(ir_node *node) { +static ir_node *gen_Phi(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); ir_node *phi; - if(mode_needs_gp_reg(mode)) { + if (ia32_mode_needs_gp_reg(mode)) { /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ mode = mode_Iu; - } else if(mode_is_float(mode)) { + } else if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { mode = mode_xmm; } else { @@ -4003,7 +3603,6 @@ static ir_node *gen_Phi(ir_node *node) { copy_node_attr(node, phi); be_duplicate_deps(node, phi); - be_set_transformed_node(node, phi); be_enqueue_preds(node); return phi; @@ -4016,7 +3615,6 @@ static ir_node *gen_IJmp(ir_node *node) { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *op = get_IJmp_target(node); ir_node *new_node; @@ -4029,8 +3627,9 @@ static ir_node *gen_IJmp(ir_node *node) match_am | match_8bit_am | match_16bit_am | match_immediate | match_8bit | match_16bit); - new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op2); + new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op2); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -4039,80 +3638,40 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } -typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ - ir_node *mem); - -typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ - ir_node *val, ir_node *mem); - /** - * Transforms a lowered Load into a "real" one. + * Transform a Bound node. */ -static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func) +static ir_node *gen_Bound(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *ptr = get_irn_n(node, 0); - ir_node *new_ptr = be_transform_node(ptr); - ir_node *mem = get_irn_n(node, 1); - ir_node *new_mem = be_transform_node(mem); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_ia32_ls_mode(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *new_op; + ir_node *new_node; + ir_node *lower = get_Bound_lower(node); + dbg_info *dbgi = get_irn_dbg_info(node); - new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem); - - set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node)); - set_ia32_am_scale(new_op, get_ia32_am_scale(node)); - set_ia32_am_sc(new_op, get_ia32_am_sc(node)); - if (is_ia32_am_sc_sign(node)) - set_ia32_am_sc_sign(new_op); - set_ia32_ls_mode(new_op, mode); - if (is_ia32_use_frame(node)) { - set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); - set_ia32_use_frame(new_op); - } + if (is_Const_0(lower)) { + /* typical case for Java */ + ir_node *sub, *res, *flags, *block; + ir_graph *irg = current_ir_graph; - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), + new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate); - return new_op; + block = get_nodes_block(res); + if (! is_Proj(res)) { + sub = res; + set_irn_mode(sub, mode_T); + res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res); + } else { + sub = get_Proj_pred(res); + } + flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + } else { + panic("generic Bound not supported in ia32 Backend"); + } + return new_node; } -/** - * Transforms a lowered Store into a "real" one. - */ -static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func) -{ - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *ptr = get_irn_n(node, 0); - ir_node *new_ptr = be_transform_node(ptr); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ir_node *mem = get_irn_n(node, 2); - ir_node *new_mem = be_transform_node(mem); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_ia32_ls_mode(node); - ir_node *new_op; - long am_offs; - - new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); - - am_offs = get_ia32_am_offs_int(node); - add_ia32_am_offs_int(new_op, am_offs); - - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_ls_mode(new_op, mode); - set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); - set_ia32_use_frame(new_op); - - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - - return new_op; -} static ir_node *gen_ia32_l_ShlDep(ir_node *node) { @@ -4139,14 +3698,15 @@ static ir_node *gen_ia32_l_SarDep(ir_node *node) match_immediate); } -static ir_node *gen_ia32_l_Add(ir_node *node) { +static ir_node *gen_ia32_l_Add(ir_node *node) +{ ir_node *left = get_irn_n(node, n_ia32_l_Add_left); ir_node *right = get_irn_n(node, n_ia32_l_Add_right); ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative | match_am | match_immediate | match_mode_neutral); - if(is_Proj(lowered)) { + if (is_Proj(lowered)) { lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Add(lowered)); @@ -4163,80 +3723,13 @@ static ir_node *gen_ia32_l_Adc(ir_node *node) match_mode_neutral); } -/** - * Transforms an ia32_l_vfild into a "real" ia32_vfild node - * - * @param node The node to transform - * @return the created ia32 vfild node - */ -static ir_node *gen_ia32_l_vfild(ir_node *node) { - return gen_lowered_Load(node, new_rd_ia32_vfild); -} - -/** - * Transforms an ia32_l_Load into a "real" ia32_Load node - * - * @param node The node to transform - * @return the created ia32 Load node - */ -static ir_node *gen_ia32_l_Load(ir_node *node) { - return gen_lowered_Load(node, new_rd_ia32_Load); -} - -/** - * Transforms an ia32_l_Store into a "real" ia32_Store node - * - * @param node The node to transform - * @return the created ia32 Store node - */ -static ir_node *gen_ia32_l_Store(ir_node *node) { - return gen_lowered_Store(node, new_rd_ia32_Store); -} - -/** - * Transforms a l_vfist into a "real" vfist node. - * - * @param node The node to transform - * @return the created ia32 vfist node - */ -static ir_node *gen_ia32_l_vfist(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *ptr = get_irn_n(node, 0); - ir_node *new_ptr = be_transform_node(ptr); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ir_node *mem = get_irn_n(node, 2); - ir_node *new_mem = be_transform_node(mem); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_ia32_ls_mode(node); - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); - ir_node *new_op; - long am_offs; - - new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, - new_val, trunc_mode); - - am_offs = get_ia32_am_offs_int(node); - add_ia32_am_offs_int(new_op, am_offs); - - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_ls_mode(new_op, mode); - set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); - set_ia32_use_frame(new_op); - - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - - return new_op; -} - /** * Transforms a l_MulS into a "real" MulS node. * * @return the created ia32 Mul node */ -static ir_node *gen_ia32_l_Mul(ir_node *node) { +static ir_node *gen_ia32_l_Mul(ir_node *node) +{ ir_node *left = get_binop_left(node); ir_node *right = get_binop_right(node); @@ -4249,21 +3742,23 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) { * * @return the created ia32 IMul1OP node */ -static ir_node *gen_ia32_l_IMul(ir_node *node) { - ir_node *left = get_binop_left(node); - ir_node *right = get_binop_right(node); +static ir_node *gen_ia32_l_IMul(ir_node *node) +{ + ir_node *left = get_binop_left(node); + ir_node *right = get_binop_right(node); return gen_binop(node, left, right, new_rd_ia32_IMul1OP, match_commutative | match_am | match_mode_neutral); } -static ir_node *gen_ia32_l_Sub(ir_node *node) { +static ir_node *gen_ia32_l_Sub(ir_node *node) +{ ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend); ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend); ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, match_am | match_immediate | match_mode_neutral); - if(is_Proj(lowered)) { + if (is_Proj(lowered)) { lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Sub(lowered)); @@ -4273,7 +3768,8 @@ static ir_node *gen_ia32_l_Sub(ir_node *node) { return lowered; } -static ir_node *gen_ia32_l_Sbb(ir_node *node) { +static ir_node *gen_ia32_l_Sbb(ir_node *node) +{ return gen_binop_flags(node, new_rd_ia32_Sbb, match_am | match_immediate | match_mode_neutral); } @@ -4299,7 +3795,9 @@ static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, /* the shift amount can be any mode that is bigger than 5 bits, since all * other bits are ignored anyway */ - while (is_Conv(count) && get_irn_n_edges(count) == 1) { + while (is_Conv(count) && + get_irn_n_edges(count) == 1 && + mode_is_int(get_irn_mode(count))) { assert(get_mode_size_bits(get_irn_mode(count)) >= 5); count = get_Conv_op(count); } @@ -4333,7 +3831,8 @@ static ir_node *gen_ia32_l_ShrD(ir_node *node) return gen_lowered_64bit_shifts(node, high, low, count); } -static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { +static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; @@ -4351,7 +3850,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { ir_node *store_low; ir_node *store_high; - if(!mode_is_signed(get_irn_mode(val_high))) { + if (!mode_is_signed(get_irn_mode(val_high))) { panic("unsigned long long -> float not supported yet (%+F)", node); } @@ -4387,7 +3886,8 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); } -static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { +static ir_node *gen_ia32_l_FloattoLL(ir_node *node) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; @@ -4397,30 +3897,28 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { ir_node *nomem = new_NoMem(); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + ir_node *fist, *mem; - ir_node *fist; - - /* do a fist */ - fist = new_rd_ia32_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, - trunc_mode); + mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist); SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_ls_mode(fist, mode_Ls); - return fist; + return mem; } /** * the BAD transformer. */ -static ir_node *bad_transform(ir_node *node) { - panic("No transform function for %+F available.\n", node); +static ir_node *bad_transform(ir_node *node) +{ + panic("No transform function for %+F available.", node); return NULL; } -static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { +static ir_node *gen_Proj_l_FloattoLL(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); @@ -4457,7 +3955,8 @@ static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { /** * Transform the Projs of an AddSP. */ -static ir_node *gen_Proj_be_AddSP(ir_node *node) { +static ir_node *gen_Proj_be_AddSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -4468,23 +3967,23 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) { if (proj == pn_be_AddSP_sp) { ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack); - arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; - } else if(proj == pn_be_AddSP_res) { + } else if (proj == pn_be_AddSP_res) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_addr); } else if (proj == pn_be_AddSP_M) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj->AddSP"); } /** * Transform the Projs of a SubSP. */ -static ir_node *gen_Proj_be_SubSP(ir_node *node) { +static ir_node *gen_Proj_be_SubSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -4495,20 +3994,20 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) { if (proj == pn_be_SubSP_sp) { ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj->SubSP"); } /** * Transform and renumber the Projs from a Load. */ -static ir_node *gen_Proj_Load(ir_node *node) { +static ir_node *gen_Proj_Load(ir_node *node) +{ ir_node *new_pred; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); @@ -4516,22 +4015,19 @@ static ir_node *gen_Proj_Load(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - /* loads might be part of source address mode matches, so we don't - transform the ProjMs yet (with the exception of loads whose result is - not used) + * transform the ProjMs yet (with the exception of loads whose result is + * not used) */ if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) { ir_node *res; - assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM - nodes is 1 */ /* this is needed, because sometimes we have loops that are only reachable through the ProjM */ be_enqueue_preds(node); /* do it in 2 steps, to silence firm verifier */ res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M); - set_Proj_proj(res, pn_ia32_Load_M); + set_Proj_proj(res, pn_ia32_mem); return res; } @@ -4603,20 +4099,19 @@ static ir_node *gen_Proj_Load(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj"); } /** * Transform and renumber the Projs from a DivMod like instruction. */ -static ir_node *gen_Proj_DivMod(ir_node *node) { +static ir_node *gen_Proj_DivMod(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); @@ -4671,23 +4166,22 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->DivMod"); } /** * Transform and renumber the Projs from a CopyB. */ -static ir_node *gen_Proj_CopyB(ir_node *node) { +static ir_node *gen_Proj_CopyB(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_CopyB_M_regular: if (is_ia32_CopyB_i(new_pred)) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M); @@ -4699,23 +4193,22 @@ static ir_node *gen_Proj_CopyB(ir_node *node) { break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->CopyB"); } /** * Transform and renumber the Projs from a Quot. */ -static ir_node *gen_Proj_Quot(ir_node *node) { +static ir_node *gen_Proj_Quot(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_Quot_M: if (is_ia32_xDiv(new_pred)) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M); @@ -4730,34 +4223,86 @@ static ir_node *gen_Proj_Quot(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; + case pn_Quot_X_regular: + case pn_Quot_X_except: default: break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->Quot"); } -/** - * Transform the Thread Local Storage Proj. - */ -static ir_node *gen_Proj_tls(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = NULL; - ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu); +static ir_node *gen_be_Call(ir_node *node) +{ + dbg_info *const dbgi = get_irn_dbg_info(node); + ir_graph *const irg = current_ir_graph; + ir_node *const src_block = get_nodes_block(node); + ir_node *const block = be_transform_node(src_block); + ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem); + ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp); + ir_node *const sp = be_transform_node(src_sp); + ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr); + ir_node *const noreg = ia32_new_NoReg_gp(env_cg); + ia32_address_mode_t am; + ia32_address_t *const addr = &am.addr; + ir_node * mem; + ir_node * call; + int i; + ir_node * fpcw; + ir_node * eax = noreg; + ir_node * ecx = noreg; + ir_node * edx = noreg; + unsigned const pop = be_Call_get_pop(node); + ir_type *const call_tp = be_Call_get_type(node); + + /* Run the x87 simulator if the call returns a float value */ + if (get_method_n_ress(call_tp) > 0) { + ir_type *const res_type = get_method_res_type(call_tp, 0); + ir_mode *const res_mode = get_type_mode(res_type); + + if (res_mode != NULL && mode_is_float(res_mode)) { + env_cg->do_x87_sim = 1; + } + } - return res; -} + /* We do not want be_Call direct calls */ + assert(be_Call_get_entity(node) == NULL); -static ir_node *gen_be_Call(ir_node *node) { - ir_node *res = be_duplicate_node(node); - be_node_add_flags(res, -1, arch_irn_flags_modify_flags); + match_arguments(&am, src_block, NULL, src_ptr, src_mem, + match_am | match_immediate); - return res; + i = get_irn_arity(node) - 1; + fpcw = be_transform_node(get_irn_n(node, i--)); + for (; i >= be_pos_Call_first_arg; --i) { + arch_register_req_t const *const req = arch_get_register_req(node, i); + ir_node *const reg_parm = be_transform_node(get_irn_n(node, i)); + + assert(req->type == arch_register_req_type_limited); + assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]); + + switch (*req->limited) { + case 1 << REG_EAX: assert(eax == noreg); eax = reg_parm; break; + case 1 << REG_ECX: assert(ecx == noreg); ecx = reg_parm; break; + case 1 << REG_EDX: assert(edx == noreg); edx = reg_parm; break; + default: panic("Invalid GP register for register parameter"); + } + } + + mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem); + call = new_rd_ia32_Call(dbgi, irg, block, addr->base, addr->index, mem, + am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); + set_am_attributes(call, &am); + call = fix_mem_proj(call, &am); + + if (get_irn_pinned(node) == op_pin_state_pinned) + set_irn_pinned(call, op_pin_state_pinned); + + SET_IA32_ORIG_NODE(call, ia32_get_old_node_name(env_cg, node)); + return call; } -static ir_node *gen_be_IncSP(ir_node *node) { +static ir_node *gen_be_IncSP(ir_node *node) +{ ir_node *res = be_duplicate_node(node); be_node_add_flags(res, -1, arch_irn_flags_modify_flags); @@ -4767,7 +4312,8 @@ static ir_node *gen_be_IncSP(ir_node *node) { /** * Transform the Projs from a be_Call. */ -static ir_node *gen_Proj_be_Call(ir_node *node) { +static ir_node *gen_Proj_be_Call(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *call = get_Proj_pred(node); ir_node *new_call = be_transform_node(call); @@ -4779,6 +4325,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { ir_mode *mode = get_irn_mode(node); ir_node *sse_load; const arch_register_class_t *cls; + ir_node *res; /* The following is kinda tricky: If we're using SSE, then we have to * move the result value of the call in floating point registers to an @@ -4797,9 +4344,9 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { call_res_pred = get_Proj_pred(call_res_new); } - if (call_res_pred == NULL || be_is_Call(call_res_pred)) { + if (call_res_pred == NULL || is_ia32_Call(call_res_pred)) { return new_rd_Proj(dbgi, irg, block, new_call, mode_M, - pn_be_Call_M_regular); + n_ia32_Call_mem); } else { assert(is_ia32_xLoad(call_res_pred)); return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, @@ -4842,11 +4389,51 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { /* transform call modes */ if (mode_is_data(mode)) { - cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1); + cls = arch_get_irn_reg_class(node, -1); mode = cls->mode; } - return new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + /* Map from be_Call to ia32_Call proj number */ + if (proj == pn_be_Call_sp) { + proj = pn_ia32_Call_stack; + } else if (proj == pn_be_Call_M_regular) { + proj = pn_ia32_Call_M; + } else { + arch_register_req_t const *const req = arch_get_register_req(node, BE_OUT_POS(proj)); + int const n_outs = get_ia32_n_res(new_call); + int i; + + assert(proj >= pn_be_Call_first_res); + assert(req->type == arch_register_req_type_limited); + + for (i = 0; i < n_outs; ++i) { + arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i); + + if (new_req->type != arch_register_req_type_limited || + new_req->cls != req->cls || + *new_req->limited != *req->limited) + continue; + + proj = i; + break; + } + assert(i < n_outs); + } + + res = new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + + /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ + switch (proj) { + case pn_ia32_Call_stack: + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + break; + + case pn_ia32_Call_fpcw: + arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]); + break; + } + + return res; } /** @@ -4859,71 +4446,125 @@ static ir_node *gen_Proj_Cmp(ir_node *node) node); } +/** + * Transform the Projs from a Bound. + */ +static ir_node *gen_Proj_Bound(ir_node *node) +{ + ir_node *new_node, *block; + ir_node *pred = get_Proj_pred(node); + + switch (get_Proj_proj(node)) { + case pn_Bound_M: + return be_transform_node(get_Bound_mem(pred)); + case pn_Bound_X_regular: + new_node = be_transform_node(pred); + block = get_nodes_block(new_node); + return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true); + case pn_Bound_X_except: + new_node = be_transform_node(pred); + block = get_nodes_block(new_node); + return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false); + case pn_Bound_res: + return be_transform_node(get_Bound_index(pred)); + default: + panic("unsupported Proj from Bound"); + } +} + +static ir_node *gen_Proj_ASM(ir_node *node) +{ + ir_node *pred; + ir_node *new_pred; + ir_node *block; + + if (get_irn_mode(node) != mode_M) + return be_duplicate_node(node); + + pred = get_Proj_pred(node); + new_pred = be_transform_node(pred); + block = get_nodes_block(new_pred); + return new_r_Proj(current_ir_graph, block, new_pred, mode_M, + get_ia32_n_res(new_pred) + 1); +} + /** * Transform and potentially renumber Proj nodes. */ -static ir_node *gen_Proj(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj(ir_node *node) +{ + ir_node *pred = get_Proj_pred(node); + long proj; - if (is_Store(pred)) { + switch (get_irn_opcode(pred)) { + case iro_Store: + proj = get_Proj_proj(node); if (proj == pn_Store_M) { return be_transform_node(pred); } else { - assert(0); - return new_r_Bad(irg); + panic("No idea how to transform proj->Store"); } - } else if (is_Load(pred)) { + case iro_Load: return gen_Proj_Load(node); - } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) { + case iro_ASM: + return gen_Proj_ASM(node); + case iro_Div: + case iro_Mod: + case iro_DivMod: return gen_Proj_DivMod(node); - } else if (is_CopyB(pred)) { + case iro_CopyB: return gen_Proj_CopyB(node); - } else if (is_Quot(pred)) { + case iro_Quot: return gen_Proj_Quot(node); - } else if (be_is_SubSP(pred)) { + case beo_SubSP: return gen_Proj_be_SubSP(node); - } else if (be_is_AddSP(pred)) { + case beo_AddSP: return gen_Proj_be_AddSP(node); - } else if (be_is_Call(pred)) { + case beo_Call: return gen_Proj_be_Call(node); - } else if (is_Cmp(pred)) { + case iro_Cmp: return gen_Proj_Cmp(node); - } else if (get_irn_op(pred) == op_Start) { - if (proj == pn_Start_X_initial_exec) { - ir_node *block = get_nodes_block(pred); - ir_node *jump; - - /* we exchange the ProjX with a jump */ - block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, irg, block); - return jump; - } - if (node == be_get_old_anchor(anchor_tls)) { - return gen_Proj_tls(node); + case iro_Bound: + return gen_Proj_Bound(node); + case iro_Start: + proj = get_Proj_proj(node); + switch (proj) { + case pn_Start_X_initial_exec: { + ir_node *block = get_nodes_block(pred); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + /* we exchange the ProjX with a jump */ + ir_node *jump = new_rd_Jmp(dbgi, current_ir_graph, new_block); + + return jump; + } + + case pn_Start_P_tls: + return gen_Proj_tls(node); } - } else if (is_ia32_l_FloattoLL(pred)) { - return gen_Proj_l_FloattoLL(node); + break; + + default: + if (is_ia32_l_FloattoLL(pred)) { + return gen_Proj_l_FloattoLL(node); #ifdef FIRM_EXT_GRS - } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization + } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization #else - } else { + } else { #endif - ir_node *new_pred = be_transform_node(pred); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - if (mode_needs_gp_reg(mode)) { - ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, - get_Proj_proj(node)); + ir_mode *mode = get_irn_mode(node); + if (ia32_mode_needs_gp_reg(mode)) { + ir_node *new_pred = be_transform_node(pred); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred, + mode_Iu, get_Proj_proj(node)); #ifdef DEBUG_libfirm - new_proj->node_nr = node->node_nr; + new_proj->node_nr = node->node_nr; #endif - return new_proj; + return new_proj; + } } } - return be_duplicate_node(node); } @@ -4950,7 +4591,7 @@ static void register_transformers(void) GEN(Shl); GEN(Shr); GEN(Shrs); - GEN(Rot); + GEN(Rotl); GEN(Quot); @@ -4970,11 +4611,11 @@ static void register_transformers(void) GEN(Cmp); GEN(ASM); GEN(CopyB); - BAD(Mux); - GEN(Psi); + GEN(Mux); GEN(Proj); GEN(Phi); GEN(IJmp); + GEN(Bound); /* transform ops from intrinsic lowering */ GEN(ia32_l_Add); @@ -4988,10 +4629,6 @@ static void register_transformers(void) GEN(ia32_l_ShrD); GEN(ia32_l_Sub); GEN(ia32_l_Sbb); - GEN(ia32_l_vfild); - GEN(ia32_l_Load); - GEN(ia32_l_vfist); - GEN(ia32_l_Store); GEN(ia32_l_LLtoFloat); GEN(ia32_l_FloattoLL); @@ -5034,8 +4671,9 @@ static void register_transformers(void) /** * Pre-transform all unknown and noreg nodes. */ -static void ia32_pretransform_node(void *arch_cg) { - ia32_code_gen_t *cg = arch_cg; +static void ia32_pretransform_node(void) +{ + ia32_code_gen_t *cg = env_cg; cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp); @@ -5047,8 +4685,8 @@ static void ia32_pretransform_node(void *arch_cg) { } /** - * Walker, checks if all ia32 nodes producing more than one result have - * its Projs, other wise creates new projs and keep them using a be_Keep node. + * Walker, checks if all ia32 nodes producing more than one result have their + * Projs, otherwise creates new Projs and keeps them using a be_Keep node. */ static void add_missing_keep_walker(ir_node *node, void *data) { @@ -5058,56 +4696,64 @@ static void add_missing_keep_walker(ir_node *node, void *data) ir_mode *mode = get_irn_mode(node); ir_node *last_keep; (void) data; - if(mode != mode_T) + if (mode != mode_T) return; - if(!is_ia32_irn(node)) + if (!is_ia32_irn(node)) return; n_outs = get_ia32_n_res(node); - if(n_outs <= 0) + if (n_outs <= 0) return; - if(is_ia32_SwitchJmp(node)) + if (is_ia32_SwitchJmp(node)) return; assert(n_outs < (int) sizeof(unsigned) * 8); foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); - int pn = get_Proj_proj(proj); + int pn; + + /* The node could be kept */ + if (is_End(proj)) + continue; - assert(get_irn_mode(proj) == mode_M || pn < n_outs); + if (get_irn_mode(proj) == mode_M) + continue; + + pn = get_Proj_proj(proj); + assert(pn < n_outs); found_projs |= 1 << pn; } /* are keeps missing? */ last_keep = NULL; - for(i = 0; i < n_outs; ++i) { + for (i = 0; i < n_outs; ++i) { ir_node *block; ir_node *in[1]; const arch_register_req_t *req; - const arch_register_class_t *class; + const arch_register_class_t *cls; - if(found_projs & (1 << i)) { + if (found_projs & (1 << i)) { continue; } - req = get_ia32_out_req(node, i); - class = req->cls; - if(class == NULL) { + req = get_ia32_out_req(node, i); + cls = req->cls; + if (cls == NULL) { continue; } - if(class == &ia32_reg_classes[CLASS_ia32_flags]) { + if (cls == &ia32_reg_classes[CLASS_ia32_flags]) { continue; } block = get_nodes_block(node); in[0] = new_r_Proj(current_ir_graph, block, node, - arch_register_class_mode(class), i); - if(last_keep != NULL) { - be_Keep_add_node(last_keep, class, in[0]); + arch_register_class_mode(cls), i); + if (last_keep != NULL) { + be_Keep_add_node(last_keep, cls, in[0]); } else { - last_keep = be_new_Keep(class, current_ir_graph, block, 1, in); - if(sched_is_scheduled(node)) { + last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in); + if (sched_is_scheduled(node)) { sched_add_after(node, last_keep); } } @@ -5125,17 +4771,17 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) } /* do the transformation */ -void ia32_transform_graph(ia32_code_gen_t *cg) { +void ia32_transform_graph(ia32_code_gen_t *cg) +{ int cse_last; - ir_graph *irg = cg->irg; register_transformers(); env_cg = cg; initial_fpcw = NULL; -BE_TIMER_PUSH(t_heights); - heights = heights_new(irg); -BE_TIMER_POP(t_heights); + BE_TIMER_PUSH(t_heights); + heights = heights_new(cg->irg); + BE_TIMER_POP(t_heights); ia32_calculate_non_address_mode_nodes(cg->birg); /* the transform phase is not safe for CSE (yet) because several nodes get @@ -5143,7 +4789,7 @@ BE_TIMER_POP(t_heights); cse_last = get_opt_cse(); set_opt_cse(0); - be_transform_graph(cg->birg, ia32_pretransform_node, cg); + be_transform_graph(cg->birg, ia32_pretransform_node); set_opt_cse(cse_last);