X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=ed2348d2a19ade195bd7b16526d938c6bd660d56;hb=191dc2e925e405104aed46be66ff7fadf24a37a6;hp=a929cbdda4dc4d46cdef38448ee64d5a95751e8d;hpb=c7185bafd120e50e4caeece50493e5a4e27251bb;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index a929cbdda..ed2348d2a 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -18,7 +18,7 @@ $comment_string = "/*"; # # => { # "op_flags" => "N|L|C|X|I|F|Y|H|c|K", -# "irn_flags" => "R|N|I" +# "irn_flags" => "R|N|I|S" # "arity" => "0|1|2|3 ... |variable|dynamic|any", # "state" => "floats|pinned|mem_pinned|exc_pinned", # "args" => [ @@ -57,6 +57,7 @@ $comment_string = "/*"; # R rematerializeable # N not spillable # I ignore for register allocation +# S modifies stack pointer # # state: state of the operation, OPTIONAL (default is "floats") # @@ -243,7 +244,7 @@ $comment_string = "/*"; "MulS" => { "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] }, + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */', "outs" => [ "EAX", "EDX", "M" ], }, @@ -276,7 +277,7 @@ $comment_string = "/*"; "Mulh" => { "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] }, + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */', "outs" => [ "EAX", "EDX", "M" ], }, @@ -380,12 +381,12 @@ $comment_string = "/*"; "DivMod" => { "op_flags" => "F|L", "state" => "exc_pinned", - "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] }, + "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] }, "attr" => "ia32_op_flavour_t dm_flav", "init_attr" => " attr->data.op_flav = dm_flav;", "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n", "emit" => -' if (mode_is_signed(get_irn_mode(n))) { +' if (mode_is_signed(get_ia32_res_mode(n))) { 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ } else { @@ -628,7 +629,6 @@ else { "Load" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", @@ -695,14 +695,17 @@ else { "emit" => ' if (get_ia32_id_cnst(n)) { if (get_ia32_immop_type(n) == ia32_ImmConst) { -. push %C /* Push(%A2) */ - } else { -. push OFFSET FLAT:%C /* Push(%A2) */ +4. push %C /* Push const on stack */ +} else { +4. push OFFSET FLAT:%C /* Push symconst on stack */ } } -else { -. push %S2 /* Push(%A2) */ +else if (get_ia32_op_type(n) == ia32_Normal) { +2. push %S2 /* Push(%A2) */ } +else { +2. push %ia32_emit_am /* Push memory to stack */ +}; ', "outs" => [ "stack", "M" ], }, @@ -710,7 +713,14 @@ else { "Pop" => { "comment" => "pop a gp register from the stack", "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] }, - "emit" => '. pop %D1 /* Pop -> %D1 */', + "emit" => ' +if (get_ia32_op_type(n) == ia32_Normal) { +2. pop %D1 /* Pop from stack into %D1 */ +} +else { +2. pop %ia32_emit_am /* Pop from stack into memory */ +} +', "outs" => [ "res", "stack", "M" ], }, @@ -728,6 +738,13 @@ else { "outs" => [ "frame", "stack", "M" ], }, +"AddSP" => { + "irn_flags" => "S|I", + "comment" => "allocate space on stack", + "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, + "outs" => [ "stack", "M" ], +}, + #-----------------------------------------------------------------------------# # _____ _____ ______ __ _ _ _ # # / ____/ ____| ____| / _| | | | | | # @@ -861,7 +878,6 @@ else { "xLoad" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", @@ -880,6 +896,16 @@ else { "outs" => [ "M" ], }, +"xStoreSimple" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "xmm", "none" ] }, + "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */', + "outs" => [ "M" ], +}, + "l_X87toSSE" => { "op_flags" => "L|F", "comment" => "construct: transfer a value from x87 FPU into a SSE register", @@ -894,13 +920,36 @@ else { "arity" => 3, }, +"GetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "store ST0 onto stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ] }, + "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */', + "outs" => [ "M" ], +}, + +"SetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "load ST0 from stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] }, + "emit" => '. fld %ia32_emit_am /* load ST0 from stack */', + "outs" => [ "res", "M" ], +}, + # CopyB "CopyB" => { "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", - "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] }, + "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] }, + "outs" => [ "DST", "SRC", "CNT", "M" ], }, "CopyB_i" => { @@ -908,7 +957,8 @@ else { "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] }, + "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] }, + "outs" => [ "DST", "SRC", "M" ], }, # Conversions @@ -1103,7 +1153,6 @@ else { "vfld" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", @@ -1123,7 +1172,6 @@ else { # Conversions "vfild" => { - "irn_flags" => "R", "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, @@ -1394,7 +1442,6 @@ else { "fild" => { "op_flags" => "R", - "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "reg_req" => { }, @@ -1421,6 +1468,7 @@ else { "fldz" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { }, @@ -1429,6 +1477,7 @@ else { "fld1" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { }, @@ -1437,6 +1486,7 @@ else { "fldpi" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load pi: Ld pi -> reg", "reg_req" => { }, @@ -1445,6 +1495,7 @@ else { "fldln2" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { }, @@ -1453,6 +1504,7 @@ else { "fldlg2" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { }, @@ -1461,6 +1513,7 @@ else { "fldl2t" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { }, @@ -1469,6 +1522,7 @@ else { "fldl2e" => { "op_flags" => "R", + "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ld e: Ld ld e -> reg", "reg_req" => { },