X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=dc0c49d8e41c5c6c1f9a6b28b54bef0bbae8a38d;hb=90f2e217df8deecb71f08af6bb28f9decd6795b0;hp=fbfe1ef222cdc4e0b319f5ead7d7e40e7fc0cffd;hpb=b0e09fe0aada2e5d9dc0299e969b3c93c1092d97;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index fbfe1ef22..dc0c49d8e 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -364,7 +364,7 @@ ProduceVal => { Add => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. add%M %binop', am => "full,binary", @@ -394,7 +394,7 @@ AddMem8Bit => { }, Adc => { - reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right", "eflags" ], emit => '. adc%M %binop', am => "full,binary", @@ -414,21 +414,6 @@ l_Adc => { ins => [ "left", "right", "eflags" ], }, -Add64Bit => { - irn_flags => "R", - arity => 4, - reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, - emit => ' -. movl %S0, %D0 -. movl %S1, %D1 -. addl %SI2, %D0 -. adcl %SI3, %D1 -', - outs => [ "low_res", "high_res" ], - units => [ "GP" ], - modified_flags => $status_flags -}, - Mul => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains @@ -453,7 +438,7 @@ l_Mul => { IMul => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. imul%M %binop', am => "source,binary", @@ -486,7 +471,7 @@ l_IMul => { And => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "full,binary", emit => '. and%M %binop', @@ -517,7 +502,7 @@ AndMem8Bit => { Or => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "full,binary", emit => '. or%M %binop', @@ -548,7 +533,7 @@ OrMem8Bit => { Xor => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "full,binary", emit => '. xor%M %binop', @@ -581,7 +566,7 @@ XorMem8Bit => { Sub => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "full,binary", emit => '. sub%M %binop', @@ -611,8 +596,8 @@ SubMem8Bit => { }, Sbb => { - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 !in_r5" ] }, - ins => [ "base", "index", "mem", "left", "right" ], + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right", "eflags" ], am => "full,binary", emit => '. sbb%M %binop', units => [ "GP" ], @@ -620,19 +605,14 @@ Sbb => { modified_flags => $status_flags }, -Sub64Bit => { - irn_flags => "R", - arity => 4, - reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, - emit => ' -. movl %S0, %D0 -. movl %S1, %D1 -. subl %SI2, %D0 -. sbbl %SI3, %D1 -', - outs => [ "low_res", "high_res" ], - units => [ "GP" ], - modified_flags => $status_flags +l_Sub => { + reg_req => { in => [ "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right" ], +}, + +l_Sbb => { + reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right", "eflags" ], }, IDiv => { @@ -1181,8 +1161,7 @@ FnstCW => { }, Cltd => { - # we should not rematrialize this node. It produces 2 results and has - # very strict constrains + # we should not rematrialize this node. It has very strict constraints. reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] }, ins => [ "val", "globbered" ], emit => '. cltd', @@ -1355,7 +1334,7 @@ xZero => { xAdd => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. add%XXM %binop', latency => 4, @@ -1365,7 +1344,7 @@ xAdd => { xMul => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. mul%XXM %binop', latency => 4, @@ -1375,7 +1354,7 @@ xMul => { xMax => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. max%XXM %binop', latency => 2, @@ -1385,7 +1364,7 @@ xMax => { xMin => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. min%XXM %binop', latency => 2, @@ -1395,7 +1374,7 @@ xMin => { xAnd => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. andp%XSD %binop', latency => 3, @@ -1405,7 +1384,7 @@ xAnd => { xOr => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. orp%XSD %binop', units => [ "SSE" ], @@ -1414,7 +1393,7 @@ xOr => { xXor => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. xorp%XSD %binop', latency => 3, @@ -1567,7 +1546,7 @@ CopyB_i => { Conv_I2I => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "in_r4", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] }, ins => [ "base", "index", "mem", "val" ], units => [ "GP" ], attr => "ir_mode *smaller_mode", @@ -1577,7 +1556,7 @@ Conv_I2I => { Conv_I2I8Bit => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "in_r4", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] }, ins => [ "base", "index", "mem", "val" ], units => [ "GP" ], attr => "ir_mode *smaller_mode",