X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=700479b9c00e7b2e319ab24a9da810dbc3464214;hb=1c89dc2a2c3cccd6e29fcfbf65248496db66ab92;hp=53fbc9fa9d030e541f1eff094379dce7a13d6e56;hpb=975ab11f67fae5636505d8ece87ea566997d70fb;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index 53fbc9fa9..700479b9c 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -34,16 +34,17 @@ #include "tv.h" #include "irgmod.h" #include "irgwalk.h" -#include "height.h" +#include "heights.h" #include "irbitset.h" #include "irprintf.h" +#include "irdump.h" #include "error.h" -#include "../be_t.h" -#include "../beabi.h" -#include "../benode.h" -#include "../besched.h" -#include "../bepeephole.h" +#include "be_t.h" +#include "beabi.h" +#include "benode.h" +#include "besched.h" +#include "bepeephole.h" #include "ia32_new_nodes.h" #include "ia32_optimize.h" @@ -52,21 +53,18 @@ #include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" -#include "ia32_util.h" #include "ia32_architecture.h" DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -static ia32_code_gen_t *cg; - -static void copy_mark(const ir_node *old, ir_node *new) +static void copy_mark(const ir_node *old, ir_node *newn) { if (is_ia32_is_reload(old)) - set_ia32_is_reload(new); + set_ia32_is_reload(newn); if (is_ia32_is_spill(old)) - set_ia32_is_spill(new); + set_ia32_is_spill(newn); if (is_ia32_is_remat(old)) - set_ia32_is_remat(new); + set_ia32_is_remat(newn); } typedef enum produces_flag_t { @@ -104,15 +102,15 @@ static produces_flag_t produces_test_flag(ir_node *node, int pn) case iro_ia32_ShlD: case iro_ia32_ShrD: - assert(n_ia32_ShlD_count == n_ia32_ShrD_count); + assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count); count = get_irn_n(node, n_ia32_ShlD_count); goto check_shift_amount; case iro_ia32_Shl: case iro_ia32_Shr: case iro_ia32_Sar: - assert(n_ia32_Shl_count == n_ia32_Shr_count - && n_ia32_Shl_count == n_ia32_Sar_count); + assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count + && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count); count = get_irn_n(node, n_ia32_Shl_count); check_shift_amount: /* when shift count is zero the flags are not affected, so we can only @@ -145,6 +143,7 @@ check_shift_amount: static void peephole_ia32_Cmp(ir_node *const node) { ir_node *right; + ir_graph *irg; ia32_immediate_attr_t const *imm; dbg_info *dbgi; ir_node *block; @@ -153,7 +152,6 @@ static void peephole_ia32_Cmp(ir_node *const node) ir_node *op; ia32_attr_t const *attr; int ins_permuted; - int cmp_unsigned; ir_node *test; arch_register_t const *reg; ir_edge_t const *edge; @@ -171,25 +169,25 @@ static void peephole_ia32_Cmp(ir_node *const node) return; dbgi = get_irn_dbg_info(node); + irg = get_irn_irg(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); + noreg = ia32_new_NoReg_gp(irg); nomem = get_irg_no_mem(current_ir_graph); op = get_irn_n(node, n_ia32_Cmp_left); - attr = get_irn_generic_attr(node); + attr = get_ia32_attr(node); ins_permuted = attr->data.ins_permuted; - cmp_unsigned = attr->data.cmp_unsigned; if (is_ia32_Cmp(node)) { test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem, - op, op, ins_permuted, cmp_unsigned); + op, op, ins_permuted); } else { test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem, - op, op, ins_permuted, cmp_unsigned); + op, op, ins_permuted); } set_ia32_ls_mode(test, get_ia32_ls_mode(node)); - reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags); - arch_irn_set_register(test, pn_ia32_Test_eflags, reg); + reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags); + arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg); foreach_out_edge_safe(node, edge, tmp) { ir_node *const user = get_edge_src_irn(edge); @@ -213,23 +211,25 @@ static void peephole_ia32_Test(ir_node *node) ir_node *left = get_irn_n(node, n_ia32_Test_left); ir_node *right = get_irn_n(node, n_ia32_Test_right); - assert(n_ia32_Test_left == n_ia32_Test8Bit_left - && n_ia32_Test_right == n_ia32_Test8Bit_right); + assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left + && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right); if (left == right) { /* we need a test for 0 */ ir_node *block = get_nodes_block(node); int pn = pn_ia32_res; + ir_node *op = left; ir_node *flags_proj; ir_mode *flags_mode; + ir_mode *op_mode; ir_node *schedpoint; const ir_edge_t *edge; if (get_nodes_block(left) != block) return; - if (is_Proj(left)) { - pn = get_Proj_proj(left); - left = get_Proj_pred(left); + if (is_Proj(op)) { + pn = get_Proj_proj(op); + op = get_Proj_pred(op); } /* walk schedule up and abort when we find left or some other node @@ -237,7 +237,7 @@ static void peephole_ia32_Test(ir_node *node) schedpoint = node; for (;;) { schedpoint = sched_prev(schedpoint); - if (schedpoint == left) + if (schedpoint == op) break; if (arch_irn_is(schedpoint, modify_flags)) return; @@ -247,29 +247,29 @@ static void peephole_ia32_Test(ir_node *node) /* make sure only Lg/Eq tests are used */ foreach_out_edge(node, edge) { - ir_node *user = get_edge_src_irn(edge); - int pnc = get_ia32_condcode(user); + ir_node *user = get_edge_src_irn(edge); + ia32_condition_code_t cc = get_ia32_condcode(user); - if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { + if (cc != ia32_cc_equal && cc != ia32_cc_not_equal) { return; } } - switch (produces_test_flag(left, pn)) { + switch (produces_test_flag(op, pn)) { case produces_flag_zero: break; case produces_flag_carry: foreach_out_edge(node, edge) { - ir_node *user = get_edge_src_irn(edge); - int pnc = get_ia32_condcode(user); + ir_node *user = get_edge_src_irn(edge); + ia32_condition_code_t cc = get_ia32_condcode(user); - switch (pnc) { - case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break; - case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break; - default: panic("unexpected pn"); + switch (cc) { + case ia32_cc_equal: cc = ia32_cc_above_equal; break; /* CF = 0 */ + case ia32_cc_not_equal: cc = ia32_cc_below; break; /* CF = 1 */ + default: panic("unexpected pn"); } - set_ia32_condcode(user, pnc); + set_ia32_condcode(user, cc); } break; @@ -277,22 +277,33 @@ static void peephole_ia32_Test(ir_node *node) return; } - if (get_irn_mode(left) != mode_T) { - set_irn_mode(left, mode_T); + op_mode = get_ia32_ls_mode(op); + if (op_mode == NULL) + op_mode = get_irn_mode(op); + + /* Make sure we operate on the same bit size */ + if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node))) + return; + + if (get_irn_mode(op) != mode_T) { + set_irn_mode(op, mode_T); /* If there are other users, reroute them to result proj */ - if (get_irn_n_edges(left) != 2) { - ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res); + if (get_irn_n_edges(op) != 2) { + ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res); - edges_reroute(left, res, current_ir_graph); + edges_reroute(op, res); /* Reattach the result proj to left */ - set_Proj_pred(res, left); + set_Proj_pred(res, op); } + } else { + if (get_irn_n_edges(left) == 2) + kill_node(left); } flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode; - flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags); - arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]); + flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags); + arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]); assert(get_irn_mode(node) != mode_T); @@ -307,21 +318,21 @@ static void peephole_ia32_Test(ir_node *node) offset = imm->offset; if (get_ia32_op_type(node) == ia32_AddrModeS) { - ia32_attr_t *const attr = get_irn_generic_attr(node); + ia32_attr_t *const attr = get_ia32_attr(node); if ((offset & 0xFFFFFF00) == 0) { /* attr->am_offs += 0; */ } else if ((offset & 0xFFFF00FF) == 0) { - ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 1; } else if ((offset & 0xFF00FFFF) == 0) { - ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 2; } else if ((offset & 0x00FFFFFF) == 0) { - ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 3; } else { return; @@ -329,10 +340,10 @@ static void peephole_ia32_Test(ir_node *node) } else if (offset < 256) { arch_register_t const* const reg = arch_get_irn_register(left); - if (reg != &ia32_gp_regs[REG_EAX] && - reg != &ia32_gp_regs[REG_EBX] && - reg != &ia32_gp_regs[REG_ECX] && - reg != &ia32_gp_regs[REG_EDX]) { + if (reg != &ia32_registers[REG_EAX] && + reg != &ia32_registers[REG_EBX] && + reg != &ia32_registers[REG_ECX] && + reg != &ia32_registers[REG_EDX]) { return; } } else { @@ -352,13 +363,11 @@ static void peephole_ia32_Test(ir_node *node) */ static void peephole_ia32_Return(ir_node *node) { - ir_node *block, *irn; + ir_node *irn; if (!ia32_cg_config.use_pad_return) return; - block = get_nodes_block(node); - /* check if this return is the first on the block */ sched_foreach_reverse_from(node, irn) { switch (get_irn_opcode(irn)) { @@ -367,7 +376,6 @@ static void peephole_ia32_Return(ir_node *node) continue; case iro_Start: case beo_Start: - case beo_Barrier: /* ignore no code generated */ continue; case beo_IncSP: @@ -387,7 +395,7 @@ static void peephole_ia32_Return(ir_node *node) } /* only optimize up to 48 stores behind IncSPs */ -#define MAXPUSH_OPTIMIZE 48 +#define MAXPUSH_OPTIMIZE 48 /** * Tries to create Push's from IncSP, Store combinations. @@ -477,19 +485,20 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* walk through the Stores and create Pushs for them */ block = get_nodes_block(irn); spmode = get_irn_mode(irn); - irg = cg->irg; + irg = get_irn_irg(irn); for (; i >= 0; --i) { const arch_register_t *spreg; ir_node *push; ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; - ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(irg); val = get_irn_n(store, n_ia32_unary_op); mem = get_irn_n(store, n_ia32_mem); spreg = arch_get_irn_register(curr_sp); - push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp); + push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, + mem, val, curr_sp); copy_mark(store, push); if (first_push == NULL) @@ -504,8 +513,22 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* create memory Proj */ mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M); + /* rewire Store Projs */ + foreach_out_edge_safe(store, edge, next) { + ir_node *proj = get_edge_src_irn(edge); + if (!is_Proj(proj)) + continue; + switch (get_Proj_proj(proj)) { + case pn_ia32_Store_M: + exchange(proj, mem_proj); + break; + default: + panic("unexpected Proj on Store->IncSp"); + } + } + /* use the memproj now */ - be_peephole_exchange(store, mem_proj); + be_peephole_exchange(store, push); inc_ofs -= 4; } @@ -524,6 +547,35 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) } #if 0 +/** + * Creates a Push instruction before the given schedule point. + * + * @param dbgi debug info + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value + */ +static ir_node *create_push(dbg_info *dbgi, ir_node *block, + ir_node *stack, ir_node *schedpoint) +{ + const arch_register_t *esp = &ia32_registers[REG_ESP]; + + ir_node *val = ia32_new_NoReg_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_graph *irg = get_irn_irg(block); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack); + sched_add_before(schedpoint, push); + + stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack); + arch_set_irn_register(stack, esp); + + return stack; +} + static void peephole_store_incsp(ir_node *store) { dbg_info *dbgi; @@ -551,8 +603,8 @@ static void peephole_store_incsp(ir_node *store) /* we have to be at offset 0 */ int my_offset = get_ia32_am_offs_int(store); if (my_offset != 0) { - /* TODO here: find out wether there is a store with offset 0 before - * us and wether we can move it down to our place */ + /* TODO here: find out whether there is a store with offset 0 before + * us and whether we can move it down to our place */ return; } ir_mode *ls_mode = get_ia32_ls_mode(store); @@ -614,7 +666,7 @@ static void peephole_store_incsp(ir_node *store) */ static inline int mode_needs_gp_reg(ir_mode *mode) { - if (mode == mode_fpcw) + if (mode == ia32_mode_fpcw) return 0; if (get_mode_size_bits(mode) > 32) return 0; @@ -628,11 +680,10 @@ static inline int mode_needs_gp_reg(ir_mode *mode) */ static void peephole_Load_IncSP_to_pop(ir_node *irn) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *esp = &ia32_registers[REG_ESP]; int i, maxslot, inc_ofs, ofs; ir_node *node, *pred_sp, *block; ir_node *loads[MAXPUSH_OPTIMIZE]; - ir_graph *irg; unsigned regmask = 0; unsigned copymask = ~0; @@ -714,7 +765,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) if (loads[loadslot] != NULL) break; - dreg = arch_irn_get_register(node, pn_ia32_Load_res); + dreg = arch_get_irn_register_out(node, pn_ia32_Load_res); if (regmask & (1 << dreg->index)) { /* this register is already used */ break; @@ -742,7 +793,6 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) /* create a new IncSP if needed */ block = get_nodes_block(irn); - irg = cg->irg; if (inc_ofs > 0) { pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); sched_add_before(irn, pred_sp); @@ -756,10 +806,10 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) const arch_register_t *reg; mem = get_irn_n(load, n_ia32_mem); - reg = arch_irn_get_register(load, pn_ia32_Load_res); + reg = arch_get_irn_register_out(load, pn_ia32_Load_res); pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp); - arch_irn_set_register(pop, pn_ia32_Load_res, reg); + arch_set_irn_register_out(pop, pn_ia32_Load_res, reg); copy_mark(load, pop); @@ -789,17 +839,18 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) /** * Find a free GP register if possible, else return NULL. */ -static const arch_register_t *get_free_gp_reg(void) +static const arch_register_t *get_free_gp_reg(ir_graph *irg) { + be_irg_t *birg = be_birg_from_irg(irg); int i; for (i = 0; i < N_ia32_gp_REGS; ++i) { - const arch_register_t *reg = &ia32_gp_regs[i]; - if (arch_register_type_is(reg, ignore)) + const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i]; + if (!rbitset_is_set(birg->allocatable_regs, reg->global_index)) continue; - if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL) - return &ia32_gp_regs[i]; + if (be_peephole_get_value(reg->global_index) == NULL) + return reg; } return NULL; @@ -820,13 +871,14 @@ static ir_node *create_pop(dbg_info *dbgi, ir_node *block, ir_node *stack, ir_node *schedpoint, const arch_register_t *reg) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *esp = &ia32_registers[REG_ESP]; + ir_graph *irg = get_irn_irg(block); ir_node *pop; ir_node *keep; ir_node *val; ir_node *in[1]; - pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack); + pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack); stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(stack, esp); @@ -842,40 +894,12 @@ static ir_node *create_pop(dbg_info *dbgi, ir_node *block, return stack; } -/** - * Creates a Push instruction before the given schedule point. - * - * @param dbgi debug info - * @param block the block - * @param stack the previous stack value - * @param schedpoint the new node is added before this node - * @param reg the register to pop - * - * @return the new stack value - */ -static ir_node *create_push(dbg_info *dbgi, ir_node *block, - ir_node *stack, ir_node *schedpoint) -{ - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; - - ir_node *val = ia32_new_NoReg_gp(cg); - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = new_NoMem(); - ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack); - sched_add_before(schedpoint, push); - - stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack); - arch_set_irn_register(stack, esp); - - return stack; -} - /** * Optimize an IncSp by replacing it with Push/Pop. */ static void peephole_be_IncSP(ir_node *node) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *esp = &ia32_registers[REG_ESP]; const arch_register_t *reg; dbg_info *dbgi; ir_node *block; @@ -904,7 +928,7 @@ static void peephole_be_IncSP(ir_node *node) if (offset < 0) { /* we need a free register for pop */ - reg = get_free_gp_reg(); + reg = get_free_gp_reg(get_irn_irg(node)); if (reg == NULL) return; @@ -921,10 +945,14 @@ static void peephole_be_IncSP(ir_node *node) dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - stack = create_push(dbgi, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); if (offset == +8) { - stack = create_push(dbgi, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); } } @@ -940,7 +968,7 @@ static void peephole_ia32_Const(ir_node *node) const arch_register_t *reg; ir_node *block; dbg_info *dbgi; - ir_node *xor; + ir_node *xorn; /* try to transform a mov 0, reg to xor reg reg */ if (attr->offset != 0 || attr->symconst != NULL) @@ -948,7 +976,7 @@ static void peephole_ia32_Const(ir_node *node) if (ia32_cg_config.use_mov_0) return; /* xor destroys the flags, so no-one must be using them */ - if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + if (be_peephole_get_value(REG_EFLAGS) != NULL) return; reg = arch_get_irn_register(node); @@ -957,18 +985,18 @@ static void peephole_ia32_Const(ir_node *node) /* create xor(produceval, produceval) */ block = get_nodes_block(node); dbgi = get_irn_dbg_info(node); - xor = new_bd_ia32_Xor0(dbgi, block); - arch_set_irn_register(xor, reg); + xorn = new_bd_ia32_Xor0(dbgi, block); + arch_set_irn_register(xorn, reg); - sched_add_before(node, xor); + sched_add_before(node, xorn); - copy_mark(node, xor); - be_peephole_exchange(node, xor); + copy_mark(node, xorn); + be_peephole_exchange(node, xorn); } -static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node) +static inline int is_noreg(const ir_node *node) { - return node == cg->noreg_gp; + return is_ia32_NoReg_GP(node); } ir_node *ia32_immediate_from_long(long val) @@ -977,7 +1005,7 @@ ir_node *ia32_immediate_from_long(long val) ir_node *start_block = get_irg_start_block(irg); ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val); - arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]); + arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]); return immediate; } @@ -994,7 +1022,7 @@ static ir_node *create_immediate_from_am(const ir_node *node) res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust, offset); - arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]); + arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]); return res; } @@ -1019,6 +1047,7 @@ static int is_am_minus_one(const ir_node *node) */ static void peephole_ia32_Lea(ir_node *node) { + ir_graph *irg; ir_node *base; ir_node *index; const arch_register_t *base_reg; @@ -1037,19 +1066,19 @@ static void peephole_ia32_Lea(ir_node *node) assert(is_ia32_Lea(node)); /* we can only do this if it is allowed to clobber the flags */ - if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + if (be_peephole_get_value(REG_EFLAGS) != NULL) return; base = get_irn_n(node, n_ia32_Lea_base); index = get_irn_n(node, n_ia32_Lea_index); - if (is_noreg(cg, base)) { + if (is_noreg(base)) { base = NULL; base_reg = NULL; } else { base_reg = arch_get_irn_register(base); } - if (is_noreg(cg, index)) { + if (is_noreg(index)) { index = NULL; index_reg = NULL; } else { @@ -1144,8 +1173,9 @@ make_add_immediate: make_add: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); - nomem = new_NoMem(); + irg = get_irn_irg(node); + noreg = ia32_new_NoReg_gp(irg); + nomem = get_irg_no_mem(irg); res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2); arch_set_irn_register(res, out_reg); set_ia32_commutative(res); @@ -1154,8 +1184,9 @@ make_add: make_shl: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); - nomem = new_NoMem(); + irg = get_irn_irg(node); + noreg = ia32_new_NoReg_gp(irg); + nomem = get_irg_no_mem(irg); res = new_bd_ia32_Shl(dbgi, block, op1, op2); arch_set_irn_register(res, out_reg); goto exchange; @@ -1186,21 +1217,21 @@ static void peephole_ia32_Imul_split(ir_node *imul) return; } /* we need a free register */ - reg = get_free_gp_reg(); + reg = get_free_gp_reg(get_irn_irg(imul)); if (reg == NULL) return; /* fine, we can rebuild it */ - res = turn_back_am(imul); + res = ia32_turn_back_am(imul); arch_set_irn_register(res, reg); } /** * Replace xorps r,r and xorpd r,r by pxor r,r */ -static void peephole_ia32_xZero(ir_node *xor) +static void peephole_ia32_xZero(ir_node *xorn) { - set_irn_op(xor, op_ia32_xPzero); + set_irn_op(xorn, op_ia32_xPzero); } /** @@ -1208,7 +1239,7 @@ static void peephole_ia32_xZero(ir_node *xor) */ static void peephole_ia32_Conv_I2I(ir_node *node) { - const arch_register_t *eax = &ia32_gp_regs[REG_EAX]; + const arch_register_t *eax = &ia32_registers[REG_EAX]; ir_mode *smaller_mode = get_ia32_ls_mode(node); ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val); dbg_info *dbgi; @@ -1218,7 +1249,7 @@ static void peephole_ia32_Conv_I2I(ir_node *node) if (get_mode_size_bits(smaller_mode) != 16 || !mode_is_signed(smaller_mode) || eax != arch_get_irn_register(val) || - eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res)) + eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res)) return; dbgi = get_irn_dbg_info(node); @@ -1239,10 +1270,8 @@ static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) } /* Perform peephole-optimizations. */ -void ia32_peephole_optimization(ia32_code_gen_t *new_cg) +void ia32_peephole_optimization(ir_graph *irg) { - cg = new_cg; - /* register peephole optimisations */ clear_irp_opcodes_generic_func(); register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); @@ -1260,12 +1289,12 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) if (ia32_cg_config.use_short_sex_eax) register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I); - be_peephole_opt(cg->birg); + be_peephole_opt(irg); } /** * Removes node from schedule if it is not used anymore. If irn is a mode_T node - * all it's Projs are removed as well. + * all its Projs are removed as well. * @param irn The irn to be removed from schedule */ static inline void try_kill(ir_node *node) @@ -1298,7 +1327,7 @@ static void optimize_conv_store(ir_node *node) if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) return; - assert(n_ia32_Store_val == n_ia32_Store8Bit_val); + assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val); pred_proj = get_irn_n(node, n_ia32_Store_val); if (is_Proj(pred_proj)) { pred = get_Proj_pred(pred_proj); @@ -1334,7 +1363,7 @@ static void optimize_load_conv(ir_node *node) if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) return; - assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val); pred = get_irn_n(node, n_ia32_Conv_I2I_val); if (!is_Proj(pred)) return; @@ -1381,7 +1410,7 @@ static void optimize_conv_conv(ir_node *node) if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) return; - assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val); pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val); if (is_Proj(pred_proj)) pred = get_Proj_pred(pred_proj); @@ -1410,8 +1439,9 @@ static void optimize_conv_conv(ir_node *node) /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { + const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node); set_irn_op(pred, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(pred, get_ia32_in_req_all(node)); + arch_set_irn_register_reqs_in(pred, reqs); } } else { /* we don't want to end up with 2 loads, so we better do nothing */ @@ -1424,8 +1454,9 @@ static void optimize_conv_conv(ir_node *node) /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { + const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node); set_irn_op(result_conv, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node)); + arch_set_irn_register_reqs_in(result_conv, reqs); } } } else { @@ -1468,12 +1499,9 @@ static void optimize_node(ir_node *node, void *env) /** * Performs conv and address mode optimization. */ -void ia32_optimize_graph(ia32_code_gen_t *cg) +void ia32_optimize_graph(ir_graph *irg) { - irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg); - - if (cg->dump) - be_dump(cg->irg, "-opt", dump_ir_block_graph_sched); + irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL); } void ia32_init_optimize(void)