X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=068e9db629662495d4c0447ea81af6a87b600944;hb=4d5c3365a58cba59993045a9e08e686d8ae079a7;hp=cc0fffda2a5e070841d36f9b326c760e23af3998;hpb=4d5066091dfdb819f254233f7ffd0b2158f922fe;p=libfirm

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index cc0fffda2..068e9db62 100644
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -1,13 +1,31 @@
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
 /**
  * Project:     libFIRM
  * File name:   ir/be/ia32/ia32_optimize.c
  * Purpose:     Implements several optimizations for IA32
  * Author:      Christian Wuerdig
  * CVS-ID:      $Id$
- * Copyright:   (c) 2006 Universität Karlsruhe
+ * Copyright:   (c) 2006 Universitaet Karlsruhe
  * Licence:     This file protected by GPL -  GNU GENERAL PUBLIC LICENSE.
  */
-
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -35,297 +53,36 @@
 #include "ia32_dbg_stat.h"
 #include "ia32_util.h"
 
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+
 #define AGGRESSIVE_AM
 
 typedef enum {
-	IA32_AM_CAND_NONE  = 0,
-	IA32_AM_CAND_LEFT  = 1,
-	IA32_AM_CAND_RIGHT = 2,
-	IA32_AM_CAND_BOTH  = 3
+	IA32_AM_CAND_NONE  = 0,  /**< no addressmode possible with irn inputs */
+	IA32_AM_CAND_LEFT  = 1,  /**< addressmode possible with left input */
+	IA32_AM_CAND_RIGHT = 2,  /**< addressmode possible with right input */
+	IA32_AM_CAND_BOTH  = 3   /**< addressmode possible with both inputs */
 } ia32_am_cand_t;
 
-#undef is_NoMem
-#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
-
 typedef int is_op_func_t(const ir_node *n);
 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
 
 /**
  * checks if a node represents the NOREG value
  */
-static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
-  be_abi_irg_t *babi = cg->birg->abi;
-	const arch_register_t *fp_noreg = USE_SSE2(cg) ?
-		&ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
-
-	return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
-	       (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
-}
-
-
-
-/*************************************************
- *   _____                _              _
- *  / ____|              | |            | |
- * | |     ___  _ __  ___| |_ __ _ _ __ | |_ ___
- * | |    / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
- * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
- *  \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
- *
- *************************************************/
-
-/**
- * creates a unique ident by adding a number to a tag
- *
- * @param tag   the tag string, must contain a %d if a number
- *              should be added
- */
-static ident *unique_id(const char *tag)
-{
-	static unsigned id = 0;
-	char str[256];
-
-	snprintf(str, sizeof(str), tag, ++id);
-	return new_id_from_str(str);
-}
-
-/**
- * Transforms a SymConst.
- *
- * @param mod     the debug module
- * @param block   the block the new node should belong to
- * @param node    the ir SymConst node
- * @param mode    mode of the SymConst
- * @return the created ia32 Const node
- */
-static ir_node *gen_SymConst(ia32_transform_env_t *env) {
-	dbg_info *dbg   = env->dbg;
-	ir_mode  *mode  = env->mode;
-	ir_graph *irg   = env->irg;
-	ir_node  *block = env->block;
-	ir_node  *cnst;
-
-	if (mode_is_float(mode)) {
-		FP_USED(env->cg);
-		if (USE_SSE2(env->cg))
-			cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
-		else
-			cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
-	}
-	else
-		cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
-
-	set_ia32_Const_attr(cnst, env->irn);
-
-	return cnst;
-}
-
-/**
- * Get a primitive type for a mode.
- */
-static ir_type *get_prim_type(pmap *types, ir_mode *mode)
-{
-	pmap_entry *e = pmap_find(types, mode);
-	ir_type *res;
-
-	if (! e) {
-		char buf[64];
-		snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
-		res = new_type_primitive(new_id_from_str(buf), mode);
-		pmap_insert(types, mode, res);
-	}
-	else
-		res = e->value;
-	return res;
-}
-
-/**
- * Get an entity that is initialized with a tarval
- */
-static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
-{
-	tarval *tv    = get_Const_tarval(cnst);
-	pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
-	entity *res;
-	ir_graph *rem;
-
-	if (! e) {
-		ir_mode *mode = get_irn_mode(cnst);
-		ir_type *tp = get_Const_type(cnst);
-		if (tp == firm_unknown_type)
-			tp = get_prim_type(cg->isa->types, mode);
-
-		res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
-
-		set_entity_ld_ident(res, get_entity_ident(res));
-		set_entity_visibility(res, visibility_local);
-		set_entity_variability(res, variability_constant);
-		set_entity_allocation(res, allocation_static);
-
-		 /* we create a new entity here: It's initialization must resist on the
-		    const code irg */
-		rem = current_ir_graph;
-		current_ir_graph = get_const_code_irg();
-		set_atomic_ent_value(res, new_Const_type(tv, tp));
-		current_ir_graph = rem;
-
-		pmap_insert(cg->isa->tv_ent, tv, res);
-	}
-	else
-		res = e->value;
-	return res;
+static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
+	return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
 }
 
-/**
- * Transforms a Const.
- *
- * @param mod     the debug module
- * @param block   the block the new node should belong to
- * @param node    the ir Const node
- * @param mode    mode of the Const
- * @return the created ia32 Const node
- */
-static ir_node *gen_Const(ia32_transform_env_t *env) {
-	ir_node *cnst, *load;
-	symconst_symbol sym;
-	ir_graph *irg   = env->irg;
-	ir_node  *block = env->block;
-	ir_node  *node  = env->irn;
-	dbg_info *dbg   = env->dbg;
-	ir_mode  *mode  = env->mode;
-
-	if (mode_is_float(mode)) {
-		FP_USED(env->cg);
-		if (! USE_SSE2(env->cg)) {
-			cnst_classify_t clss = classify_Const(node);
-
-			if (clss == CNST_NULL)
-				return new_rd_ia32_vfldz(dbg, irg, block, mode);
-			else if (clss == CNST_ONE)
-				return new_rd_ia32_vfld1(dbg, irg, block, mode);
-		}
-		sym.entity_p = get_entity_for_tv(env->cg, node);
-
-
-		cnst      = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
-		load      = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode);
-		load      = new_r_Proj(irg, block, load, mode, pn_Load_res);
-		env->irn  = cnst;
-		env->mode = mode_P;
-		cnst      = gen_SymConst(env);
-		set_Load_ptr(get_Proj_pred(load), cnst);
-		cnst      = load;
-	}
-	else {
-		cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
-		set_ia32_Const_attr(cnst, node);
-	}
-	return cnst;
-}
-
-/**
- * Transforms (all) Const's into ia32_Const and places them in the
- * block where they are used (or in the cfg-pred Block in case of Phi's).
- * Additionally all reference nodes are changed into mode_Is nodes.
- * NOTE: irn must be a firm constant!
- */
-static void ia32_transform_const(ir_node *irn, void *env) {
-	ia32_code_gen_t      *cg   = env;
-	ir_node              *cnst = NULL;
-	ia32_transform_env_t tenv;
-
-	tenv.cg   = cg;
-	tenv.irg  = cg->irg;
-	tenv.mode = get_irn_mode(irn);
-	tenv.dbg  = get_irn_dbg_info(irn);
-	tenv.irn  = irn;
-	DEBUG_ONLY(tenv.mod = cg->mod;)
-
-#if 1
-	/* place const either in the smallest dominator of all its users or the original block */
-	if (cg->opt & IA32_OPT_PLACECNST)
-		tenv.block = node_users_smallest_common_dominator(irn, 1);
-	else
-		tenv.block = get_nodes_block(irn);
-#else
-	{
-		ir_node *afterstart = NULL;
-		ir_node *startblock = get_irg_start_block(tenv.irg);
-		const ir_edge_t *edge;
-
-		foreach_block_succ(startblock, edge) {
-			ir_node *block = get_edge_src_irn(edge);
-			if (block != startblock) {
-				afterstart = block;
-				break;
-			}
-		}
-		assert(afterstart != NULL);
-		tenv.block = afterstart;
-	}
-#endif
-
-	switch (get_irn_opcode(irn)) {
-		case iro_Const:
-			cnst = gen_Const(&tenv);
-			break;
-		case iro_SymConst:
-			cnst = gen_SymConst(&tenv);
-			break;
-		default:
-			assert(0 && "Wrong usage of ia32_transform_const!");
-	}
-
-	assert(cnst && "Could not create ia32 Const");
-
-	/* set the new ia32 const */
-	exchange(irn, cnst);
-}
-
-/**
- * Transform all firm consts and assure, we visit each const only once.
- */
-static void ia32_place_consts_walker(ir_node *irn, void *env) {
-	ia32_code_gen_t *cg = env;
-
-	if(!is_Const(irn) && !is_SymConst(irn))
-		return;
-
-	ia32_transform_const(irn, cg);
-}
-
-/**
- * Replace reference modes with mode_Iu and preserve store value modes.
- */
-static void ia32_set_modes(ir_node *irn, void *env) {
-	if (is_Block(irn))
-		return;
-
-	/* transform all reference nodes into mode_Iu nodes */
-	if (mode_is_reference(get_irn_mode(irn))) {
-		set_irn_mode(irn, mode_Iu);
-	}
-}
-
-/**
- * Walks over the graph, transforms all firm consts into ia32 consts
- * and places them into the "best" block.
- * @param cg  The ia32 codegenerator object
- */
-static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
-	irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, cg);
-}
-
-/* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
 	/*
 		We need to transform the consts twice:
 		- the psi condition tree transformer needs existing constants to be ia32 constants
 		- the psi condition tree transformer inserts new firm constants which need to be transformed
 	*/
-	ia32_transform_all_firm_consts(cg);
-	irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
-	ia32_transform_all_firm_consts(cg);
+	//ia32_transform_all_firm_consts(cg);
+	irg_walk_graph(cg->irg, NULL, ia32_transform_psi_cond_tree, cg);
+	//ia32_transform_all_firm_consts(cg);
 }
 
 /********************************************************************************************************
@@ -343,8 +100,18 @@ void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
  * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
  */
 
-static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
-	return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
+static int ia32_const_equal(const ir_node *n1, const ir_node *n2) {
+	if(get_ia32_immop_type(n1) != get_ia32_immop_type(n2))
+		return 0;
+
+	if(get_ia32_immop_type(n1) == ia32_ImmConst) {
+		return get_ia32_Immop_tarval(n1) == get_ia32_Immop_tarval(n2);
+	} else if(get_ia32_immop_type(n1) == ia32_ImmSymConst) {
+		return get_ia32_Immop_symconst(n1) == get_ia32_Immop_symconst(n2);
+	}
+
+	assert(get_ia32_immop_type(n1) == ia32_ImmNone);
+	return 1;
 }
 
 /**
@@ -395,10 +162,10 @@ static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
 		}
 	}
 
-	if (same_args)
-		return ia32_cnst_compare(cand, irn);
+	if (!same_args)
+		return 0;
 
-	return 0;
+	return ia32_const_equal(cand, irn);
 }
 
 /**
@@ -412,14 +179,14 @@ static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
 	replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
 
 	if (replace) {
-		DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
+		DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
 
 		if (is_ia32_And(cand))
 			set_irn_op(irn, op_ia32_CJmpAM);
 		else
 			set_irn_op(irn, op_ia32_CJmp);
 
-		DB((cg->mod, LEVEL_1, "%+F\n", irn));
+		DB((dbg, LEVEL_1, "%+F\n", irn));
 	}
 }
 
@@ -431,20 +198,16 @@ static int is_CondJmp_cand(const ir_node *irn) {
  * Checks if the arguments of cand are the same of irn.
  */
 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
-	int i, n      = get_irn_arity(cand);
-	int same_args = 1;
+	int i, arity;
 
-	for (i = 0; i < n; i++) {
+	arity = get_irn_arity(cand);
+	for (i = 0; i < arity; i++) {
 		if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
-			same_args = 0;
-			break;
+			return 0;
 		}
 	}
 
-	if (same_args)
-		return ia32_cnst_compare(cand, irn);
-
-	return 0;
+	return ia32_const_equal(cand, irn);
 }
 
 /**
@@ -458,12 +221,12 @@ static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
 	replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
 
 	if (replace) {
-		DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
+		DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
 		DBG_OPT_CJMP(irn);
 
 		set_irn_op(irn, op_ia32_CJmpAM);
 
-		DB((cg->mod, LEVEL_1, "%+F\n", irn));
+		DB((dbg, LEVEL_1, "%+F\n", irn));
 	}
 }
 
@@ -498,10 +261,8 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 	 * attached to the node
 	 */
 	for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
-		const char *am_offs;
 		ir_node *mem;
-		int offset = -1;
-		int n;
+		int offset;
 		int storeslot;
 
 		// it has to be a store
@@ -520,18 +281,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 		if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
 			break;
 
-		am_offs = get_ia32_am_offs(node);
-		if(am_offs == NULL) {
-			offset = 0;
-		} else {
-			// the am_offs has to be of the form "+NUMBER"
-			if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') {
-				// we shouldn't have any cases in the compiler at the moment
-				// that produce something different from esp+XX
-				assert(0);
-				break;
-			}
-		}
+		offset = get_ia32_am_offs_int(node);
 
 		storeslot = offset / 4;
 		if(storeslot >= MAXPUSH_OPTIMIZE)
@@ -557,11 +307,11 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 	}
 
 	for( ; i >= 0; --i) {
-		const ir_edge_t *edge, *next;
 		const arch_register_t *spreg;
 		ir_node *push;
-		ir_node *val, *mem;
+		ir_node *val, *mem, *mem_proj;
 		ir_node *store = stores[i];
+		ir_node *noreg = ia32_new_NoReg_gp(cg);
 
 		if(store == NULL || is_Bad(store))
 			break;
@@ -571,10 +321,11 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 		spreg = arch_get_irn_register(cg->arch_env, curr_sp);
 
 		// create a push
-		push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem);
-		if(get_ia32_immop_type(store) != ia32_ImmNone) {
-			copy_ia32_Immop_attr(push, store);
-		}
+		push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
+
+		set_ia32_am_support(push, ia32_am_Source);
+		copy_ia32_Immop_attr(push, store);
+
 		sched_add_before(irn, push);
 
 		// create stackpointer proj
@@ -582,19 +333,14 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 		arch_set_irn_register(cg->arch_env, curr_sp, spreg);
 		sched_add_before(irn, curr_sp);
 
-		// rewire memprojs of the store
-		foreach_out_edge_safe(store, edge, next) {
-			ir_node *succ = get_edge_src_irn(edge);
+		// create memory proj
+		mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
+		sched_add_before(irn, mem_proj);
 
-			assert(is_Proj(succ) && get_Proj_proj(succ) == pn_ia32_Store_M);
-			set_irn_n(succ, 0, push);
-		}
+		// use the memproj now
+		exchange(store, mem_proj);
 
 		// we can remove the store now
-		set_irn_n(store, 0, new_Bad());
-		set_irn_n(store, 1, new_Bad());
-		set_irn_n(store, 2, new_Bad());
-		set_irn_n(store, 3, new_Bad());
 		sched_remove(store);
 
 		offset -= 4;
@@ -620,6 +366,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
 	}
 }
 
+#if 0
 /**
  * Tries to optimize two following IncSP.
  */
@@ -641,6 +388,7 @@ static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
 		sched_remove(prev);
 	}
 }
+#endif
 
 /**
  * Performs Peephole Optimizations.
@@ -659,8 +407,9 @@ static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
 	if (be_is_IncSP(irn)) {
 		// optimize_IncSP doesn't respect dependency edges yet...
 		//ia32_optimize_IncSP(irn, cg);
-		(void) ia32_optimize_IncSP;
-		ia32_create_Pushs(irn, cg);
+
+		if (cg->opt & IA32_OPT_PUSHARGS)
+			ia32_create_Pushs(irn, cg);
 	}
 }
 
@@ -706,11 +455,7 @@ static int ia32_get_irn_n_edges(const ir_node *irn) {
  * @return 1 if conditions are fulfilled, 0 otherwise
  */
 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
-	if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
-		return 1;
-	}
-
-	return 0;
+	return is_op_func(pred);
 }
 
 /**
@@ -736,42 +481,41 @@ static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
 }
 
 /**
- * Checks if irn is a candidate for address calculation.
+ * Checks if irn is a candidate for address calculation. We avoid transforming
+ * adds to leas if they have a load as pred, because then we can use AM mode
+ * for the add later.
  *
  * - none of the operand must be a Load  within the same block OR
  * - all Loads must have more than one user                    OR
- * - the irn has a frame entity (it's a former FrameAddr)
  *
  * @param block   The block the Loads must/mustnot be in
  * @param irn     The irn to check
  * return 1 if irn is a candidate, 0 otherwise
  */
-static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
-	ir_node *in, *left, *right;
-	int      n, is_cand = 1;
+static int is_addr_candidate(const ir_node *irn) {
+#ifndef AGGRESSIVE_AM
+	const ir_node *block = get_nodes_block(irn);
+	ir_node *left, *right;
+	int      n;
 
 	left  = get_irn_n(irn, 2);
 	right = get_irn_n(irn, 3);
 
-	in = left;
-
-#ifndef AGGRESSIVE_AM
-	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
-		n         = ia32_get_irn_n_edges(in);
-		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
+	if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
+		n         = ia32_get_irn_n_edges(left);
+		/* load with only one user: don't create LEA */
+		if(n == 1)
+			return 0;
 	}
 
-	in = right;
-
-	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
-		n         = ia32_get_irn_n_edges(in);
-		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
+	if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
+		n         = ia32_get_irn_n_edges(right);
+		if(n == 1)
+			return 0;
 	}
 #endif
 
-	is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
-
-	return is_cand;
+	return 1;
 }
 
 /**
@@ -790,29 +534,44 @@ static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
  */
 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
 	ir_node *in, *load, *other, *left, *right;
-	int      n, is_cand = 0, cand;
+	int      is_cand = 0, cand;
+	int arity;
 
 	if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
 		is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
 		return 0;
 
 	left  = get_irn_n(irn, 2);
-	right = get_irn_n(irn, 3);
+	arity = get_irn_arity(irn);
+	assert(arity == 5 || arity == 4);
+	if(arity == 5) {
+		/* binary op */
+		right = get_irn_n(irn, 3);
+	} else {
+		/* unary op */
+		right = left;
+	}
 
 	in = left;
 
 	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
 #ifndef AGGRESSIVE_AM
+		int n;
 		n         = ia32_get_irn_n_edges(in);
 		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+#else
+		is_cand   = 1;
 #endif
 
 		load  = get_Proj_pred(in);
 		other = right;
 
-		/* 8bit Loads are not supported, they cannot be used with every register */
-		if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
+		/* 8bit Loads are not supported (for binary ops),
+		 * they cannot be used with every register */
+		if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
+			assert(get_irn_arity(irn) == 5);
 			is_cand = 0;
+		}
 
 		/* If there is a data dependency of other irn from load: cannot use AM */
 		if (is_cand && get_nodes_block(other) == block) {
@@ -829,8 +588,11 @@ static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const i
 
 	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
 #ifndef AGGRESSIVE_AM
+		int n;
 		n         = ia32_get_irn_n_edges(in);
 		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+#else
+		is_cand = 1;
 #endif
 
 		load  = get_Proj_pred(in);
@@ -851,18 +613,6 @@ static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const i
 
 	cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
 
-	/* check some special cases */
-	if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
-		/* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
-		if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32)
-			cand = IA32_AM_CAND_NONE;
-	}
-	else if (is_ia32_Conv_I2I(irn)) {
-		/* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
-		if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn)))
-			cand = IA32_AM_CAND_NONE;
-	}
-
 	/* if the irn has a frame entity: we do not use address mode */
 	return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
 }
@@ -874,30 +624,24 @@ static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const i
 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
 									const ir_node *addr_b, const ir_node *addr_i)
 {
-	int     is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
-	entity *lent     = get_ia32_frame_ent(load);
-	entity *sent     = get_ia32_frame_ent(store);
-	ident  *lid      = get_ia32_am_sc(load);
-	ident  *sid      = get_ia32_am_sc(store);
-	char   *loffs    = get_ia32_am_offs(load);
-	char   *soffs    = get_ia32_am_offs(store);
-
-	/* are both entities set and equal? */
-	if (is_equal && (lent || sent))
-		is_equal = lent && sent && (lent == sent);
-
-	/* are address mode idents set and equal? */
-	if (is_equal && (lid || sid))
-		is_equal = lid && sid && (lid == sid);
-
-	/* are offsets set and equal */
-	if (is_equal && (loffs || soffs))
-		is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
-
-	/* are the load and the store of the same mode? */
-	is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
-
-	return is_equal;
+	if(get_irn_n(load, 0) != addr_b)
+		return 0;
+	if(get_irn_n(load, 1) != addr_i)
+		return 0;
+
+	if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
+		return 0;
+
+	if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
+		return 0;
+	if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
+		return 0;
+	if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
+		return 0;
+	if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
+		return 0;
+
+	return 1;
 }
 
 typedef enum _ia32_take_lea_attr {
@@ -916,11 +660,11 @@ typedef enum _ia32_take_lea_attr {
 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
 		int have_am_sc, ia32_code_gen_t *cg)
 {
-	entity  *irn_ent  = get_ia32_frame_ent(irn);
-	entity  *lea_ent  = get_ia32_frame_ent(lea);
-	int      ret_val  = 0;
-	int      is_noreg_base  = be_is_NoReg(cg, base);
-	int      is_noreg_index = be_is_NoReg(cg, index);
+	ir_entity *irn_ent  = get_ia32_frame_ent(irn);
+	ir_entity *lea_ent  = get_ia32_frame_ent(lea);
+	int        ret_val  = 0;
+	int        is_noreg_base  = be_is_NoReg(cg, base);
+	int        is_noreg_index = be_is_NoReg(cg, index);
 	ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
 
 	/* If the Add and the LEA both have a different frame entity set: keep */
@@ -1016,59 +760,60 @@ static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
 }
 
 /**
- * Removes irn from schedule if it was scheduled. If irn is a mode_T node
+ * Removes node from schedule if it is not used anymore. If irn is a mode_T node
  * all it's Projs are removed as well.
  * @param irn  The irn to be removed from schedule
  */
-static INLINE void try_remove_from_sched(ir_node *irn) {
+static INLINE void try_remove_from_sched(ir_node *node) {
 	int i, arity;
 
-	if (sched_is_scheduled(irn)) {
-		if (get_irn_mode(irn) == mode_T) {
-			const ir_edge_t *edge;
-			foreach_out_edge(irn, edge) {
-				ir_node *proj = get_edge_src_irn(edge);
-				if (sched_is_scheduled(proj)) {
-					set_irn_n(proj, 0, new_Bad());
-					sched_remove(proj);
-				}
-			}
+	if(get_irn_mode(node) == mode_T) {
+		const ir_edge_t *edge;
+		foreach_out_edge(node, edge) {
+			ir_node *proj = get_edge_src_irn(edge);
+			try_remove_from_sched(proj);
 		}
+	}
 
-		arity = get_irn_arity(irn);
-		for(i = 0; i < arity; ++i) {
-			set_irn_n(irn, i, new_Bad());
-		}
-		sched_remove(irn);
+	if(get_irn_n_edges(node) != 0)
+		return;
+
+	if (sched_is_scheduled(node)) {
+		sched_remove(node);
+	}
+
+	arity = get_irn_arity(node);
+	for(i = 0; i < arity; ++i) {
+		set_irn_n(node, i, new_Bad());
 	}
 }
 
 /**
  * Folds Add or Sub to LEA if possible
  */
-static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
+static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
 	ir_graph   *irg        = get_irn_irg(irn);
-	dbg_info   *dbg        = get_irn_dbg_info(irn);
+	dbg_info   *dbg_info   = get_irn_dbg_info(irn);
 	ir_node    *block      = get_nodes_block(irn);
 	ir_node    *res        = irn;
 	ir_node    *shift      = NULL;
 	ir_node    *lea_o      = NULL;
 	ir_node    *lea        = NULL;
-	char       *offs       = NULL;
-	const char *offs_cnst  = NULL;
-	char       *offs_lea   = NULL;
+	long        offs       = 0;
+	long        offs_cnst  = 0;
+	long        offs_lea   = 0;
 	int         scale      = 0;
 	int         isadd      = 0;
 	int         dolea      = 0;
 	int         have_am_sc = 0;
 	int         am_sc_sign = 0;
-	ident      *am_sc      = NULL;
-	entity     *lea_ent    = NULL;
+	ir_entity  *am_sc      = NULL;
+	ir_entity  *lea_ent    = NULL;
+	ir_node    *noreg      = ia32_new_NoReg_gp(cg);
 	ir_node    *left, *right, *temp;
 	ir_node    *base, *index;
 	int consumed_left_shift;
 	ia32_am_flavour_t am_flav;
-	DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
 
 	if (is_ia32_Add(irn))
 		isadd = 1;
@@ -1108,23 +853,25 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 
 	base    = left;
 	index   = noreg;
-	offs    = NULL;
+	offs    = 0;
 	scale   = 0;
 	am_flav = 0;
 
 	/* check for operation with immediate */
 	if (is_ia32_ImmConst(irn)) {
-		DBG((mod, LEVEL_1, "\tfound op with imm const"));
+		tarval *tv = get_ia32_Immop_tarval(irn);
 
-		offs_cnst = get_ia32_cnst(irn);
+		DBG((dbg, LEVEL_1, "\tfound op with imm const"));
+
+		offs_cnst = get_tarval_long(tv);
 		dolea     = 1;
 	}
-	else if (is_ia32_ImmSymConst(irn)) {
-		DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
+	else if (isadd && is_ia32_ImmSymConst(irn)) {
+		DBG((dbg, LEVEL_1, "\tfound op with imm symconst"));
 
 		have_am_sc = 1;
 		dolea      = 1;
-		am_sc      = get_ia32_id_cnst(irn);
+		am_sc      = get_ia32_Immop_symconst(irn);
 		am_sc_sign = is_ia32_am_sc_sign(irn);
 	}
 
@@ -1135,9 +882,9 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 	/* but we can only eat it up if there is no other symconst */
 	/* because the linker won't accept two symconsts           */
 	if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
-		DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
+		DBG((dbg, LEVEL_1, "\tgot op with LEA am_O"));
 
-		offs_lea   = get_ia32_am_offs(temp);
+		offs_lea   = get_ia32_am_offs_int(temp);
 		am_sc      = get_ia32_am_sc(temp);
 		am_sc_sign = is_ia32_am_sc_sign(temp);
 		have_am_sc = 1;
@@ -1156,7 +903,7 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 		dolea               = 1;
 		consumed_left_shift = -1;
 
-		DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
+		DBG((dbg, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
 
 		/* determine the operand which needs to be checked */
 		temp = left;
@@ -1167,21 +914,17 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 
 		/* check for SHL 1,2,3 */
 		if (pred_is_specific_node(temp, is_ia32_Shl)) {
-			temp  = get_Proj_pred(temp);
-			shift = temp;
 
-			if (get_ia32_Immop_tarval(temp)) {
-				scale = get_tarval_long(get_ia32_Immop_tarval(temp));
+			if (is_ia32_ImmConst(temp)) {
+				long shiftval = get_tarval_long(get_ia32_Immop_tarval(temp));
 
-				if (scale <= 3) {
+				if (shiftval <= 3) {
 					index               = get_irn_n(temp, 2);
 					consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
+					shift = temp;
+					scale = shiftval;
 
-					DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
-				}
-				else {
-					scale = 0;
-					shift = NULL;
+					DBG((dbg, LEVEL_1, "\tgot scaled index %+F\n", index));
 				}
 			}
 		}
@@ -1205,14 +948,14 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 		int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
 
 		if (take_attr == IA32_LEA_ATTR_NONE) {
-			DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
+			DBG((dbg, LEVEL_1, "\tleave old LEA, creating new one\n"));
 		}
 		else {
-			DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
+			DBG((dbg, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
 			lea = left; /* for statistics */
 
 			if (take_attr & IA32_LEA_ATTR_OFFS)
-				offs = get_ia32_am_offs(left);
+				offs = get_ia32_am_offs_int(left);
 
 			if (take_attr & IA32_LEA_ATTR_AMSC) {
 				am_sc      = get_ia32_am_sc(left);
@@ -1236,33 +979,22 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 
 	/* ok, we can create a new LEA */
 	if (dolea) {
-		res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
+		res = new_rd_ia32_Lea(dbg_info, irg, block, base, index);
 
 		/* add the old offset of a previous LEA */
-		if (offs) {
-			add_ia32_am_offs(res, offs);
-		}
+		add_ia32_am_offs_int(res, offs);
 
 		/* add the new offset */
 		if (isadd) {
-			if (offs_cnst) {
-				add_ia32_am_offs(res, offs_cnst);
-			}
-			if (offs_lea) {
-				add_ia32_am_offs(res, offs_lea);
-			}
-		}
-		else {
+			add_ia32_am_offs_int(res, offs_cnst);
+			add_ia32_am_offs_int(res, offs_lea);
+		} else {
 			/* either lea_O-cnst, -cnst or -lea_O  */
-			if (offs_cnst) {
-				if (offs_lea) {
-					add_ia32_am_offs(res, offs_lea);
-				}
-
-				sub_ia32_am_offs(res, offs_cnst);
-			}
-			else {
-				sub_ia32_am_offs(res, offs_lea);
+			if (offs_cnst != 0) {
+				add_ia32_am_offs_int(res, offs_lea);
+				add_ia32_am_offs_int(res, -offs_cnst);
+			} else {
+				add_ia32_am_offs_int(res, offs_lea);
 			}
 		}
 
@@ -1275,13 +1007,14 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 
 		/* copy the frame entity (could be set in case of Add */
 		/* which was a FrameAddr) */
-		if (lea_ent)
+		if (lea_ent != NULL) {
 			set_ia32_frame_ent(res, lea_ent);
-		else
-			set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
-
-		if (get_ia32_frame_ent(res))
 			set_ia32_use_frame(res);
+		} else {
+			set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
+			if(is_ia32_use_frame(irn))
+				set_ia32_use_frame(res);
+		}
 
 		/* set scale */
 		set_ia32_am_scale(res, scale);
@@ -1306,7 +1039,16 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 
 		SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
 
-		DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
+		DBG((dbg, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
+
+		assert(irn && "Couldn't find result proj");
+
+		/* get the result Proj of the Add/Sub */
+		try_add_to_sched(irn, res);
+
+		/* exchange the old op with the new LEA */
+		try_remove_from_sched(irn);
+		exchange(irn, res);
 
 		/* we will exchange it, report here before the Proj is created */
 		if (shift && lea && lea_o) {
@@ -1314,46 +1056,30 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
 			try_remove_from_sched(lea);
 			try_remove_from_sched(lea_o);
 			DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
-		}
-		else if (shift && lea) {
+		} else if (shift && lea) {
 			try_remove_from_sched(shift);
 			try_remove_from_sched(lea);
 			DBG_OPT_LEA3(irn, lea, shift, res);
-		}
-		else if (shift && lea_o) {
+		} else if (shift && lea_o) {
 			try_remove_from_sched(shift);
 			try_remove_from_sched(lea_o);
 			DBG_OPT_LEA3(irn, lea_o, shift, res);
-		}
-		else if (lea && lea_o) {
+		} else if (lea && lea_o) {
 			try_remove_from_sched(lea);
 			try_remove_from_sched(lea_o);
 			DBG_OPT_LEA3(irn, lea_o, lea, res);
-		}
-		else if (shift) {
+		} else if (shift) {
 			try_remove_from_sched(shift);
 			DBG_OPT_LEA2(irn, shift, res);
-		}
-		else if (lea) {
+		} else if (lea) {
 			try_remove_from_sched(lea);
 			DBG_OPT_LEA2(irn, lea, res);
-		}
-		else if (lea_o) {
+		} else if (lea_o) {
 			try_remove_from_sched(lea_o);
 			DBG_OPT_LEA2(irn, lea_o, res);
-		}
-		else
+		} else {
 			DBG_OPT_LEA1(irn, res);
-
-		/* get the result Proj of the Add/Sub */
-		try_add_to_sched(irn, res);
-		try_remove_from_sched(irn);
-		irn = ia32_get_res_proj(irn);
-
-		assert(irn && "Couldn't find result proj");
-
-		/* exchange the old op with the new LEA */
-		exchange(irn, res);
+		}
 	}
 
 	return res;
@@ -1366,19 +1092,19 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
  * @param lea The LEA
  */
 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
-	entity *irn_ent = get_ia32_frame_ent(irn);
-	entity *lea_ent = get_ia32_frame_ent(lea);
+	ir_entity *irn_ent = get_ia32_frame_ent(irn);
+	ir_entity *lea_ent = get_ia32_frame_ent(lea);
 
 	/* If the irn and the LEA both have a different frame entity set: do not merge */
-	if (irn_ent && lea_ent && (irn_ent != lea_ent))
+	if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
 		return;
-	else if (! irn_ent && lea_ent) {
+	else if (irn_ent == NULL && lea_ent != NULL) {
 		set_ia32_frame_ent(irn, lea_ent);
 		set_ia32_use_frame(irn);
 	}
 
 	/* get the AM attributes from the LEA */
-	add_ia32_am_offs(irn, get_ia32_am_offs(lea));
+	add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
 	set_ia32_am_scale(irn, get_ia32_am_scale(lea));
 	set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
 
@@ -1428,7 +1154,6 @@ static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, i
  */
 static void optimize_lea(ir_node *irn, void *env) {
 	ia32_code_gen_t *cg  = env;
-	ir_node         *block, *noreg_gp, *left, *right;
 
 	if (! is_ia32_irn(irn))
 		return;
@@ -1441,31 +1166,23 @@ static void optimize_lea(ir_node *irn, void *env) {
 	/* - Add (l == LEA with ia32_am_O, r)  -> LEA [base + offset]  */
 	/* - Add (l, r) -> LEA [base + index * scale]                  */
 	/*              with scale > 1 iff l/r == shl (1,2,3)          */
-
 	if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
-		left     = get_irn_n(irn, 2);
-		right    = get_irn_n(irn, 3);
-		block    = get_nodes_block(irn);
-		noreg_gp = ia32_new_NoReg_gp(cg);
-
-	    /* Do not try to create a LEA if one of the operands is a Load. */
-		/* check is irn is a candidate for address calculation */
-		if (is_addr_candidate(block, irn)) {
-			ir_node *res;
-
-			DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
-			res = fold_addr(cg, irn, noreg_gp);
-
-			if (res != irn)
-				DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
-			else
-				DB((cg->mod, LEVEL_1, "not transformed\n"));
-		}
-	}
-	else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
+		ir_node *res;
+
+		if(!is_addr_candidate(irn))
+			return;
+
+		DBG((dbg, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
+		res = fold_addr(cg, irn);
+
+		if (res != irn)
+			DB((dbg, LEVEL_1, "transformed into %+F\n", res));
+		else
+			DB((dbg, LEVEL_1, "not transformed\n"));
+	} else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
 		/* - Load  -> LEA into Load  } TODO: If the LEA is used by more than one Load/Store */
 		/* - Store -> LEA into Store }       it might be better to keep the LEA             */
-		left = get_irn_n(irn, 0);
+		ir_node *left = get_irn_n(irn, 0);
 
 		if (is_ia32_Lea(left)) {
 			const ir_edge_t *edge, *ne;
@@ -1476,7 +1193,7 @@ static void optimize_lea(ir_node *irn, void *env) {
 				src = get_edge_src_irn(edge);
 
 				if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
-					DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
+					DBG((dbg, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
 					if (! is_ia32_got_lea(src))
 						merge_loadstore_lea(src, left);
 					set_ia32_got_lea(src);
@@ -1486,7 +1203,6 @@ static void optimize_lea(ir_node *irn, void *env) {
 	}
 }
 
-
 /**
  * Checks for address mode patterns and performs the
  * necessary transformations.
@@ -1495,23 +1211,27 @@ static void optimize_lea(ir_node *irn, void *env) {
 static void optimize_am(ir_node *irn, void *env) {
 	ia32_am_opt_env_t *am_opt_env = env;
 	ia32_code_gen_t   *cg         = am_opt_env->cg;
+	ir_graph          *irg        = get_irn_irg(irn);
 	heights_t         *h          = am_opt_env->h;
-	ir_node           *block, *noreg_gp, *noreg_fp;
-	ir_node           *left, *right;
+	ir_node           *block, *left, *right;
 	ir_node           *store, *load, *mem_proj;
-	ir_node           *succ, *addr_b, *addr_i;
-	int               check_am_src          = 0;
+	ir_node           *addr_b, *addr_i;
 	int               need_exchange_on_fail = 0;
-	DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
+	ia32_am_type_t    am_support;
+	ia32_am_cand_t cand;
+	ia32_am_cand_t orig_cand;
+	int               dest_possible;
+	int               source_possible;
 
-	if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+	if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+		return;
+	if (is_ia32_Lea(irn))
 		return;
 
-	block    = get_nodes_block(irn);
-	noreg_gp = ia32_new_NoReg_gp(cg);
-	noreg_fp = ia32_new_NoReg_fp(cg);
+	am_support = get_ia32_am_support(irn);
+	block = get_nodes_block(irn);
 
-	DBG((mod, LEVEL_1, "checking for AM\n"));
+	DBG((dbg, LEVEL_1, "checking for AM\n"));
 
 	/* fold following patterns:                                                         */
 	/* - op -> Load into AMop with am_Source                                            */
@@ -1526,234 +1246,241 @@ static void optimize_am(ir_node *irn, void *env) {
 	/*     - the Load is only used by this op AND                                       */
 	/*     - the Load and Store are in the same block AND                               */
 	/*     - nobody else uses the result of the op                                      */
+	if (get_ia32_am_support(irn) == ia32_am_None)
+		return;
 
-	if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) {
-		ia32_am_cand_t cand      = is_am_candidate(cg, h, block, irn);
-		ia32_am_cand_t orig_cand = cand;
-
-		/* cand == 1: load is left;   cand == 2: load is right; */
-
-		if (cand == IA32_AM_CAND_NONE)
-			return;
+	cand = is_am_candidate(cg, h, block, irn);
+	if (cand == IA32_AM_CAND_NONE)
+		return;
 
-		DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
+	orig_cand = cand;
+	DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
 
-		left  = get_irn_n(irn, 2);
-		if (get_irn_arity(irn) == 4) {
-			/* it's an "unary" operation */
-			right = left;
-		}
-		else {
-			right = get_irn_n(irn, 3);
-		}
+	left  = get_irn_n(irn, 2);
+	if (get_irn_arity(irn) == 4) {
+		/* it's an "unary" operation */
+		right = left;
+		assert(cand == IA32_AM_CAND_BOTH);
+	} else {
+		right = get_irn_n(irn, 3);
+	}
 
-		/* normalize commutative ops */
-		if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) {
+	dest_possible = am_support & ia32_am_Dest ? 1 : 0;
+	source_possible = am_support & ia32_am_Source ? 1 : 0;
 
-			/* Assure that left operand is always a Load if there is one    */
-			/* because non-commutative ops can only use Dest AM if the left */
-			/* operand is a load, so we only need to check left operand.    */
+	if (dest_possible) {
+		addr_b = NULL;
+		addr_i = NULL;
+		store  = NULL;
 
-			exchange_left_right(irn, &left, &right, 3, 2);
-			need_exchange_on_fail = 1;
+		/* we should only have 1 user which is a store */
+		if (ia32_get_irn_n_edges(irn) == 1) {
+			ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
 
-			/* now: load is right */
-			cand = IA32_AM_CAND_LEFT;
+			if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
+				store  = succ;
+				addr_b = get_irn_n(store, 0);
+				addr_i = get_irn_n(store, 1);
+			}
 		}
 
-		/* check for Store -> op -> Load */
+		if (store == NULL) {
+			dest_possible = 0;
+		}
+	}
 
-		/* Store -> op -> Load optimization is only possible if supported by op */
-		/* and if right operand is a Load                                       */
-		if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_LEFT))
-		{
-			/* An address mode capable op always has a result Proj.                  */
-			/* If this Proj is used by more than one other node, we don't need to    */
-			/* check further, otherwise we check for Store and remember the address, */
-			/* the Store points to. */
-
-			succ = ia32_get_res_proj(irn);
-			assert(succ && "Couldn't find result proj");
-
-			addr_b = NULL;
-			addr_i = NULL;
-			store  = NULL;
-
-			/* now check for users and Store */
-			if (ia32_get_irn_n_edges(succ) == 1) {
-				succ = get_edge_src_irn(get_irn_out_edge_first(succ));
-
-				if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
-					store  = succ;
-					addr_b = get_irn_n(store, 0);
-					addr_i = get_irn_n(store, 1);
-				}
+	if (dest_possible) {
+		/* normalize nodes, we need the interesting load on the left side */
+		if (cand & IA32_AM_CAND_RIGHT) {
+			load = get_Proj_pred(right);
+			if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
+				exchange_left_right(irn, &left, &right, 3, 2);
+				need_exchange_on_fail ^= 1;
+				if (cand == IA32_AM_CAND_RIGHT)
+					cand = IA32_AM_CAND_LEFT;
 			}
+		}
+	}
 
-			if (store) {
-				/* we found a Store as single user: Now check for Load */
-
-				/* skip the Proj for easier access */
-				load = is_Proj(right) ? (is_ia32_Load(get_Proj_pred(right)) ? get_Proj_pred(right) : NULL) : NULL;
-
-				/* Extra check for commutative ops with two Loads */
-				/* -> put the interesting Load left               */
-				if (load && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) {
-					if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
-						/* We exchange left and right, so it's easier to kill     */
-						/* the correct Load later and to handle unary operations. */
-						exchange_left_right(irn, &left, &right, 3, 2);
-						need_exchange_on_fail ^= 1;
-					}
-				}
+	if (dest_possible) {
+		if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
+			load = get_Proj_pred(left);
 
-				/* skip the Proj for easier access */
-				load = get_Proj_pred(left);
-
-				/* Compare Load and Store address */
-				if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
-					/* Left Load is from same address, so we can */
-					/* disconnect the Load and Store here        */
-
-					/* set new base, index and attributes */
-					set_irn_n(irn, 0, addr_b);
-					set_irn_n(irn, 1, addr_i);
-					add_ia32_am_offs(irn, get_ia32_am_offs(load));
-					set_ia32_am_scale(irn, get_ia32_am_scale(load));
-					set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
-					set_ia32_op_type(irn, ia32_AddrModeD);
-					set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
-					set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
-
-					set_ia32_am_sc(irn, get_ia32_am_sc(load));
-					if (is_ia32_am_sc_sign(load))
-						set_ia32_am_sc_sign(irn);
-
-					if (is_ia32_use_frame(load))
-						set_ia32_use_frame(irn);
-
-					/* connect to Load memory and disconnect Load */
-					if (get_irn_arity(irn) == 5) {
-						/* binary AMop */
-						set_irn_n(irn, 4, get_irn_n(load, 2));
-						set_irn_n(irn, 2, noreg_gp);
-					}
-					else {
-						/* unary AMop */
-						set_irn_n(irn, 3, get_irn_n(load, 2));
-						set_irn_n(irn, 2, noreg_gp);
-					}
-
-					/* connect the memory Proj of the Store to the op */
-					mem_proj = ia32_get_proj_for_mode(store, mode_M);
-					set_Proj_pred(mem_proj, irn);
-					set_Proj_proj(mem_proj, 1);
-
-					/* clear remat flag */
-					set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
-
-					try_remove_from_sched(load);
-					try_remove_from_sched(store);
-					DBG_OPT_AM_D(load, store, irn);
-
-					DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
-
-					need_exchange_on_fail = 0;
-				}
-			} /* if (store) */
-			else if (get_ia32_am_support(irn) & ia32_am_Source) {
-				/* There was no store, check if we still can optimize for source address mode */
-				check_am_src = 1;
+#ifndef AGGRESSIVE_AM
+			/* we have to be the only user of the load */
+			if (get_irn_n_edges(left) > 1) {
+				dest_possible = 0;
 			}
-		} /* if (support AM Dest) */
-		else if (get_ia32_am_support(irn) & ia32_am_Source) {
-			/* op doesn't support am AM Dest -> check for AM Source */
-			check_am_src = 1;
+#endif
+		} else {
+			dest_possible = 0;
 		}
+	}
 
-		/* was exchanged but optimize failed: exchange back */
-		if (need_exchange_on_fail) {
-			exchange_left_right(irn, &left, &right, 3, 2);
-			cand = orig_cand;
+	if (dest_possible) {
+		/* the store has to use the loads memory or the same memory
+		 * as the load */
+		ir_node *loadmem = get_irn_n(load, 2);
+		ir_node *storemem = get_irn_n(store, 3);
+		assert(get_irn_mode(loadmem) == mode_M);
+		assert(get_irn_mode(storemem) == mode_M);
+		if(storemem != loadmem || !is_Proj(storemem)
+				|| get_Proj_pred(storemem) != load) {
+			dest_possible = 0;
 		}
+	}
 
-		need_exchange_on_fail = 0;
-
-		/* normalize commutative ops */
-		if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) {
+	if (dest_possible) {
+		/* Compare Load and Store address */
+		if (!load_store_addr_is_equal(load, store, addr_b, addr_i))
+			dest_possible = 0;
+	}
 
-			/* Assure that right operand is always a Load if there is one  */
-			/* because non-commutative ops can only use Source AM if the   */
-			/* right operand is a Load, so we only need to check the right */
-			/* operand afterwards.                                         */
+	if (dest_possible) {
+		/* all conditions fullfilled, do the transformation */
+		assert(cand & IA32_AM_CAND_LEFT);
+
+		/* set new base, index and attributes */
+		set_irn_n(irn, 0, addr_b);
+		set_irn_n(irn, 1, addr_i);
+		add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
+		set_ia32_am_scale(irn, get_ia32_am_scale(load));
+		set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
+		set_ia32_op_type(irn, ia32_AddrModeD);
+		set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
+		set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
+
+		set_ia32_am_sc(irn, get_ia32_am_sc(load));
+		if (is_ia32_am_sc_sign(load))
+			set_ia32_am_sc_sign(irn);
+
+		/* connect to Load memory and disconnect Load */
+		if (get_irn_arity(irn) == 5) {
+			/* binary AMop */
+			set_irn_n(irn, 4, get_irn_n(load, 2));
+			set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
+		} else {
+			/* unary AMop */
+			set_irn_n(irn, 3, get_irn_n(load, 2));
+			set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
+		}
 
-			exchange_left_right(irn, &left, &right, 3, 2);
-			need_exchange_on_fail = 1;
+		set_irn_mode(irn, mode_M);
 
-			/* now: load is left */
-			cand = IA32_AM_CAND_RIGHT;
-		}
+		/* connect the memory Proj of the Store to the op */
+		mem_proj = ia32_get_proj_for_mode(store, mode_M);
+		edges_reroute(mem_proj, irn, irg);
 
-		/* optimize op -> Load iff Load is only used by this op    */
-		/* and right operand is a Load which only used by this irn */
-		if (check_am_src                &&
-			(cand & IA32_AM_CAND_RIGHT) &&
-			(get_irn_arity(irn) == 5)   &&
-			(ia32_get_irn_n_edges(right) == 1))
-		{
-			right = get_Proj_pred(right);
+		/* clear remat flag */
+		set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
 
-			addr_b = get_irn_n(right, 0);
-			addr_i = get_irn_n(right, 1);
+		try_remove_from_sched(load);
+		try_remove_from_sched(store);
+		DBG_OPT_AM_D(load, store, irn);
 
-			/* set new base, index and attributes */
-			set_irn_n(irn, 0, addr_b);
-			set_irn_n(irn, 1, addr_i);
-			add_ia32_am_offs(irn, get_ia32_am_offs(right));
-			set_ia32_am_scale(irn, get_ia32_am_scale(right));
-			set_ia32_am_flavour(irn, get_ia32_am_flavour(right));
-			set_ia32_op_type(irn, ia32_AddrModeS);
-			set_ia32_frame_ent(irn, get_ia32_frame_ent(right));
-			set_ia32_ls_mode(irn, get_ia32_ls_mode(right));
+		DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
+		need_exchange_on_fail = 0;
+		source_possible = 0;
+	}
 
-			set_ia32_am_sc(irn, get_ia32_am_sc(right));
-			if (is_ia32_am_sc_sign(right))
-				set_ia32_am_sc_sign(irn);
+	if (source_possible) {
+		/* normalize ops, we need the load on the right */
+		if(cand == IA32_AM_CAND_LEFT) {
+			if(node_is_ia32_comm(irn)) {
+				exchange_left_right(irn, &left, &right, 3, 2);
+				need_exchange_on_fail ^= 1;
+				cand = IA32_AM_CAND_RIGHT;
+			} else {
+				source_possible = 0;
+			}
+		}
+	}
 
-			/* clear remat flag */
-			set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+	if (source_possible) {
+		/* all conditions fullfilled, do transform */
+		assert(cand & IA32_AM_CAND_RIGHT);
+		load = get_Proj_pred(right);
 
-			if (is_ia32_use_frame(right))
-				set_ia32_use_frame(irn);
+		if(get_irn_n_edges(load) > 1) {
+			source_possible = 0;
+		}
+	}
 
-			/* connect to Load memory */
-			set_irn_n(irn, 4, get_irn_n(right, 2));
+	if (source_possible) {
+		addr_b = get_irn_n(load, 0);
+		addr_i = get_irn_n(load, 1);
+
+		/* set new base, index and attributes */
+		set_irn_n(irn, 0, addr_b);
+		set_irn_n(irn, 1, addr_i);
+		add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
+		set_ia32_am_scale(irn, get_ia32_am_scale(load));
+		set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
+		set_ia32_op_type(irn, ia32_AddrModeS);
+		set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
+		set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
+
+		set_ia32_am_sc(irn, get_ia32_am_sc(load));
+		if (is_ia32_am_sc_sign(load))
+			set_ia32_am_sc_sign(irn);
+
+		/* clear remat flag */
+		set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+
+		if (is_ia32_use_frame(load)) {
+			if(get_ia32_frame_ent(load) == NULL) {
+				set_ia32_need_stackent(irn);
+			}
+			set_ia32_use_frame(irn);
+		}
 
-			/* this is only needed for Compares, but currently ALL nodes
-			 * have this attribute :-) */
-			set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
+		/* connect to Load memory and disconnect Load */
+		if (get_irn_arity(irn) == 5) {
+			/* binary AMop */
+			set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
+			set_irn_n(irn, 4, get_irn_n(load, 2));
+		} else {
+			assert(get_irn_arity(irn) == 4);
+			/* unary AMop */
+			set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
+			set_irn_n(irn, 3, get_irn_n(load, 2));
+		}
 
-			/* disconnect from Load */
-			set_irn_n(irn, 3, noreg_gp);
+		DBG_OPT_AM_S(load, irn);
 
-			DBG_OPT_AM_S(right, irn);
+		/* If Load has a memory Proj, connect it to the op */
+		mem_proj = ia32_get_proj_for_mode(load, mode_M);
+		if (mem_proj != NULL) {
+			ir_node *res_proj;
+			ir_mode *mode = get_irn_mode(irn);
 
-			/* If Load has a memory Proj, connect it to the op */
-			mem_proj = ia32_get_proj_for_mode(right, mode_M);
-			if (mem_proj) {
-				set_Proj_pred(mem_proj, irn);
-				set_Proj_proj(mem_proj, 1);
-			}
+			res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
+			                       get_nodes_block(irn), new_Unknown(mode_T),
+								   mode, 0);
+			set_irn_mode(irn, mode_T);
+			edges_reroute(irn, res_proj, irg);
+			set_Proj_pred(res_proj, irn);
 
-			try_remove_from_sched(right);
+			set_Proj_pred(mem_proj, irn);
+			set_Proj_proj(mem_proj, 1);
 
-			DB((mod, LEVEL_1, "merged with %+F into source AM\n", right));
+			if(sched_is_scheduled(irn)) {
+				sched_add_after(irn, res_proj);
+				sched_add_after(irn, mem_proj);
+			}
 		}
-		else {
-			/* was exchanged but optimize failed: exchange back */
-			if (need_exchange_on_fail)
-				exchange_left_right(irn, &left, &right, 3, 2);
+
+		if(get_irn_n_edges(load) == 0) {
+			try_remove_from_sched(load);
 		}
+		need_exchange_on_fail = 0;
+
+		DB((dbg, LEVEL_1, "merged with %+F into source AM\n", load));
+	}
+
+	/* was exchanged but optimize failed: exchange back */
+	if (need_exchange_on_fail) {
+		exchange_left_right(irn, &left, &right, 3, 2);
 	}
 }
 
@@ -1763,8 +1490,10 @@ static void optimize_am(ir_node *irn, void *env) {
 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
 	/* if we are supposed to do AM or LEA optimization: recalculate edges */
 	if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
+#if 0
 		edges_deactivate(cg->irg);
 		edges_activate(cg->irg);
+#endif
 	}
 	else {
 		/* no optimizations at all */
@@ -1782,6 +1511,13 @@ void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
 	if (cg->dump)
 		be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
 
+	/* hack for now, so these don't get created during optimize, because then
+	 * they will be unknown to the heights module
+	 */
+	ia32_new_NoReg_gp(cg);
+	ia32_new_NoReg_fp(cg);
+	ia32_new_NoReg_vfp(cg);
+
 	if (cg->opt & IA32_OPT_DOAM) {
 		/* we need height information for am optimization */
 		heights_t *h = heights_new(cg->irg);
@@ -1795,3 +1531,8 @@ void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
 		heights_free(h);
 	}
 }
+
+void ia32_init_optimize(void)
+{
+	FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");
+}