X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fbearch_ia32_t.h;h=eb3206e4e71fbb43e635bebe68586b3b8d9da171;hb=90f2e217df8deecb71f08af6bb28f9decd6795b0;hp=947eba143d7889c343d33421ad79d78c49d729bb;hpb=c0acb5cc9a2967e31e2b2961a98831d674cea3b8;p=libfirm diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h index 947eba143..eb3206e4e 100644 --- a/ir/be/ia32/bearch_ia32_t.h +++ b/ir/be/ia32/bearch_ia32_t.h @@ -1,5 +1,30 @@ -#ifndef _BEARCH_IA32_T_H_ -#define _BEARCH_IA32_T_H_ +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +/** + * @file + * @brief This is the main ia32 firm backend driver. + * @author Christian Wuerdig + * @version $Id$ + */ +#ifndef FIRM_BE_IA32_BEARCH_IA32_T_H +#define FIRM_BE_IA32_BEARCH_IA32_T_H #include "firm_config.h" @@ -9,35 +34,38 @@ #include "set.h" #include "pdeq.h" -#include "../be.h" +#include "be.h" #include "../bemachine.h" #include "../beemitter.h" #ifdef NDEBUG #define SET_IA32_ORIG_NODE(n, o) -#else +#else /* ! NDEBUG */ #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o); #endif /* NDEBUG */ /* some typedefs */ +typedef enum ia32_optimize_t ia32_optimize_t; +typedef enum cpu_support cpu_support; +typedef enum fp_support fp_support; /** * Bitmask for the backend optimization settings. */ -typedef enum _ia32_optimize_t { +enum ia32_optimize_t { IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */ IA32_OPT_DOAM = 2, /**< do address mode optimizations */ IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */ IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */ IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */ IA32_OPT_PUSHARGS = 32, /**< create pushs for function argument passing */ -} ia32_optimize_t; +}; /** * Architectures. Clustered for easier macro implementation, * do not change. */ -typedef enum cpu_support { +enum cpu_support { arch_i386, /**< i386 */ arch_i486, /**< i486 */ arch_pentium, /**< Pentium */ @@ -52,7 +80,8 @@ typedef enum cpu_support { arch_athlon, /**< Athlon */ arch_athlon_64, /**< Athlon64 */ arch_opteron, /**< Opteron */ -} cpu_support; + arch_generic /**< generic */ +}; /** checks for l <= x <= h */ #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l))) @@ -63,18 +92,21 @@ typedef enum cpu_support { /** returns true if it's AMD architecture */ #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron) +/** return true if it's a Athlon/Opteron */ +#define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron) + +/** return true if the CPU has MMX support */ +#define ARCH_MMX(x) _IN_RANGE((x), arch_pentium_mmx, arch_opteron) + #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \ _IN_RANGE((x), arch_athlon, arch_opteron)) /** floating point support */ -typedef enum fp_support { +enum fp_support { fp_none, /**< no floating point instructions are used */ fp_x87, /**< use x87 instructions */ fp_sse2 /**< use SSE2 instructions */ -} fp_support; - -/** Sets the used flag to the current floating point architecture. */ -#define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind) +}; /** Returns non-zero if the current floating point architecture is SSE2. */ #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2) @@ -82,15 +114,15 @@ typedef enum fp_support { /** Returns non-zero if the current floating point architecture is x87. */ #define USE_x87(cg) ((cg)->fp_kind == fp_x87) -/** Sets the flag to enforce x87 simulation. */ -#define FORCE_x87(cg) ((cg)->force_sim = 1) - -typedef struct _ia32_isa_t ia32_isa_t; +typedef struct ia32_isa_t ia32_isa_t; +typedef struct ia32_code_gen_t ia32_code_gen_t; +typedef struct ia32_irn_ops_t ia32_irn_ops_t; +typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t; /** * IA32 code generator */ -typedef struct _ia32_code_gen_t { +struct ia32_code_gen_t { const arch_code_generator_if_t *impl; /**< implementation */ ir_graph *irg; /**< current irg */ const arch_env_t *arch_env; /**< the arch env */ @@ -102,8 +134,7 @@ typedef struct _ia32_code_gen_t { int arch; /**< instruction architecture */ int opt_arch; /**< optimize for architecture */ char fp_kind; /**< floating point kind */ - char used_fp; /**< which floating point unit used in this graph */ - char force_sim; /**< set to 1 if x87 simulation should be enforced */ + char do_x87_sim; /**< set to 1 if x87 simulation should be enforced */ char dump; /**< set to 1 if graphs should be dumped */ ir_node *unknown_gp; /**< unique Unknown_GP node */ ir_node *unknown_vfp; /**< unique Unknown_VFP node */ @@ -115,16 +146,16 @@ typedef struct _ia32_code_gen_t { ir_node *fpu_trunc_mode; /**< truncate fpu mode */ struct obstack *obst; -} ia32_code_gen_t; +}; /** * IA32 ISA object */ -struct _ia32_isa_t { +struct ia32_isa_t { arch_isa_t arch_isa; /**< must be derived from arch_isa_t */ - be_emit_env_t emit; pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */ pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */ + pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */ pmap *types; /**< A map of modes to primitive types */ pmap *tv_ent; /**< A map of entities that store const tarvals */ ia32_optimize_t opt; /**< contains optimization information */ @@ -138,18 +169,33 @@ struct _ia32_isa_t { #endif /* NDEBUG */ }; -typedef struct _ia32_irn_ops_t { +struct ia32_irn_ops_t { const arch_irn_ops_if_t *impl; ia32_code_gen_t *cg; -} ia32_irn_ops_t; +}; + +/** + * A helper type collecting needed info for IA32 intrinsic lowering. + */ +struct ia32_intrinsic_env_t { + ia32_isa_t *isa; /**< the isa object */ + ir_graph *irg; /**< the irg, these entities belong to */ + ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */ + ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */ + ir_entity *ll_d_conv; /**< entity for converts ll -> d */ + ir_entity *d_ll_conv; /**< entity for converts d -> ll */ + ir_entity *divdi3; /**< entity for __divdi3 library call */ + ir_entity *moddi3; /**< entity for __moddi3 library call */ + ir_entity *udivdi3; /**< entity for __udivdi3 library call */ + ir_entity *umoddi3; /**< entity for __umoddi3 library call */ + tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */ +}; + +/** The mode for the floating point control word. */ +extern ir_mode *mode_fpcw; -typedef struct _ia32_intrinsic_env_t { - ir_graph *irg; /**< the irg, these entities belong to */ - ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */ - ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */ - ir_entity *ll_d_conv; /**< entity for converts ll -> d */ - ir_entity *d_ll_conv; /**< entity for converts d -> ll */ -} ia32_intrinsic_env_t; +/** The current code generator. */ +extern ia32_code_gen_t *ia32_current_cg; /** * Returns the unique per irg GP NoReg node. @@ -172,7 +218,7 @@ ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg); ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg); /** - * Returns the uniqure per irg FPU truncation mode node. + * Returns the unique per irg FPU truncation mode node. */ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg); @@ -201,4 +247,4 @@ ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op, const ir_mode *imode, const ir_mode *omode, void *context); -#endif /* _BEARCH_IA32_T_H_ */ +#endif