X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=2df148316d5d3e81c42512d8958968171a310ffb;hb=acd5a14eb9f5db22065b247996de0bcb0961522b;hp=edd26f187f89e959c40ff4eab00bda076049009b;hpb=ae3dce180880d08e70c80c9216dabf586f9547d9;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index edd26f187..2df148316 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -633,7 +633,7 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
 			cost += 150;
 	}
 	else if (is_ia32_CopyB_i(irn)) {
-		int size = get_ia32_pncode(irn);
+		int size = get_ia32_copyb_size(irn);
 		cost     = 20 + (int)ceil((4/3) * size);
 		if (ARCH_INTEL(ops->cg->arch))
 			cost += 150;
@@ -906,7 +906,7 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = {
 	ia32_perform_memory_operand,
 };
 
-ia32_irn_ops_t ia32_irn_ops = {
+static ia32_irn_ops_t ia32_irn_ops = {
 	&ia32_irn_ops_if,
 	NULL
 };
@@ -925,9 +925,14 @@ ia32_irn_ops_t ia32_irn_ops = {
  **************************************************/
 
 static void ia32_before_abi(void *self) {
+	lower_mode_b_config_t lower_mode_b_config = {
+		mode_Iu,  /* lowered mode */
+		mode_Bu,  /* prefered mode for set */
+		0,        /* don't lower direct compares */
+	};
 	ia32_code_gen_t *cg = self;
 
-	ir_lower_mode_b(cg->irg, mode_Iu, 0);
+	ir_lower_mode_b(cg->irg, &lower_mode_b_config);
 	if(cg->dump)
 		be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
 }
@@ -1346,7 +1351,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
 	}
 
 	in[0] = sp;
-	keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+	keep  = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
 	sched_add_before(node, keep);
 
 	// exchange memprojs
@@ -1416,12 +1421,13 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
 		           || is_ia32_vfld(node)) {
-			const ir_mode *mode = get_ia32_ls_mode(node);
-			int align = 4;
+			const ir_mode *mode  = get_ia32_ls_mode(node);
+			int            align = 4;
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else if(is_ia32_FldCW(node)) {
-			const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
-			int align = 4;
+			/* although 2 byte would be enough 4 byte performs best */
+			const ir_mode *mode  = mode_Iu;
+			int            align = 4;
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else {
 #ifndef NDEBUG
@@ -1808,7 +1814,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 
 	n = get_method_n_params(method_type);
 	for (i = regnum = 0; i < n; i++) {
-		const ir_mode         *mode;
+		ir_mode               *mode;
 		const arch_register_t *reg = NULL;
 
 		tp   = get_method_param_type(method_type, i);
@@ -1820,7 +1826,11 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 			be_abi_call_param_reg(abi, i, reg);
 			++regnum;
 		} else {
-			be_abi_call_param_stack(abi, i, 4, 0, 0);
+			/* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
+			 * movl has a shorter opcode than mov[sz][bw]l */
+			ir_mode *load_mode = mode;
+			if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
+			be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
 		}
 	}
 
@@ -2316,6 +2326,7 @@ static const lc_opt_table_entry_t ia32_options[] = {
 	LC_OPT_ENT_ENUM_INT("opt",       "optimize for instruction architecture", &opt_arch_var),
 	LC_OPT_ENT_ENUM_INT("fpunit",    "select the floating point unit", &fp_unit_var),
 	LC_OPT_ENT_NEGBIT("nooptcc",  "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
+	LC_OPT_ENT_BIT("unsafe_floatconv",  "do unsage floating point controlword optimisations", &ia32_isa_template.opt, IA32_OPT_UNSAFE_FLOATCONV),
 	LC_OPT_ENT_ENUM_INT("gasmode",   "set the GAS compatibility mode", &gas_var),
 	LC_OPT_LAST
 };