X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;ds=sidebyside;f=ir%2Fbe%2Fbearch_t.h;h=e85c872fa0e49bbb2225e0155bae370d6ab3241f;hb=38efd2ac16aa827ae9f07acc9ebfc7d74422290e;hp=8480dc04e8dc66f8c9f437a2c013ba89a5e58b52;hpb=4546797d0245eb829ee52a91538c36a72c075c0c;p=libfirm diff --git a/ir/be/bearch_t.h b/ir/be/bearch_t.h index 8480dc04e..e85c872fa 100644 --- a/ir/be/bearch_t.h +++ b/ir/be/bearch_t.h @@ -1,282 +1,588 @@ +/* + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ -#ifndef _FIRM_BEARCH_T_H -#define _FIRM_BEARCH_T_H - -#include "firm_config.h" - -#include "irop_t.h" -#include "irnode_t.h" -#include "irmode_t.h" - -#include "hashptr.h" -#include "fourcc.h" -#include "set.h" -#include "list.h" -#include "ident.h" +/** + * @file + * @brief Processor architecture specification - internal data structures. + * @author Sebastian Hack + * @version $Id$ + */ +#ifndef FIRM_BE_BEARCH_T_H +#define FIRM_BE_BEARCH_T_H #include "bearch.h" -#define ARCH_IRN_FOURCC FOURCC('A', 'R', 'C', 'H') +#include "belistsched.h" +#include "beilpsched.h" +#include "bemachine.h" +#include "beirg.h" +#include "beabi.h" +#include "raw_bitset.h" /** - * Flags for registers. + * A register. */ -enum { +struct arch_register_t { + const char *name; /**< The name of the register. */ + const arch_register_class_t *reg_class; /**< The class the register belongs to. */ + unsigned index; /**< The index of the register in the class. */ + arch_register_type_t type; /**< The type of the register. */ + void *data; /**< Custom data. */ +}; - /** - * The register is invariant concerning writes. - * Examples are the 0 registers in RISC architectures. - */ - REG_WRITE_INVARIAT = 1 +static INLINE const arch_register_class_t * +_arch_register_get_class(const arch_register_t *reg) +{ + return reg->reg_class; +} -} arch_register_flags_t; +static INLINE +unsigned _arch_register_get_index(const arch_register_t *reg) +{ + return reg->index; +} + +static INLINE +const char *_arch_register_get_name(const arch_register_t *reg) +{ + return reg->name; +} -typedef enum { -#define ARCH_OBJ(x,list) arch_kind_##x, -#include "bearch_obj.def" -#undef ARCH_OBJ - arch_kind_last -} arch_kind_t; +#define arch_register_get_class(reg) _arch_register_get_class(reg) +#define arch_register_get_index(reg) _arch_register_get_index(reg) +#define arch_register_get_name(reg) _arch_register_get_name(reg) /** - * A header which each of the arch structs should posess. + * Convenience macro to check for register type. + * @param req A pointer to register. + * @param kind The kind of type to check for (see arch_register_type_t). + * @return 1, If register is of given kind, 0 if not. */ -typedef struct { - arch_kind_t kind; - arch_isa_t *isa; - const char *name; - struct list_head list; - unsigned is_new : 1; -} arch_header_t; - +#define arch_register_type_is(reg, kind) \ + (((reg)->type & arch_register_type_ ## kind) != 0) /** - * Get the architecture an arch object belongs to. - * @param obj The object. - * @return The architecture it belongs to. + * A class of registers. + * Like general purpose or floating point. */ -static INLINE arch_isa_t *arch_obj_get_isa(const void *obj) +struct arch_register_class_t { + unsigned index; /**< index of this register class */ + const char *name; /**< The name of the register class.*/ + unsigned n_regs; /**< Number of registers in this + class. */ + ir_mode *mode; /**< The mode of the register class.*/ + const arch_register_t *regs; /**< The array of registers. */ + arch_register_class_flags_t flags; /**< register class flags. */ +}; + +/** return the number of registers in this register class */ +#define arch_register_class_n_regs(cls) ((cls)->n_regs) + +/** return the largest mode of this register class */ +#define arch_register_class_mode(cls) ((cls)->mode) + +/** return the name of this register class */ +#define arch_register_class_name(cls) ((cls)->name) + +/** return the index of this register class */ +#define arch_register_class_index(cls) ((cls)->index) + +/** return the register class flags */ +#define arch_register_class_flags(cls) ((cls)->flags) + +static INLINE const arch_register_t * +_arch_register_for_index(const arch_register_class_t *cls, unsigned idx) { - return ((const arch_header_t *) obj)->isa; + assert(idx < cls->n_regs); + return &cls->regs[idx]; } -typedef enum _arch_register_flag_t { - arch_register_flag_none, - arch_register_flag_caller_saved, /**< The register must be saved by the caller - upon a function call. It thus can be overwritten - in the called function. */ - arch_register_flag_callee_saved, /**< The register must be saved by the called function, - it thus survives a function call. */ - arch_register_flag_ignore /**< Do not consider this register when allocating. */ -} arch_register_flag_t; +#define arch_register_for_index(cls, idx) _arch_register_for_index(cls, idx) /** - * A register. + * Convenience macro to check for set constraints. + * @param req A pointer to register requirements. + * @param kind The kind of constraint to check for (see arch_register_req_type_t). + * @return 1, If the kind of constraint is present, 0 if not. */ -struct _arch_register_t { - arch_header_t header; - int index; /**< The index of the register in the class. */ - const arch_register_class_t *reg_class; /**< The class the register belongs to. */ - arch_register_flag_t flags; /**< Flags describing several properties of - the register. */ -}; +#define arch_register_req_is(req, kind) \ + (((req)->type & (arch_register_req_type_ ## kind)) != 0) /** - * A (sub-) set of registers. + * Expresses requirements to register allocation for an operand. */ -struct _arch_register_set_t { - arch_header_t header; - const struct _arch_register_class_t *reg_class; /**< The register class for this set. */ - char regs[1]; /**< An array containing 0/1 at place i - whether the register with index i is - in the set or not. */ +struct arch_register_req_t { + arch_register_req_type_t type; /**< The type of the constraint. */ + const arch_register_class_t *cls; /**< The register class this constraint belongs to. */ + + const unsigned *limited; /**< allowed register bitset */ + + unsigned other_same; /**< Bitmask of ins which should use the + same register (should_be_same). */ + unsigned other_different; /**< Bitmask of ins which shall use a + different register + (must_be_different) */ }; -static INLINE int _arch_register_in_set(const arch_register_set_t *set, const arch_register_t *reg) +static INLINE int reg_reqs_equal(const arch_register_req_t *req1, + const arch_register_req_t *req2) { - if(reg->reg_class != set->reg_class) + if (req1 == req2) + return 1; + + if (req1->type != req2->type + || req1->cls != req2->cls + || req1->other_same != req2->other_same + || req1->other_different != req2->other_different) return 0; - return set->regs[reg->index]; -} + if (req1->limited != NULL) { + size_t n_regs; + if (req2->limited == NULL) + return 0; -/** - * A class of registers. - * Like general purpose or floating point. - */ -struct _arch_register_class_t { - arch_header_t header; - struct list_head list; /**< list head to list up in the list of all - register classes in an isa. */ - arch_register_set_t *set; /**< A register set containing all registers - in this class. */ - int n_regs; /**< Number of registers in this class. */ - arch_register_t *regs[1]; /**< The array of registers. */ -}; + n_regs = arch_register_class_n_regs(req1->cls); + if (!rbitset_equal(req1->limited, req2->limited, n_regs)) + return 0; + } -static INLINE const arch_register_t *_arch_register_for_index(const arch_register_class_t *cls, int idx) -{ - assert(0 <= idx && idx <= cls->n_regs); - return cls->regs[idx]; + return 1; } /** - * Get the register set for a register class. - * @param cls The register class. - * @return The set containing all registers in the class. + * An inverse operation returned by the backend */ -static INLINE arch_register_set_t *_arch_get_register_set_for_class(const arch_register_class_t *cls) -{ - return cls->set; -} +struct arch_inverse_t { + int n; /**< count of nodes returned in nodes array */ + int costs; /**< costs of this remat */ -/** - * An immediate. - */ -struct _arch_immediate_t { - arch_header_t header; - ir_mode *mode; /**< The mode of the immediate. */ + /**< nodes for this inverse operation. shall be in + * schedule order. last element is the target value + */ + ir_node **nodes; }; -/** - * The member of an enum. - */ -struct _arch_enum_member_t { - arch_header_t header; /**< The omnipresent header. */ - arch_enum_t *enm; /**< The enum, this member belongs to. */ -}; +struct arch_irn_ops_if_t { -/** - * An enumeration operand type. - * - * Enumeration operand types can be used to describe the variants - * of an instruction, like giving the cases for a compare (gt, lt, - * eq, ...) some other special attributes of an instruction. - */ -struct _arch_enum_t { - arch_header_t header; - int n_members; /**< The number of members in this enum. */ - arch_enum_member_t *members[1]; /**< The array of members. */ -}; + /** + * Get the register requirements for a given operand. + * @param self The self pointer. + * @param irn The node. + * @param pos The operand's position + * (-1 for the result of the node, 0..n for the input operands). + * @return The register requirements for the selected operand. + * The pointer returned is never NULL. + */ + const arch_register_req_t *(*get_irn_reg_req)(const void *self, + const ir_node *irn, int pos); -typedef enum _arch_operand_type_t { -#define ARCH_OPERAND_TYPE(name,size_in_irn) arch_operand_type_ ## name, -#include "bearch_operand_types.def" -#undef ARCH_OPERAND_TYPE - arch_operand_type_last -} arch_operand_type_t; + /** + * Set the register for an output operand. + * @param irn The node. + * @param reg The register allocated to that operand. + * @note If the operand is not a register operand, + * the call is ignored. + */ + void (*set_irn_reg)(const void *self, ir_node *irn, const arch_register_t *reg); + /** + * Get the register allocated for an output operand. + * @param irn The node. + * @return The register allocated at that operand. NULL, if + * the operand was no register operand or + * @c arch_register_invalid, if no register has yet been + * allocated for this node. + */ + const arch_register_t *(*get_irn_reg)(const void *self, const ir_node *irn); + /** + * Classify the node. + * @param irn The node. + * @return A classification. + */ + arch_irn_class_t (*classify)(const void *self, const ir_node *irn); -/** - * The data for the different flavours of operand types. - */ -typedef union _arch_operand_data_t { - arch_register_callback_t *callback; /**< The set of valid registers is determined - by a callback function. */ + /** + * Get the flags of a node. + * @param self The irn ops themselves. + * @param irn The node. + * @return A set of flags. + */ + arch_irn_flags_t (*get_flags)(const void *self, const ir_node *irn); - const arch_register_set_t *set; /**< The set of valid registers is directly - given. Note, that if an insn has no constraints, - the set comprises all registers in the - register class. */ + /** + * Get the entity on the stack frame this node depends on. + * @param self The this pointer. + * @param irn The node in question. + * @return The entity on the stack frame or NULL, if the node does not have a + * stack frame entity. + */ + ir_entity *(*get_frame_entity)(const void *self, const ir_node *irn); - const arch_immediate_t *imm; /**< If the operand is an immediate - operand, this describes the kind of - immediate. */ + /** + * Set the entity on the stack frame this node depends on. + * @param self The this pointer. + * @param irn The node in question. + * @param ent The entity to set + */ + void (*set_frame_entity)(const void *self, ir_node *irn, ir_entity *ent); - const arch_enum_t *enm; /**< Some enumeration value. */ + /** + * Set the offset of a node carrying an entity on the stack frame. + * @param self The this pointer. + * @param irn The node. + * @param offset The offset of the node's stack frame entity. + */ + void (*set_frame_offset)(const void *self, ir_node *irn, int offset); - int same_as_pos; /**< 'Same as' position for equals. */ -} arch_operand_data_t; + /** + * Returns the delta of the stackpointer for nodes that increment or + * decrement the stackpointer with a constant value. (push, pop + * nodes on most architectures). + * A positive value stands for an expanding stack area, a negative value for + * a shrinking one. + * + * @param self The this pointer + * @param irn The node + * @return 0 if the stackpointer is not modified with a constant + * value, otherwise the increment/decrement value + */ + int (*get_sp_bias)(const void *self, const ir_node *irn); + + /** + * Returns an inverse operation which yields the i-th argument + * of the given node as result. + * + * @param self The this pointer. + * @param irn The original operation + * @param i Index of the argument we want the inverse operation to yield + * @param inverse struct to be filled with the resulting inverse op + * @param obstack The obstack to use for allocation of the returned nodes array + * @return The inverse operation or NULL if operation invertible + */ + arch_inverse_t *(*get_inverse)(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obstack); + + /** + * Get the estimated cycle count for @p irn. + * + * @param self The this pointer. + * @param irn The node. + * + * @return The estimated cycle count for this operation + */ + int (*get_op_estimated_cost)(const void *self, const ir_node *irn); + + /** + * Asks the backend whether operand @p i of @p irn can be loaded form memory internally + * + * @param self The this pointer. + * @param irn The node. + * @param i Index of the argument we would like to know whether @p irn can load it form memory internally + * + * @return nonzero if argument can be loaded or zero otherwise + */ + int (*possible_memory_operand)(const void *self, const ir_node *irn, unsigned int i); + + /** + * Ask the backend to assimilate @p reload of operand @p i into @p irn. + * + * @param self The this pointer. + * @param irn The node. + * @param spill The spill. + * @param i The position of the reload. + */ + void (*perform_memory_operand)(const void *self, ir_node *irn, ir_node *spill, unsigned int i); +}; /** - * An operand to an instruction. + * irn_ops base class. */ -struct _arch_operand_t { - arch_operand_type_t type; /**< The type of the operand. */ - arch_operand_data_t data; /**< The payload. */ +struct arch_irn_ops_t { + const arch_irn_ops_if_t *impl; }; /** - * An instruction format. + * The code generator interface. */ -struct _arch_insn_format_t { - arch_header_t header; - int n_in; /**< Number of in operands. */ - int n_out; /**< Number of out operands. */ +struct arch_code_generator_if_t { + /** + * Initialize the code generator. + * @param birg A backend IRG session. + * @return A newly created code generator. + */ + void *(*init)(be_irg_t *birg); - arch_operand_t operands[1]; /**< Array with operands. */ -}; + /** + * return node used as base in pic code addresses + */ + ir_node* (*get_pic_base)(void *self); -/* - * Transform the position into an offset which is suitable to - * index the operands array in the format. - * - * The layout is: - * operand: in0 in1 in2 ... out0 out1 out2 - * position: 0 1 2 -1 -2 -3 - */ -#define arch_inout_to_index(fmt, pos) ((pos) >= 0 ? (pos) : -((pos) + 1) + (fmt)->n_in) + /** + * Called before abi introduce. + */ + void (*before_abi)(void *self); + + /** + * Called, when the graph is being normalized. + */ + void (*prepare_graph)(void *self); -#define arch_get_in_operand(fmt, pos) (&((fmt)->operands[arch_inout_to_index(fmt, pos)])) -#define arch_get_out_operand(fmt, pos) (&((fmt)->operands[arch_inout_to_index(fmt, -((pos) + 1))])) + /** + * Backend may provide an own spiller. + * This spiller needs to spill all register classes. + */ + void (*spill)(void *self, be_irg_t *birg); + /** + * Called before scheduling. + */ + void (*before_sched)(void *self); + + /** + * Called before register allocation. + */ + void (*before_ra)(void *self); + + /** + * Called after register allocation. + */ + void (*after_ra)(void *self); + + /** + * Called directly before done is called. This should be the last place + * where the irg is modified. + */ + void (*finish)(void *self); + + /** + * Called after everything happened. This call should emit the final + * assembly code but avoid changing the irg. + * The code generator must also be de-allocated here. + */ + void (*done)(void *self); +}; /** - * An instruction. + * helper macro: call function func from the code generator + * if it's implemented. */ -struct _arch_insn_t { - arch_header_t header; - const arch_insn_format_t *format; /**< The format of the instruction. */ - ir_op *op; /**< The firm opcode for this insn. */ +#define _arch_cg_call(cg, func) \ +do { \ + if((cg)->impl->func) \ + (cg)->impl->func(cg); \ +} while(0) + +#define _arch_cg_call_env(cg, env, func) \ +do { \ + if((cg)->impl->func) \ + (cg)->impl->func(cg, env); \ +} while(0) + +#define arch_code_generator_before_abi(cg) _arch_cg_call(cg, before_abi) +#define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph) +#define arch_code_generator_before_sched(cg) _arch_cg_call(cg, before_sched) +#define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra) +#define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra) +#define arch_code_generator_finish(cg) _arch_cg_call(cg, finish) +#define arch_code_generator_done(cg) _arch_cg_call(cg, done) +#define arch_code_generator_spill(cg, birg) _arch_cg_call_env(cg, birg, spill) +#define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL) +#define arch_code_generator_get_pic_base(cg) \ + ((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL) + +/** + * Code generator base class. + */ +struct arch_code_generator_t { + const arch_code_generator_if_t *impl; }; /** - * This truct is placed into each ir_node which is made from an arch - * insn (If the node is made via arch_new node). + * ISA base class. */ -typedef struct _arch_irn_data_t { - unsigned magic; /**< A magic number to tell if node is an - arch node. */ - const arch_insn_t *insn; /**< The insn this nodes instantiates. */ -} arch_irn_data_t; +struct arch_isa_t { + const arch_isa_if_t *impl; + const arch_register_t *sp; /** The stack pointer register. */ + const arch_register_t *bp; /** The base pointer register. */ + int stack_dir; /** -1 for decreasing, 1 for increasing. */ + int stack_alignment; /** stack alignment */ + const be_main_env_t *main_env; /** the be main environment */ + int spill_cost; /** cost for a be_Spill node */ + int reload_cost; /** cost for a be_Reload node */ +}; -#define _arch_get_irn_data(irn) ((const arch_irn_data_t *) &((irn)->attr)) +#define arch_isa_stack_dir(isa) ((isa)->stack_dir) +#define arch_isa_sp(isa) ((isa)->sp) +#define arch_isa_bp(isa) ((isa)->bp) /** - * Check, if an ir node is made by the arch module. - * @param irn An ir node. - * @return 1 if the node was made via arch_new_node() or 0 otherwise. + * Architecture interface. */ -static INLINE int _arch_is_irn(const ir_node *irn) -{ - return _arch_get_irn_data(irn)->magic == ARCH_IRN_FOURCC; -} +struct arch_isa_if_t { + /** + * Initialize the isa interface. + * @param file_handle the file handle to write the output to + * @param main_env the be main environment + * @return a new isa instance + */ + void *(*init)(FILE *file_handle); -static INLINE const arch_insn_t *_arch_irn_get_insn(const ir_node *irn) -{ - if(!_arch_is_irn(irn)) - return NULL; + /** + * Free the isa instance. + */ + void (*done)(void *self); - return _arch_get_irn_data(irn)->insn; -} + /** + * Get the the number of register classes in the isa. + * @return The number of register classes. + */ + unsigned (*get_n_reg_class)(const void *self); + + /** + * Get the i-th register class. + * @param i The number of the register class. + * @return The register class. + */ + const arch_register_class_t *(*get_reg_class)(const void *self, unsigned i); + + /** + * Get the register class which shall be used to store a value of a given mode. + * @param self The this pointer. + * @param mode The mode in question. + * @return A register class which can hold values of the given mode. + */ + const arch_register_class_t *(*get_reg_class_for_mode)(const void *self, const ir_mode *mode); + + /** + * Get the ABI restrictions for procedure calls. + * @param self The this pointer. + * @param call_type The call type of the method (procedure) in question. + * @param p The array of parameter locations to be filled. + */ + void (*get_call_abi)(const void *self, ir_type *call_type, be_abi_call_t *abi); + + /** + * The irn handler for this architecture. + * The irn handler is registered by the Firm back end + * when the architecture is initialized. + */ + arch_get_irn_ops_t *(*get_irn_handler)(const void *self); + /** + * Get the code generator interface. + * @param self The this pointer. + * @return Some code generator interface. + */ + const arch_code_generator_if_t *(*get_code_generator_if)(void *self); + + /** + * Get the list scheduler to use. There is already a selector given, the + * backend is free to modify and/or ignore it. + * + * @param self The isa object. + * @param selector The selector given by options. + * @return The list scheduler selector. + */ + const list_sched_selector_t *(*get_list_sched_selector)(const void *self, list_sched_selector_t *selector); + + /** + * Get the ILP scheduler to use. + * @param self The isa object. + * @return The ILP scheduler selector + */ + const ilp_sched_selector_t *(*get_ilp_sched_selector)(const void *self); + + /** + * Get the necessary alignment for storing a register of given class. + * @param self The isa object. + * @param cls The register class. + * @return The alignment in bytes. + */ + int (*get_reg_class_alignment)(const void *self, const arch_register_class_t *cls); + + /** + * A "static" function, returns the frontend settings + * needed for this backend. + */ + const backend_params *(*get_params)(void); + + /** + * Returns an 2-dim array of execution units, @p irn can be executed on. + * The first dimension is the type, the second the allowed units of this + * type. + * Each dimension is a NULL terminated list. + * @param self The isa object. + * @param irn The node. + * @return An array of allowed execution units. + * exec_unit = { + * { unit1_of_tp1, ..., unitX1_of_tp1, NULL }, + * ..., + * { unit1_of_tpY, ..., unitXn_of_tpY, NULL }, + * NULL + * }; + */ + const be_execution_unit_t ***(*get_allowed_execution_units)(const void *self, const ir_node *irn); + + /** + * Return the abstract machine for this isa. + * @param self The isa object. + */ + const be_machine_t *(*get_machine)(const void *self); + + /** + * Return an ordered list of irgs where code should be generated for. + * If NULL is returned, all irg will be taken into account and they will be + * generated in an arbitrary order. + * @param self The isa object. + * @param irgs A flexible array ARR_F of length 0 where the backend can append the desired irgs. + * @return A flexible array ARR_F containing all desired irgs in the desired order. + */ + ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs); +}; + +#define arch_isa_get_n_reg_class(isa) ((isa)->impl->get_n_reg_class(isa)) +#define arch_isa_get_reg_class(isa,i) ((isa)->impl->get_reg_class(isa, i)) +#define arch_isa_get_irn_handler(isa) ((isa)->impl->get_irn_handler(isa)) +#define arch_isa_get_call_abi(isa,tp,abi) ((isa)->impl->get_call_abi((isa), (tp), (abi))) +#define arch_isa_get_reg_class_for_mode(isa,mode) ((isa)->impl->get_reg_class_for_mode((isa), (mode))) +#define arch_isa_make_code_generator(isa,irg) ((isa)->impl->make_code_generator((isa), (irg))) +#define arch_isa_get_reg_class_alignment(isa, cls) ((isa)->impl->get_reg_class_alignment((isa), (cls))) +#define arch_isa_get_allowed_execution_units(isa, irn) ((isa)->impl->get_allowed_execution_units((isa), (irn))) +#define arch_isa_get_machine(isa) ((isa)->impl->get_machine((isa))) +#define arch_isa_get_backend_irg_list(isa, irgs) ((isa)->impl->get_backend_irg_list((isa), (irgs))) /** - * An instruction set architecture. + * Environment for the architecture infrastructure. + * Keep this everywhere you're going. */ -struct _arch_isa_t { - arch_header_t header; - struct list_head heads[arch_kind_last]; /**< List heads to list objects created in the - context of this isa. Note: some of the list heads - remain unused. */ -}; +struct arch_env_t { + arch_isa_t *isa; /**< The isa about which everything is. */ -struct _arch_implementation_t { - const arch_isa_t *isa; - const char *name; + arch_get_irn_ops_t *arch_handler; /**< The get_irn_ops handler for the selected architecture. */ }; +/** + * Get the isa of an arch environment. + * @param env The environment. + * @return The isa with which the env was initialized with. + */ +#define arch_env_get_isa(env) ((env)->isa) -#endif /* _FIRM_BEARCH_T_H */ +#endif /* FIRM_BE_BEARCH_T_H */