Model (un)reachable block info with bottom/top, not false/true.
[libfirm] / ir / opt / fp-vrp.c
index 14cf316..f5d5edb 100644 (file)
@@ -169,9 +169,9 @@ static int transfer(ir_node* const irn)
 
                DB((dbg, LEVEL_3, "transfer %+F\n", irn));
 
-               if (b->z == f && b->o == f) {
+               if (b->z == f) {
                        z = f;
-                       o = f;
+                       o = t;
                } else switch (get_irn_opcode(irn)) {
                        case iro_Proj: {
                                ir_node* const pred = get_Proj_pred(irn);
@@ -249,8 +249,13 @@ result_unknown_X:
                                irn == get_irg_end_block(irg);
                }
 
-               o = f;
-               z = reachable ? t : f;
+               if (reachable) {
+                       z = t;
+                       o = f;
+               } else {
+                       z = f;
+                       o = t;
+               }
        } else if (mode_is_intb(m)) {
                DB((dbg, LEVEL_3, "transfer %+F\n", irn));
                switch (get_irn_opcode(irn)) {
@@ -772,6 +777,12 @@ void fixpoint_vrp(ir_graph* const irg)
                   blocks in Firm. Moreover build phi list. */
                irg_walk_anchors(irg, clear_links, build_phi_lists, NULL);
 
+               { ir_tarval* const f = get_tarval_b_false();
+                       ir_tarval* const t = get_tarval_b_true();
+                       set_bitinfo(get_irg_bad(irg),       f, t); /* Undefined. */
+                       set_bitinfo(get_irg_end_block(irg), t, f); /* Reachable. */
+               }
+
                /* TODO Improve iteration order. Best is reverse postorder in data flow
                 * direction and respecting loop nesting for fastest convergence. */
                irg_walk_blkwise_dom_top_down(irg, NULL, first_round, q);