finalize debug stuff before arch_env_done which frees be_emitter

[libfirm] / ir / opt / fp-vrp.c

diff --git a/ir/opt/fp-vrp.c b/ir/opt/fp-vrp.c
index b3bd270..3b4dccd 100644 (file)
--- a/ir/opt/fp-vrp.c
+++ b/ir/opt/fp-vrp.c
@@ -745,6 +745,28 @@ exchange_only:
                        break;
                }
 
+               case iro_Eor: {
+                       ir_node*       const l  = get_Eor_left(irn);
+                       ir_node*       const r  = get_Eor_right(irn);
+                       bitinfo const* const bl = get_bitinfo(l);
+                       bitinfo const* const br = get_bitinfo(r);
+                       /* if each bit is guaranteed to be zero on either the left or right
+                        * then an Add will have the same effect as the Eor. Change it for
+                        * normalisation */
+                       if (tarval_is_null(tarval_and(bl->z, br->z))) {
+                               dbg_info      *dbgi     = get_irn_dbg_info(irn);
+                               ir_node       *block    = get_nodes_block(irn);
+                               ir_mode       *mode     = get_irn_mode(irn);
+                               ir_node       *new_node = new_rd_Add(dbgi, block, l, r, mode);
+                               bitinfo const *bi       = get_bitinfo(irn);
+                               DB((dbg, LEVEL_2, "%+F(%+F, %+F) normalised to Add\n", irn, l, r));
+                               set_bitinfo(new_node, bi->z, bi->o);
+                               exchange(irn, new_node);
+                               env->modified = 1;
+                       }
+                       break;
+               }
+
                case iro_Or: {
                        ir_node*       const l  = get_Or_left(irn);
                        ir_node*       const r  = get_Or_right(irn);
@@ -763,6 +785,22 @@ exchange_only:
                                        env->modified = 1;
                                }
                        }
+
+                       /* if each bit is guaranteed to be zero on either the left or right
+                        * then an Add will have the same effect as the Or. Change it for
+                        * normalisation */
+                       if (tarval_is_null(tarval_and(bl->z, br->z))) {
+                               dbg_info      *dbgi     = get_irn_dbg_info(irn);
+                               ir_node       *block    = get_nodes_block(irn);
+                               ir_mode       *mode     = get_irn_mode(irn);
+                               ir_node       *new_node = new_rd_Add(dbgi, block, l, r, mode);
+                               bitinfo const *bi       = get_bitinfo(irn);
+                               DB((dbg, LEVEL_2, "%+F(%+F, %+F) normalised to Add\n", irn, l, r));
+                               set_bitinfo(new_node, bi->z, bi->o);
+                               exchange(irn, new_node);
+                               env->modified = 1;
+                       }
+
                        break;
                }
        }
@@ -866,9 +904,9 @@ static ir_graph_state_t do_fixpoint_vrp(ir_graph* const irg)
        return res;
 }
 
-optdesc_t opt_fpvrp = {
+static optdesc_t opt_fpvrp = {
        "fp-vrp",
-       IR_GRAPH_STATE_NO_BAD_BLOCKS | IR_GRAPH_STATE_NO_UNREACHABLE_CODE | IR_GRAPH_STATE_CONSISTENT_DOMINANCE | IR_GRAPH_STATE_CONSISTENT_OUT_EDGES,
+       IR_GRAPH_STATE_NO_BADS | IR_GRAPH_STATE_NO_UNREACHABLE_CODE | IR_GRAPH_STATE_CONSISTENT_DOMINANCE | IR_GRAPH_STATE_CONSISTENT_OUT_EDGES,
        do_fixpoint_vrp,
 };