It does not make any sense to remove AM, which loads a non-GP value to fix register...

[libfirm] / ir / lower / lower_hl.c

diff --git a/ir/lower/lower_hl.c b/ir/lower/lower_hl.c
index dcbf9e8..dbb35c3 100644 (file)
--- a/ir/lower/lower_hl.c
+++ b/ir/lower/lower_hl.c
@@ -54,7 +54,7 @@ static void lower_sel(ir_node *sel) {
 
        /* Do not lower frame type/global offset table access: must be lowered by the backend. */
        ptr = get_Sel_ptr(sel);
-       if (ptr == get_irg_frame(current_ir_graph) || ptr == get_irg_globals(current_ir_graph))
+       if (ptr == get_irg_frame(current_ir_graph))
                return;
 
        ent   = get_Sel_entity(sel);
@@ -354,7 +354,7 @@ static void lower_bitfields_loads(ir_node *proj, ir_node *load) {
        int offset, bit_offset, bits, bf_bits, old_cse;
        dbg_info *db;
 
-       if (get_irn_op(sel) != op_Sel)
+       if (!is_Sel(sel))
                return;
 
        ent     = get_Sel_entity(sel);
@@ -447,7 +447,7 @@ static void lower_bitfields_stores(ir_node *store) {
        dbg_info *db;
 
        /* check bitfield access */
-       if (get_irn_op(sel) != op_Sel)
+       if (!is_Sel(sel))
                return;
 
        ent     = get_Sel_entity(sel);
@@ -568,9 +568,8 @@ static void lower_bf_access(ir_node *irn, void *env) {
        {
                long proj     = get_Proj_proj(irn);
                ir_node *pred = get_Proj_pred(irn);
-               ir_op *op     = get_irn_op(pred);
 
-               if ((proj == pn_Load_res) && (op == op_Load))
+               if (proj == pn_Load_res && is_Load(pred))
                        lower_bitfields_loads(irn, pred);
                break;
        }
@@ -598,7 +597,6 @@ void lower_highlevel_graph(ir_graph *irg, int lower_bitfields) {
 
        /* Finally: lower SymConst-Size and Sel nodes, Casts, unaligned Load/Stores. */
        irg_walk_graph(irg, NULL, lower_irnode, NULL);
-       set_irg_phase_low(irg);
 }  /* lower_highlevel_graph */
 
 /*