ent = get_Sel_entity(sel);
bf_type = get_entity_type(ent);
+ /* must be a bitfield type */
+ if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
+ return;
+
/* We have a bitfield access, if either a bit offset is given, or
the size is not integral. */
bf_mode = get_type_mode(bf_type);
bits = get_mode_size_bits(mode);
offset = get_entity_offset(ent);
- bit_offset += 8 * offset;
/*
* ok, here we are: now convert the Proj_mode_bf(Load) into And(Shr(Proj_mode(Load)) for unsigned
/* abandon bitfield sel */
ptr = get_Sel_ptr(sel);
db = get_irn_dbg_info(sel);
+ ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
set_Load_ptr(load, ptr);
set_Load_mode(load, mode);
ent = get_Sel_entity(sel);
bf_type = get_entity_type(ent);
+ /* must be a bitfield type */
+ if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
+ return;
+
/* We have a bitfield access, if either a bit offset is given, or
the size is not integral. */
bf_mode = get_type_mode(bf_type);
*/
mem = get_Store_mem(store);
offset = get_entity_offset(ent);
- bit_offset += 8 * offset;
bits_mask = get_mode_size_bits(mode) - bf_bits;
mask = ((unsigned)-1) >> bits_mask;
/* abandon bitfield sel */
ptr = get_Sel_ptr(sel);
db = get_irn_dbg_info(sel);
+ ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
if (neg_mask) {
/* there are some bits, normal case */
set_Store_ptr(store, ptr);
} /* lower_bitfields_stores */
+/**
+ * Lowers unaligned Loads.
+ */
+static void lower_unaligned_Load(ir_node *load) {
+ /* NYI */
+}
+
+/**
+ * Lowers unaligned Stores
+ */
+static void lower_unaligned_Store(ir_node *store) {
+ /* NYI */
+}
+
/**
* lowers IR-nodes, called from walker
*/
case iro_SymConst:
lower_symconst(irn);
break;
+ case iro_Load:
+ if (env != NULL && get_Load_align(irn) == align_non_aligned)
+ lower_unaligned_Load(irn);
+ break;
+ case iro_Store:
+ if (env != NULL && get_Store_align(irn) == align_non_aligned)
+ lower_unaligned_Store(irn);
+ break;
default:
break;
}
/* First step: lower bitfield access: must be run as long as Sels still exists. */
irg_walk_graph(irg, NULL, lower_bf_access, NULL);
- /* Finally: lower SymConst-Size and Sel nodes. */
+ /* Finally: lower SymConst-Size and Sel nodes, unaligned Load/Stores. */
irg_walk_graph(irg, NULL, lower_irnode, NULL);
set_irg_phase_low(irg);