/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
lower_env_t *lenv = env;
ir_mode *mode = get_irn_op_mode(node);
node_entry_t *link;
- int i;
+ int i, idx;
if (mode == lenv->params->high_signed ||
mode == lenv->params->high_unsigned) {
memset(link, 0, sizeof(*link));
- lenv->entries[get_irn_idx(node)] = link;
+ idx = get_irn_idx(node);
+ if (idx >= lenv->n_entries) {
+ /* enlarge: this happens only for Rotl nodes which is RARELY */
+ int old = lenv->n_entries;
+ int n_idx = idx + (idx >> 3);
+
+ ARR_RESIZE(node_entry_t *, lenv->entries, n_idx);
+ memset(&lenv->entries[old], 0, (n_idx - old) * sizeof(lenv->entries[0]));
+ lenv->n_entries = n_idx;
+ }
+ lenv->entries[idx] = link;
lenv->flags |= MUST_BE_LOWERED;
} else if (is_Conv(node)) {
/* Conv nodes have two modes */
ent = entry->ent;
} /* if */
sym.entity_p = ent;
- return new_r_SymConst(current_ir_graph, block, sym, symconst_addr_ent);
+ return new_r_SymConst(current_ir_graph, block, mode_P_code, sym, symconst_addr_ent);
} /* get_intrinsic_address */
/**
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shr_left(node);
ir_node *c;
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_mode *mode_l;
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shl_left(node);
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shrs_left(node);
long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
idx = get_irn_idx(node);
if (shf_cnt > 0) {
+ ir_node *tmp;
c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
- env->entries[idx]->low_word = new_r_Shrs(irg, block, left, c, mode);
+ tmp = new_r_Shrs(irg, block, left, c, mode);
+ /* low word is expected to have mode_Iu */
+ env->entries[idx]->low_word = new_r_Conv(irg, block, tmp, mode_Iu);
} else {
env->entries[idx]->low_word = left;
} /* if */
} /* lower_Shrs */
/**
- * Translate a Rot and handle special cases.
+ * Rebuild Rotl nodes into Or(Shl, Shr) and prepare all nodes.
*/
-static void lower_Rot(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_node *right = get_Rot_right(node);
-
- if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
-
- if (tarval_is_long(tv) &&
- get_tarval_long(tv) == get_mode_size_bits(mode)) {
- ir_node *left = get_Rot_left(node);
- ir_node *h, *l;
- int idx = get_irn_idx(left);
-
- l = env->entries[idx]->low_word;
- h = env->entries[idx]->high_word;
- idx = get_irn_idx(node);
+static void prepare_links_and_handle_rotl(ir_node *node, void *env) {
+ lower_env_t *lenv = env;
+
+ if (is_Rotl(node)) {
+ ir_mode *mode = get_irn_op_mode(node);
+ if (mode == lenv->params->high_signed ||
+ mode == lenv->params->high_unsigned) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left, *shl, *shr, *or, *block, *sub, *c;
+ ir_mode *omode, *rmode;
+ ir_graph *irg;
+ dbg_info *dbg;
+ optimization_state_t state;
+
+ if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
+ tarval *tv = get_Const_tarval(right);
+
+ if (tarval_is_long(tv) &&
+ get_tarval_long(tv) == (long)get_mode_size_bits(mode)) {
+ /* will be optimized in lower_Rotl() */
+ return;
+ }
+ }
+
+ /* replace the Rotl(x,y) by an Or(Shl(x,y), Shr(x,64-y)) and lower those */
+ dbg = get_irn_dbg_info(node);
+ omode = get_irn_mode(node);
+ left = get_Rotl_left(node);
+ irg = current_ir_graph;
+ block = get_nodes_block(node);
+ shl = new_rd_Shl(dbg, irg, block, left, right, omode);
+ rmode = get_irn_mode(right);
+ c = new_Const_long(rmode, get_mode_size_bits(omode));
+ sub = new_rd_Sub(dbg, irg, block, c, right, rmode);
+ shr = new_rd_Shr(dbg, irg, block, left, sub, omode);
+
+ /* optimization must be switched off here, or we will get the Rotl back */
+ save_optimization_state(&state);
+ set_opt_algebraic_simplification(0);
+ or = new_rd_Or(dbg, irg, block, shl, shr, omode);
+ restore_optimization_state(&state);
+
+ exchange(node, or);
+
+ /* do lowering on the new nodes */
+ prepare_links(shl, env);
+ prepare_links(c, env);
+ prepare_links(sub, env);
+ prepare_links(shr, env);
+ prepare_links(or, env);
+ }
+ } else {
+ prepare_links(node, env);
+ }
+}
- env->entries[idx]->low_word = h;
- env->entries[idx]->high_word = l;
+/**
+ * Translate a special case Rotl(x, sizeof(w)).
+ */
+static void lower_Rotl(ir_node *node, ir_mode *mode, lower_env_t *env) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left = get_Rotl_left(node);
+ ir_node *h, *l;
+ int idx = get_irn_idx(left);
+
+ assert(get_mode_arithmetic(mode) == irma_twos_complement &&
+ is_Const(right) && tarval_is_long(get_Const_tarval(right)) &&
+ get_tarval_long(get_Const_tarval(right)) == (long)get_mode_size_bits(mode));
+
+ l = env->entries[idx]->low_word;
+ h = env->entries[idx]->high_word;
+ idx = get_irn_idx(node);
- return;
- } /* if */
- } /* if */
- lower_Shiftop(node, mode, env);
-} /* lower_Rot */
+ env->entries[idx]->low_word = h;
+ env->entries[idx]->high_word = l;
+} /* lower_Rotl */
/**
* Translate an Unop.
env->entries[idx]->high_word = constr_rd(dbg, irg, block, lop_h, rop_h, mode);
} /* lower_Binop_logical */
-/** create a logical operation tranformation */
+/** create a logical operation transformation */
#define lower_logical(op) \
static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \
lower_Binop_logical(node, mode, env, new_rd_##op); \
assert(projT && projF);
/* create a new high compare */
- block = get_nodes_block(cmp);
+ block = get_nodes_block(node);
dbg = get_irn_dbg_info(cmp);
irg = current_ir_graph;
pnc = get_Proj_proj(sel);
ir_node *cmp = new_rd_Cmp(dbg, irg, block, or, new_Const_long(mode, 0));
ir_node *proj = new_r_Proj(irg, block, cmp, mode_b, pnc);
- exchange(sel, proj);
+ set_Cond_selector(node, proj);
return;
}
}
* Translate an Unknown into two.
*/
static void lower_Unknown(ir_node *node, ir_mode *mode, lower_env_t *env) {
- int idx = get_irn_idx(node);
+ int idx = get_irn_idx(node);
ir_graph *irg = current_ir_graph;
+ ir_mode *low_mode = env->params->low_unsigned;
- env->entries[idx]->low_word =
+ env->entries[idx]->low_word = new_r_Unknown(irg, low_mode);
env->entries[idx]->high_word = new_r_Unknown(irg, mode);
} /* lower_Unknown */
} /* lower_Phi */
/**
- * Translate a Psi.
+ * Translate a Mux.
*/
-static void lower_Psi(ir_node *psi, ir_mode *mode, lower_env_t *env) {
+static void lower_Mux(ir_node *mux, ir_mode *mode, lower_env_t *env) {
ir_graph *irg = current_ir_graph;
ir_node *block, *val;
- ir_node **valsl, **valsh, **conds;
+ ir_node *true_l, *true_h, *false_l, *false_h, *sel;
dbg_info *dbg;
- int idx, i, n_conds = get_Psi_n_conds(psi);
+ int idx;
- /* first create a new in array */
- NEW_ARR_A(ir_node *, valsl, n_conds + 1);
- NEW_ARR_A(ir_node *, valsh, n_conds + 1);
+ val = get_Mux_true(mux);
+ idx = get_irn_idx(val);
+ if (env->entries[idx]->low_word) {
+ /* Values already build */
+ true_l = env->entries[idx]->low_word;
+ true_h = env->entries[idx]->high_word;
+ } else {
+ /* still not ready */
+ pdeq_putr(env->waitq, mux);
+ return;
+ } /* if */
- for (i = 0; i < n_conds; ++i) {
- val = get_Psi_val(psi, i);
- idx = get_irn_idx(val);
- if (env->entries[idx]->low_word) {
- /* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
- } else {
- /* still not ready */
- pdeq_putr(env->waitq, psi);
- return;
- } /* if */
- } /* for */
- val = get_Psi_default(psi);
+ val = get_Mux_false(mux);
idx = get_irn_idx(val);
if (env->entries[idx]->low_word) {
/* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
+ false_l = env->entries[idx]->low_word;
+ false_h = env->entries[idx]->high_word;
} else {
/* still not ready */
- pdeq_putr(env->waitq, psi);
+ pdeq_putr(env->waitq, mux);
return;
} /* if */
- NEW_ARR_A(ir_node *, conds, n_conds);
- for (i = 0; i < n_conds; ++i) {
- conds[i] = get_Psi_cond(psi, i);
- } /* for */
+ sel = get_Mux_sel(mux);
- dbg = get_irn_dbg_info(psi);
- block = get_nodes_block(psi);
+ dbg = get_irn_dbg_info(mux);
+ block = get_nodes_block(mux);
- idx = get_irn_idx(psi);
+ idx = get_irn_idx(mux);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsl, mode);
- env->entries[idx]->high_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsh, mode);
-} /* lower_Psi */
+ env->entries[idx]->low_word = new_rd_Mux(dbg, irg, block, sel, false_l, true_l, mode);
+ env->entries[idx]->high_word = new_rd_Mux(dbg, irg, block, sel, false_h, true_h, mode);
+} /* lower_Mux */
/**
* check for opcodes that must always be lowered.
int idx = get_irn_idx(node);
ir_mode *mode = get_irn_mode(node);
- if (mode == mode_b || is_Psi(node)) {
+ if (mode == mode_b || is_Mux(node) || is_Conv(node)) {
int i;
for (i = get_irn_arity(node) - 1; i >= 0; --i) {
return (e1->imode - e2->imode) | (e1->omode - e2->omode);
} /* static int cmp_conv_tp */
+/**
+ * Enter a lowering function into an ir_op.
+ */
+static void enter_lower_func(ir_op *op, lower_func func) {
+ op->ops.generic = (op_func)func;
+}
+
/*
* Do the lowering.
*/
if (! prim_types)
prim_types = pmap_create();
if (! intrinsic_fkt)
- intrinsic_fkt = new_set(cmp_op_mode, iro_MaxOpcode);
+ intrinsic_fkt = new_set(cmp_op_mode, iro_Last + 1);
if (! conv_types)
conv_types = new_set(cmp_conv_tp, 16);
if (! lowered_type)
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
-#define LOWER2(op, fkt) op_##op->ops.generic = (op_func)fkt
+#define LOWER2(op, fkt) enter_lower_func(op_##op, fkt)
#define LOWER(op) LOWER2(op, lower_##op)
#define LOWER_BIN(op) LOWER2(op, lower_Binop)
#define LOWER_UN(op) LOWER2(op, lower_Unop)
LOWER(Call);
LOWER(Unknown);
LOWER(Phi);
- LOWER(Psi);
+ LOWER(Mux);
LOWER(Start);
LOWER_BIN(Add);
LOWER(Shl);
LOWER(Shr);
LOWER(Shrs);
- LOWER(Rot);
+ LOWER(Rotl);
LOWER(DivMod);
LOWER(Div);
LOWER(Mod);
obstack_init(&lenv.obst);
n_idx = get_irg_last_idx(irg);
+ n_idx = n_idx + (n_idx >> 2); /* add 25% */
lenv.n_entries = n_idx;
- lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0]));
+ lenv.entries = NEW_ARR_F(node_entry_t *, n_idx);
memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0]));
/* first step: link all nodes and allocate data */
lenv.flags = 0;
lenv.proj_2_block = pmap_create();
- irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv);
+ irg_walk_graph(irg, firm_clear_link, prepare_links_and_handle_rotl, &lenv);
if (lenv.flags & MUST_BE_LOWERED) {
DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg));
} /* if */
} /* if */
pmap_destroy(lenv.proj_2_block);
- free(lenv.entries);
+ DEL_ARR_F(lenv.entries);
obstack_free(&lenv.obst, NULL);
} /* for */
del_pdeq(lenv.waitq);
projects / libfirm / blobdiff