* @author Michael Beck
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
-# include "config.h"
-#endif
-
-#ifdef HAVE_STRING_H
-# include <string.h>
-#endif
-#ifdef HAVE_STDLIB_H
-# include <stdlib.h>
-#endif
+#include "config.h"
+#include <string.h>
+#include <stdlib.h>
#include <assert.h>
+#include "error.h"
#include "lowering.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "pmap.h"
#include "pdeq.h"
#include "irdump.h"
-#include "xmalloc.h"
+#include "array_t.h"
/** A map from mode to a primitive type. */
static pmap *prim_types;
typedef struct _lower_env_t {
node_entry_t **entries; /**< entries per node */
struct obstack obst; /**< an obstack holding the temporary data */
+ ir_type *l_mtp; /**< lowered method type of the current method */
tarval *tv_mode_bytes; /**< a tarval containing the number of bytes in the lowered modes */
tarval *tv_mode_bits; /**< a tarval containing the number of bits in the lowered modes */
pdeq *waitq; /**< a wait queue of all nodes that must be handled later */
pmap *proj_2_block; /**< a map from ProjX to its destination blocks */
+ ident *first_id; /**< .l for little and .h for big endian */
+ ident *next_id; /**< .h for little and .l for big endian */
const lwrdw_param_t *params; /**< transformation parameter */
unsigned flags; /**< some flags */
int n_entries; /**< number of entries */
+ ir_type *value_param_tp; /**< the old value param type */
} lower_env_t;
/**
set_irn_in(block, i + 1, in);
- for (phi = get_irn_link(block); phi; phi = get_irn_link(phi)) {
+ for (phi = get_Block_phis(block); phi != NULL; phi = get_Phi_next(phi)) {
for (i = 0; i < arity; ++i)
in[i] = get_irn_n(phi, i);
in[i] = in[nr];
lower_env_t *lenv = env;
ir_mode *mode = get_irn_op_mode(node);
node_entry_t *link;
- int i;
+ int i, idx;
if (mode == lenv->params->high_signed ||
mode == lenv->params->high_unsigned) {
memset(link, 0, sizeof(*link));
- lenv->entries[get_irn_idx(node)] = link;
+ idx = get_irn_idx(node);
+ if (idx >= lenv->n_entries) {
+ /* enlarge: this happens only for Rotl nodes which is RARELY */
+ int old = lenv->n_entries;
+ int n_idx = idx + (idx >> 3);
+
+ ARR_RESIZE(node_entry_t *, lenv->entries, n_idx);
+ memset(&lenv->entries[old], 0, (n_idx - old) * sizeof(lenv->entries[0]));
+ lenv->n_entries = n_idx;
+ }
+ lenv->entries[idx] = link;
lenv->flags |= MUST_BE_LOWERED;
} else if (is_Conv(node)) {
/* Conv nodes have two modes */
} else if (is_Phi(node)) {
/* link all Phi nodes to its block */
ir_node *block = get_nodes_block(node);
-
- set_irn_link(node, get_irn_link(block));
- set_irn_link(block, node);
+ add_Block_phi(block, node);
} else if (is_Block(node)) {
/* fill the Proj -> Block map */
for (i = get_Block_n_cfgpreds(node) - 1; i >= 0; --i) {
tarval *tv, *tv_l, *tv_h;
ir_node *low, *high;
dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
int idx;
ir_graph *irg = current_ir_graph;
ir_mode *low_mode = env->params->low_unsigned;
tv = get_Const_tarval(node);
tv_l = tarval_convert_to(tv, low_mode);
- low = new_rd_Const(dbg, irg, block, low_mode, tv_l);
+ low = new_rd_Const(dbg, irg, tv_l);
tv_h = tarval_convert_to(tarval_shrs(tv, env->tv_mode_bits), mode);
- high = new_rd_Const(dbg, irg, block, mode, tv_h);
+ high = new_rd_Const(dbg, irg, tv_h);
idx = get_irn_idx(node);
assert(idx < env->n_entries);
* Translate a Load: create two.
*/
static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_mode *low_mode = env->params->low_unsigned;
- ir_graph *irg = current_ir_graph;
- ir_node *adr = get_Load_ptr(node);
- ir_node *mem = get_Load_mem(node);
- ir_node *low, *high, *proj;
- dbg_info *dbg;
- ir_node *block = get_nodes_block(node);
- int idx;
+ ir_mode *low_mode = env->params->low_unsigned;
+ ir_graph *irg = current_ir_graph;
+ ir_node *adr = get_Load_ptr(node);
+ ir_node *mem = get_Load_mem(node);
+ ir_node *low, *high, *proj;
+ dbg_info *dbg;
+ ir_node *block = get_nodes_block(node);
+ int idx;
+ ir_cons_flags volatility = get_Load_volatility(node) == volatility_is_volatile
+ ? cons_volatile : 0;
if (env->params->little_endian) {
low = adr;
high = new_r_Add(irg, block, adr,
- new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
+ new_r_Const(irg, env->tv_mode_bytes),
get_irn_mode(adr));
} else {
low = new_r_Add(irg, block, adr,
- new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
+ new_r_Const(irg, env->tv_mode_bytes),
get_irn_mode(adr));
high = adr;
} /* if */
/* create two loads */
dbg = get_irn_dbg_info(node);
- low = new_rd_Load(dbg, irg, block, mem, low, low_mode);
+ low = new_rd_Load(dbg, irg, block, mem, low, low_mode, volatility);
proj = new_r_Proj(irg, block, low, mode_M, pn_Load_M);
- high = new_rd_Load(dbg, irg, block, proj, high, mode);
-
- set_Load_volatility(low, get_Load_volatility(node));
- set_Load_volatility(high, get_Load_volatility(node));
+ high = new_rd_Load(dbg, irg, block, proj, high, mode, volatility);
idx = get_irn_idx(node);
assert(idx < env->n_entries);
* Translate a Store: create two.
*/
static void lower_Store(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_graph *irg;
- ir_node *block, *adr, *mem;
- ir_node *low, *high, *irn, *proj;
- dbg_info *dbg;
- int idx;
+ ir_graph *irg;
+ ir_node *block, *adr, *mem;
+ ir_node *low, *high, *irn, *proj;
+ dbg_info *dbg;
+ int idx;
node_entry_t *entry;
- (void) node;
+ ir_cons_flags volatility = get_Store_volatility(node) == volatility_is_volatile
+ ? cons_volatile : 0;
(void) mode;
irn = get_Store_value(node);
if (env->params->little_endian) {
low = adr;
high = new_r_Add(irg, block, adr,
- new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
+ new_r_Const(irg, env->tv_mode_bytes),
get_irn_mode(adr));
} else {
low = new_r_Add(irg, block, adr,
- new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
+ new_r_Const(irg, env->tv_mode_bytes),
get_irn_mode(adr));
high = adr;
} /* if */
/* create two Stores */
dbg = get_irn_dbg_info(node);
- low = new_rd_Store(dbg, irg, block, mem, low, entry->low_word);
+ low = new_rd_Store(dbg, irg, block, mem, low, entry->low_word, volatility);
proj = new_r_Proj(irg, block, low, mode_M, pn_Store_M);
- high = new_rd_Store(dbg, irg, block, proj, high, entry->high_word);
-
- set_Store_volatility(low, get_Store_volatility(node));
- set_Store_volatility(high, get_Store_volatility(node));
+ high = new_rd_Store(dbg, irg, block, proj, high, entry->high_word, volatility);
idx = get_irn_idx(node);
assert(idx < env->n_entries);
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shr_left(node);
ir_node *c;
idx = get_irn_idx(node);
if (shf_cnt > 0) {
- c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
+ c = new_r_Const_long(irg, env->params->low_unsigned, shf_cnt);
env->entries[idx]->low_word = new_r_Shr(irg, block, left, c, mode);
} else {
env->entries[idx]->low_word = left;
} /* if */
- env->entries[idx]->high_word = new_r_Const(irg, block, mode, get_mode_null(mode));
+ env->entries[idx]->high_word = new_r_Const(irg, get_mode_null(mode));
return;
} /* if */
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_mode *mode_l;
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shl_left(node);
left = new_r_Conv(irg, block, env->entries[idx]->low_word, mode);
idx = get_irn_idx(node);
+ mode_l = env->params->low_unsigned;
if (shf_cnt > 0) {
- c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
+ c = new_r_Const_long(irg, mode_l, shf_cnt);
env->entries[idx]->high_word = new_r_Shl(irg, block, left, c, mode);
} else {
env->entries[idx]->high_word = left;
} /* if */
- mode_l = env->params->low_unsigned;
- env->entries[idx]->low_word = new_r_Const(irg, block, mode_l, get_mode_null(mode_l));
+ env->entries[idx]->low_word = new_r_Const(irg, get_mode_null(mode_l));
return;
} /* if */
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) {
- ir_node *block = get_nodes_block(node);
- ir_node *left = get_Shrs_left(node);
- long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
+ ir_node *block = get_nodes_block(node);
+ ir_node *left = get_Shrs_left(node);
+ long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
+ int idx = get_irn_idx(left);
+ ir_mode *mode_l;
+ ir_node *low;
ir_node *c;
- int idx = get_irn_idx(left);
left = env->entries[idx]->high_word;
idx = get_irn_idx(node);
+ mode_l = env->params->low_unsigned;
if (shf_cnt > 0) {
- c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
- env->entries[idx]->low_word = new_r_Shrs(irg, block, left, c, mode);
+ c = new_r_Const_long(irg, mode_l, shf_cnt);
+ low = new_r_Shrs(irg, block, left, c, mode);
} else {
- env->entries[idx]->low_word = left;
+ low = left;
} /* if */
- c = new_r_Const_long(irg, block, mode_Iu, get_mode_size_bits(mode) - 1);
+ /* low word is expected to have mode_l */
+ env->entries[idx]->low_word = new_r_Conv(irg, block, low, mode_l);
+
+ c = new_r_Const_long(irg, mode_l, get_mode_size_bits(mode) - 1);
env->entries[idx]->high_word = new_r_Shrs(irg, block, left, c, mode);
return;
} /* lower_Shrs */
/**
- * Translate a Rot and handle special cases.
+ * Rebuild Rotl nodes into Or(Shl, Shr) and prepare all nodes.
*/
-static void lower_Rot(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_node *right = get_Rot_right(node);
-
- if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
+static void prepare_links_and_handle_rotl(ir_node *node, void *env) {
+ lower_env_t *lenv = env;
+
+ if (is_Rotl(node)) {
+ ir_mode *mode = get_irn_op_mode(node);
+ if (mode == lenv->params->high_signed ||
+ mode == lenv->params->high_unsigned) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left, *shl, *shr, *or, *block, *sub, *c;
+ ir_mode *omode, *rmode;
+ ir_graph *irg;
+ dbg_info *dbg;
+ optimization_state_t state;
+
+ if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
+ tarval *tv = get_Const_tarval(right);
+
+ if (tarval_is_long(tv) &&
+ get_tarval_long(tv) == (long)get_mode_size_bits(mode)) {
+ /* will be optimized in lower_Rotl() */
+ return;
+ }
+ }
+
+ /* replace the Rotl(x,y) by an Or(Shl(x,y), Shr(x,64-y)) and lower those */
+ dbg = get_irn_dbg_info(node);
+ omode = get_irn_mode(node);
+ left = get_Rotl_left(node);
+ irg = current_ir_graph;
+ block = get_nodes_block(node);
+ shl = new_rd_Shl(dbg, irg, block, left, right, omode);
+ rmode = get_irn_mode(right);
+ c = new_Const_long(rmode, get_mode_size_bits(omode));
+ sub = new_rd_Sub(dbg, irg, block, c, right, rmode);
+ shr = new_rd_Shr(dbg, irg, block, left, sub, omode);
+
+ /* optimization must be switched off here, or we will get the Rotl back */
+ save_optimization_state(&state);
+ set_opt_algebraic_simplification(0);
+ or = new_rd_Or(dbg, irg, block, shl, shr, omode);
+ restore_optimization_state(&state);
+
+ exchange(node, or);
+
+ /* do lowering on the new nodes */
+ prepare_links(shl, env);
+ prepare_links(c, env);
+ prepare_links(sub, env);
+ prepare_links(shr, env);
+ prepare_links(or, env);
+ }
+ } else {
+ prepare_links(node, env);
+ }
+}
- if (tarval_is_long(tv) &&
- get_tarval_long(tv) == (int) get_mode_size_bits(mode)) {
- ir_node *left = get_Rot_left(node);
- ir_node *h, *l;
- int idx = get_irn_idx(left);
+/**
+ * Translate a special case Rotl(x, sizeof(w)).
+ */
+static void lower_Rotl(ir_node *node, ir_mode *mode, lower_env_t *env) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left = get_Rotl_left(node);
+ ir_node *h, *l;
+ int idx = get_irn_idx(left);
+ (void) right;
+ (void) mode;
- l = env->entries[idx]->low_word;
- h = env->entries[idx]->high_word;
- idx = get_irn_idx(node);
+ assert(get_mode_arithmetic(mode) == irma_twos_complement &&
+ is_Const(right) && tarval_is_long(get_Const_tarval(right)) &&
+ get_tarval_long(get_Const_tarval(right)) == (long)get_mode_size_bits(mode));
- env->entries[idx]->low_word = h;
- env->entries[idx]->high_word = l;
+ l = env->entries[idx]->low_word;
+ h = env->entries[idx]->high_word;
+ idx = get_irn_idx(node);
- return;
- } /* if */
- } /* if */
- lower_Shiftop(node, mode, env);
-} /* lower_Rot */
+ env->entries[idx]->low_word = h;
+ env->entries[idx]->high_word = l;
+} /* lower_Rotl */
/**
* Translate an Unop.
env->entries[idx]->high_word = constr_rd(dbg, irg, block, lop_h, rop_h, mode);
} /* lower_Binop_logical */
-/** create a logical operation tranformation */
+/** create a logical operation transformation */
#define lower_logical(op) \
static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \
lower_Binop_logical(node, mode, env, new_rd_##op); \
if (mode_is_signed(imode)) {
ir_node *op_conv = new_rd_Conv(dbg, irg, block, op, dst_mode_h);
env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op_conv,
- new_Const_long(mode_Iu, get_mode_size_bits(dst_mode_h) - 1), dst_mode_h);
+ new_Const_long(dst_mode_l, get_mode_size_bits(dst_mode_h) - 1), dst_mode_h);
} else {
- env->entries[idx]->high_word = new_Const(dst_mode_h, get_mode_null(dst_mode_h));
+ env->entries[idx]->high_word = new_Const(get_mode_null(dst_mode_h));
} /* if */
} /* if */
} else {
if (mode_is_signed(imode)) {
env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
- new_Const_long(mode_Iu, get_mode_size_bits(dst_mode) - 1), dst_mode);
+ new_Const_long(dst_mode, get_mode_size_bits(dst_mode) - 1), dst_mode);
} else {
- env->entries[idx]->high_word = new_Const(dst_mode, get_mode_null(dst_mode));
+ env->entries[idx]->high_word = new_Const(get_mode_null(dst_mode));
} /* if */
} /* if */
} else {
/**
* Lower the method type.
+ *
+ * @param mtp the method type to lower
+ * @param ent the lower environment
+ *
+ * @return the lowered type
*/
static ir_type *lower_mtp(ir_type *mtp, lower_env_t *env) {
pmap_entry *entry;
- ident *id;
- ir_type *res;
+ ident *id, *lid;
+ ir_type *res, *value_type;
if (is_lowered_type(mtp))
return mtp;
} /* if */
} /* for */
- id = mangle_u(new_id_from_chars("L", 1), get_type_ident(mtp));
+ id = id_mangle_u(new_id_from_chars("L", 1), get_type_ident(mtp));
res = new_type_method(id, n_param, n_res);
/* set param types and result types */
} /* for */
set_lowered_type(mtp, res);
pmap_insert(lowered_type, mtp, res);
+
+ value_type = get_method_value_param_type(mtp);
+ if (value_type != NULL) {
+ /* this creates a new value parameter type */
+ (void)get_method_value_param_ent(res, 0);
+
+ /* set new param positions */
+ for (i = n_param = 0; i < n; ++i) {
+ ir_type *tp = get_method_param_type(mtp, i);
+ ident *id = get_method_param_ident(mtp, i);
+ ir_entity *ent = get_method_value_param_ent(mtp, i);
+
+ set_entity_link(ent, INT_TO_PTR(n_param));
+ if (is_Primitive_type(tp)) {
+ ir_mode *mode = get_type_mode(tp);
+
+ if (mode == env->params->high_signed || mode == env->params->high_unsigned) {
+ if (id != NULL) {
+ lid = id_mangle(id, env->first_id);
+ set_method_param_ident(res, n_param, lid);
+ set_entity_ident(get_method_value_param_ent(res, n_param), lid);
+ lid = id_mangle(id, env->next_id);
+ set_method_param_ident(res, n_param + 1, lid);
+ set_entity_ident(get_method_value_param_ent(res, n_param + 1), lid);
+ } /* if */
+ n_param += 2;
+ continue;
+ } /* if */
+ } /* if */
+ if (id != NULL) {
+ set_method_param_ident(res, n_param, id);
+ set_entity_ident(get_method_value_param_ent(res, n_param), id);
+ } /* if */
+ ++n_param;
+ } /* for */
+
+ set_lowered_type(value_type, get_method_value_param_type(res));
+ } /* if */
} else {
res = entry->value;
} /* if */
env->entries[idx]->low_word = phi_l = new_rd_Phi(dbg, irg, block, arity, inl, mode_l);
env->entries[idx]->high_word = phi_h = new_rd_Phi(dbg, irg, block, arity, inh, mode);
- /* Don't forget to link the new Phi nodes into the block! */
- set_irn_link(phi_l, get_irn_link(block));
- set_irn_link(phi_h, phi_l);
- set_irn_link(block, phi_h);
+ /* Don't forget to link the new Phi nodes into the block.
+ * Beware that some Phis might be optimized away. */
+ if (is_Phi(phi_l))
+ add_Block_phi(block, phi_l);
+ if (is_Phi(phi_h))
+ add_Block_phi(block, phi_h);
if (enq) {
/* not yet finished */
} /* lower_Phi */
/**
- * Translate a Psi.
+ * Translate a Mux.
*/
-static void lower_Psi(ir_node *psi, ir_mode *mode, lower_env_t *env) {
+static void lower_Mux(ir_node *mux, ir_mode *mode, lower_env_t *env) {
ir_graph *irg = current_ir_graph;
ir_node *block, *val;
- ir_node **valsl, **valsh, **conds;
+ ir_node *true_l, *true_h, *false_l, *false_h, *sel;
dbg_info *dbg;
- int idx, i, n_conds = get_Psi_n_conds(psi);
+ int idx;
- /* first create a new in array */
- NEW_ARR_A(ir_node *, valsl, n_conds + 1);
- NEW_ARR_A(ir_node *, valsh, n_conds + 1);
+ val = get_Mux_true(mux);
+ idx = get_irn_idx(val);
+ if (env->entries[idx]->low_word) {
+ /* Values already build */
+ true_l = env->entries[idx]->low_word;
+ true_h = env->entries[idx]->high_word;
+ } else {
+ /* still not ready */
+ pdeq_putr(env->waitq, mux);
+ return;
+ } /* if */
- for (i = 0; i < n_conds; ++i) {
- val = get_Psi_val(psi, i);
- idx = get_irn_idx(val);
- if (env->entries[idx]->low_word) {
- /* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
- } else {
- /* still not ready */
- pdeq_putr(env->waitq, psi);
- return;
- } /* if */
- } /* for */
- val = get_Psi_default(psi);
+ val = get_Mux_false(mux);
idx = get_irn_idx(val);
if (env->entries[idx]->low_word) {
/* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
+ false_l = env->entries[idx]->low_word;
+ false_h = env->entries[idx]->high_word;
} else {
/* still not ready */
- pdeq_putr(env->waitq, psi);
+ pdeq_putr(env->waitq, mux);
return;
} /* if */
- NEW_ARR_A(ir_node *, conds, n_conds);
- for (i = 0; i < n_conds; ++i) {
- conds[i] = get_Psi_cond(psi, i);
- } /* for */
+ sel = get_Mux_sel(mux);
- dbg = get_irn_dbg_info(psi);
- block = get_nodes_block(psi);
+ dbg = get_irn_dbg_info(mux);
+ block = get_nodes_block(mux);
- idx = get_irn_idx(psi);
+ idx = get_irn_idx(mux);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsl, mode);
- env->entries[idx]->high_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsh, mode);
-} /* lower_Psi */
+ env->entries[idx]->low_word = new_rd_Mux(dbg, irg, block, sel, false_l, true_l, mode);
+ env->entries[idx]->high_word = new_rd_Mux(dbg, irg, block, sel, false_h, true_h, mode);
+} /* lower_Mux */
+
+/**
+ * Translate an ASM node.
+ */
+static void lower_ASM(ir_node *asmn, ir_mode *mode, lower_env_t *env) {
+ ir_mode *his = env->params->high_signed;
+ ir_mode *hiu = env->params->high_unsigned;
+ int i;
+ ir_node *n;
+
+ (void)mode;
+
+ for (i = get_irn_arity(asmn) - 1; i >= 0; --i) {
+ ir_mode *op_mode = get_irn_mode(get_irn_n(asmn, i));
+ if (op_mode == his || op_mode == hiu) {
+ panic("lowering ASM unimplemented");
+ } /* if */
+ } /* for */
+
+ for (n = asmn;;) {
+ ir_mode *proj_mode;
+
+ n = get_irn_link(n);
+ if (n == NULL)
+ break;
+
+ proj_mode = get_irn_mode(n);
+ if (proj_mode == his || proj_mode == hiu) {
+ panic("lowering ASM unimplemented");
+ } /* if */
+ } /* for */
+} /* lower_ASM */
+
+/**
+ * Translate a Sel node.
+ */
+static void lower_Sel(ir_node *sel, ir_mode *mode, lower_env_t *env) {
+ (void) mode;
+
+ /* we must only lower value parameter Sels if we change the
+ value parameter type. */
+ if (env->value_param_tp != NULL) {
+ ir_entity *ent = get_Sel_entity(sel);
+ if (get_entity_owner(ent) == env->value_param_tp) {
+ int pos = PTR_TO_INT(get_entity_link(ent));
+
+ ent = get_method_value_param_ent(env->l_mtp, pos);
+ set_Sel_entity(sel, ent);
+ } /* if */
+ } /* if */
+} /* lower_Sel */
/**
* check for opcodes that must always be lowered.
*/
static int always_lower(ir_opcode code) {
switch (code) {
+ case iro_ASM:
case iro_Proj:
case iro_Start:
case iro_Call:
case iro_Return:
case iro_Cond:
case iro_Conv:
+ case iro_Sel:
return 1;
default:
return 0;
int idx = get_irn_idx(node);
ir_mode *mode = get_irn_mode(node);
- if (mode == mode_b || is_Psi(node)) {
+ if (mode == mode_b || is_Mux(node) || is_Conv(node)) {
int i;
for (i = get_irn_arity(node) - 1; i >= 0; --i) {
(void) size;
return (e1->imode - e2->imode) | (e1->omode - e2->omode);
-} /* static int cmp_conv_tp */
+} /* cmp_conv_tp */
/**
* Enter a lowering function into an ir_op.
*/
static void enter_lower_func(ir_op *op, lower_func func) {
op->ops.generic = (op_func)func;
-}
+} /* enter_lower_func */
+
+/**
+ * Returns non-zero if a method type must be lowered.
+ *
+ * @param mtp the method type
+ */
+static int mtp_must_to_lowered(ir_type *mtp, lower_env_t *env) {
+ int i, n_params;
+
+ n_params = get_method_n_params(mtp);
+ if (n_params <= 0)
+ return 0;
+
+ /* first check if we have parameters that must be fixed */
+ for (i = 0; i < n_params; ++i) {
+ ir_type *tp = get_method_param_type(mtp, i);
+
+ if (is_Primitive_type(tp)) {
+ ir_mode *mode = get_type_mode(tp);
+
+ if (mode == env->params->high_signed ||
+ mode == env->params->high_unsigned)
+ return 1;
+ } /* if */
+ } /* for */
+ return 0;
+} /* mtp_must_to_lowered */
/*
* Do the lowering.
void lower_dw_ops(const lwrdw_param_t *param)
{
lower_env_t lenv;
- int i;
- ir_graph *rem;
+ int i;
+ ir_graph *rem;
if (! param)
return;
if (! prim_types)
prim_types = pmap_create();
if (! intrinsic_fkt)
- intrinsic_fkt = new_set(cmp_op_mode, iro_Last);
+ intrinsic_fkt = new_set(cmp_op_mode, iro_Last + 1);
if (! conv_types)
conv_types = new_set(cmp_conv_tp, 16);
if (! lowered_type)
shiftop_tp_s = new_type_method(IDENT("shiftop_s_intrinsic"), 3, 2);
set_method_param_type(shiftop_tp_s, 0, tp_u);
set_method_param_type(shiftop_tp_s, 1, tp_s);
- /* beware: shift count is always mode_Iu */
set_method_param_type(shiftop_tp_s, 2, tp_u);
set_method_res_type(shiftop_tp_s, 0, tp_u);
set_method_res_type(shiftop_tp_s, 1, tp_s);
set_method_res_type(unop_tp_s, 1, tp_s);
} /* if */
- lenv.tv_mode_bytes = new_tarval_from_long(get_mode_size_bytes(param->low_unsigned), mode_Iu);
- lenv.tv_mode_bits = new_tarval_from_long(get_mode_size_bits(param->low_unsigned), mode_Iu);
+ lenv.tv_mode_bytes = new_tarval_from_long(get_mode_size_bytes(param->low_unsigned), param->low_unsigned);
+ lenv.tv_mode_bits = new_tarval_from_long(get_mode_size_bits(param->low_unsigned), param->low_unsigned);
lenv.waitq = new_pdeq();
lenv.params = param;
+ lenv.first_id = new_id_from_chars(param->little_endian ? ".l" : ".h", 2);
+ lenv.next_id = new_id_from_chars(param->little_endian ? ".h" : ".l", 2);
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
#define LOWER_UN(op) LOWER2(op, lower_Unop)
/* the table of all operations that must be lowered follows */
+ LOWER(ASM);
LOWER(Load);
LOWER(Store);
LOWER(Const);
LOWER(Call);
LOWER(Unknown);
LOWER(Phi);
- LOWER(Psi);
+ LOWER(Mux);
LOWER(Start);
LOWER_BIN(Add);
LOWER(Shl);
LOWER(Shr);
LOWER(Shrs);
- LOWER(Rot);
+ LOWER(Rotl);
LOWER(DivMod);
LOWER(Div);
LOWER(Mod);
+ LOWER(Sel);
LOWER_UN(Abs);
LOWER_UN(Minus);
/* transform all graphs */
rem = current_ir_graph;
for (i = get_irp_n_irgs() - 1; i >= 0; --i) {
- ir_graph *irg = get_irp_irg(i);
+ ir_graph *irg = get_irp_irg(i);
+ ir_entity *ent;
+ ir_type *mtp;
int n_idx;
obstack_init(&lenv.obst);
n_idx = get_irg_last_idx(irg);
+ n_idx = n_idx + (n_idx >> 2); /* add 25% */
lenv.n_entries = n_idx;
- lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0]));
+ lenv.entries = NEW_ARR_F(node_entry_t *, n_idx);
memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0]));
- /* first step: link all nodes and allocate data */
- lenv.flags = 0;
+ lenv.l_mtp = NULL;
+ lenv.flags = 0;
lenv.proj_2_block = pmap_create();
- irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv);
+ lenv.value_param_tp = NULL;
+ ir_reserve_resources(irg, IR_RESOURCE_PHI_LIST | IR_RESOURCE_IRN_LINK);
+
+ ent = get_irg_entity(irg);
+ mtp = get_entity_type(ent);
+
+ if (mtp_must_to_lowered(mtp, &lenv)) {
+ ir_type *ltp = lower_mtp(mtp, &lenv);
+ lenv.flags |= MUST_BE_LOWERED;
+ set_entity_type(ent, ltp);
+ lenv.l_mtp = ltp;
+ lenv.value_param_tp = get_method_value_param_type(mtp);
+ } /* if */
+
+ /* first step: link all nodes and allocate data */
+ irg_walk_graph(irg, firm_clear_node_and_phi_links, prepare_links_and_handle_rotl, &lenv);
if (lenv.flags & MUST_BE_LOWERED) {
DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg));
lower_ops(node, &lenv);
} /* while */
+ ir_free_resources(irg, IR_RESOURCE_PHI_LIST | IR_RESOURCE_IRN_LINK);
+
/* outs are invalid, we changed the graph */
set_irg_outs_inconsistent(irg);
set_irg_extblk_inconsistent(irg);
set_irg_loopinfo_inconsistent(irg);
} /* if */
+ } else {
+ ir_free_resources(irg, IR_RESOURCE_PHI_LIST | IR_RESOURCE_IRN_LINK);
} /* if */
pmap_destroy(lenv.proj_2_block);
- free(lenv.entries);
+ DEL_ARR_F(lenv.entries);
obstack_free(&lenv.obst, NULL);
} /* for */
del_pdeq(lenv.waitq);
projects / libfirm / blobdiff