/*
- * Project: libFIRM
- * File name: ir/lower/lower_dw.c
- * Purpose: Lower Double word operations, ie Mode L -> I.
- * Author: Michael Beck
- * Created: 8.10.2004
- * CVS-ID: $Id$
- * Copyright: (c) 1998-2006 Universität Karlsruhe
- * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
+/**
+ * @file
+ * @brief Lower Double word operations, ie 64bit -> 32bit, 32bit -> 16bit etc.
+ * @date 8.10.2004
+ * @author Michael Beck
+ * @version $Id$
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#include <assert.h>
+#include "error.h"
+#include "lowering.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
#include "firmstat.h"
#include "irgwalk.h"
#include "ircons.h"
-#include "lower_dw.h"
#include "irflag.h"
#include "irtools.h"
#include "debug.h"
#include "pmap.h"
#include "pdeq.h"
#include "irdump.h"
-#include "xmalloc.h"
+#include "array_t.h"
/** A map from mode to a primitive type. */
static pmap *prim_types;
/* set param types and result types */
n_param = 0;
if (imode == env->params->high_signed) {
- set_method_param_type(mtd, n_param++, tp_s);
+ set_method_param_type(mtd, n_param++, tp_u);
set_method_param_type(mtd, n_param++, tp_s);
} else if (imode == env->params->high_unsigned) {
set_method_param_type(mtd, n_param++, tp_u);
n_res = 0;
if (omode == env->params->high_signed) {
- set_method_res_type(mtd, n_res++, tp_s);
+ set_method_res_type(mtd, n_res++, tp_u);
set_method_res_type(mtd, n_res++, tp_s);
} else if (omode == env->params->high_unsigned) {
set_method_res_type(mtd, n_res++, tp_u);
lower_env_t *lenv = env;
ir_mode *mode = get_irn_op_mode(node);
node_entry_t *link;
- int i;
+ int i, idx;
if (mode == lenv->params->high_signed ||
mode == lenv->params->high_unsigned) {
memset(link, 0, sizeof(*link));
- lenv->entries[get_irn_idx(node)] = link;
+ idx = get_irn_idx(node);
+ if (idx >= lenv->n_entries) {
+ /* enlarge: this happens only for Rotl nodes which is RARELY */
+ int old = lenv->n_entries;
+ int n_idx = idx + (idx >> 3);
+
+ ARR_RESIZE(node_entry_t *, lenv->entries, n_idx);
+ memset(&lenv->entries[old], 0, (n_idx - old) * sizeof(lenv->entries[0]));
+ lenv->n_entries = n_idx;
+ }
+ lenv->entries[idx] = link;
lenv->flags |= MUST_BE_LOWERED;
- } else if (get_irn_op(node) == op_Conv) {
+ } else if (is_Conv(node)) {
/* Conv nodes have two modes */
ir_node *pred = get_Conv_op(node);
mode = get_irn_mode(pred);
ir_node *block = get_nodes_block(node);
int idx;
ir_graph *irg = current_ir_graph;
+ ir_mode *low_mode = env->params->low_unsigned;
tv = get_Const_tarval(node);
- tv_l = tarval_convert_to(tv, mode);
- low = new_rd_Const(dbg, irg, block, mode, tv_l);
+ tv_l = tarval_convert_to(tv, low_mode);
+ low = new_rd_Const(dbg, irg, block, low_mode, tv_l);
tv_h = tarval_convert_to(tarval_shrs(tv, env->tv_mode_bits), mode);
high = new_rd_Const(dbg, irg, block, mode, tv_h);
* Translate a Load: create two.
*/
static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env) {
+ ir_mode *low_mode = env->params->low_unsigned;
ir_graph *irg = current_ir_graph;
ir_node *adr = get_Load_ptr(node);
ir_node *mem = get_Load_mem(node);
/* create two loads */
dbg = get_irn_dbg_info(node);
- low = new_rd_Load(dbg, irg, block, mem, low, mode);
+ low = new_rd_Load(dbg, irg, block, mem, low, low_mode);
proj = new_r_Proj(irg, block, low, mode_M, pn_Load_M);
high = new_rd_Load(dbg, irg, block, proj, high, mode);
break;
case pn_Load_res: /* Result of load operation. */
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, low, mode, pn_Load_res);
- env->entries[idx]->high_word = new_r_Proj(irg, block, high, mode, pn_Load_res);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, low, low_mode, pn_Load_res);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, high, mode, pn_Load_res);
break;
default:
assert(0 && "unexpected Proj number");
dbg_info *dbg;
int idx;
node_entry_t *entry;
+ (void) node;
+ (void) mode;
irn = get_Store_value(node);
entry = env->entries[get_irn_idx(irn)];
ent = entry->ent;
} /* if */
sym.entity_p = ent;
- return new_r_SymConst(current_ir_graph, block, sym, symconst_addr_ent);
+ return new_r_SymConst(current_ir_graph, block, mode_P_code, sym, symconst_addr_ent);
} /* get_intrinsic_address */
/**
case pn_Div_res: /* Result of computation. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
break;
default:
assert(0 && "unexpected Proj number");
case pn_Mod_res: /* Result of computation. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, irn, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
break;
default:
assert(0 && "unexpected Proj number");
case pn_DivMod_res_div: /* Result of Div. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, resDiv, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, resDiv, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, resDiv, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, resDiv, mode, 1);
break;
case pn_DivMod_res_mod: /* Result of Mod. */
idx = get_irn_idx(proj);
- env->entries[idx]->low_word = new_r_Proj(irg, block, resMod, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, resMod, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, resMod, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, resMod, mode, 1);
break;
default:
assert(0 && "unexpected Proj number");
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, irn, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
} /* lower_Binop */
/**
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, irn, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
} /* lower_Shiftop */
/**
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shr_left(node);
ir_node *c;
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
+ ir_mode *mode_l;
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shl_left(node);
ir_node *c;
long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
int idx = get_irn_idx(left);
- left = env->entries[idx]->low_word;
+ left = new_r_Conv(irg, block, env->entries[idx]->low_word, mode);
idx = get_irn_idx(node);
if (shf_cnt > 0) {
} else {
env->entries[idx]->high_word = left;
} /* if */
- env->entries[idx]->low_word = new_r_Const(irg, block, mode, get_mode_null(mode));
+ mode_l = env->params->low_unsigned;
+ env->entries[idx]->low_word = new_r_Const(irg, block, mode_l, get_mode_null(mode_l));
return;
} /* if */
tarval *tv = get_Const_tarval(right);
if (tarval_is_long(tv) &&
- get_tarval_long(tv) >= get_mode_size_bits(mode)) {
- ir_node *block = get_nodes_block(node);
- ir_node *left = get_Shrs_left(node);
- long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
+ get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
+ ir_node *block = get_nodes_block(node);
+ ir_node *left = get_Shrs_left(node);
+ long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
+ int idx = get_irn_idx(left);
+ ir_node *low;
ir_node *c;
- int idx = get_irn_idx(left);
left = env->entries[idx]->high_word;
idx = get_irn_idx(node);
if (shf_cnt > 0) {
- c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
- env->entries[idx]->low_word = new_r_Shrs(irg, block, left, c, mode);
+ c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
+ low = new_r_Shrs(irg, block, left, c, mode);
} else {
- env->entries[idx]->low_word = left;
+ low = left;
} /* if */
+ /* low word is expected to have mode_Iu */
+ env->entries[idx]->low_word = new_r_Conv(irg, block, low, mode_Iu);
+
c = new_r_Const_long(irg, block, mode_Iu, get_mode_size_bits(mode) - 1);
env->entries[idx]->high_word = new_r_Shrs(irg, block, left, c, mode);
} /* lower_Shrs */
/**
- * Translate a Rot and handle special cases.
+ * Rebuild Rotl nodes into Or(Shl, Shr) and prepare all nodes.
*/
-static void lower_Rot(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_node *right = get_Rot_right(node);
-
- if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
-
- if (tarval_is_long(tv) &&
- get_tarval_long(tv) == get_mode_size_bits(mode)) {
- ir_node *left = get_Rot_left(node);
- ir_node *h, *l;
- int idx = get_irn_idx(left);
-
- l = env->entries[idx]->low_word;
- h = env->entries[idx]->high_word;
- idx = get_irn_idx(node);
+static void prepare_links_and_handle_rotl(ir_node *node, void *env) {
+ lower_env_t *lenv = env;
+
+ if (is_Rotl(node)) {
+ ir_mode *mode = get_irn_op_mode(node);
+ if (mode == lenv->params->high_signed ||
+ mode == lenv->params->high_unsigned) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left, *shl, *shr, *or, *block, *sub, *c;
+ ir_mode *omode, *rmode;
+ ir_graph *irg;
+ dbg_info *dbg;
+ optimization_state_t state;
+
+ if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
+ tarval *tv = get_Const_tarval(right);
+
+ if (tarval_is_long(tv) &&
+ get_tarval_long(tv) == (long)get_mode_size_bits(mode)) {
+ /* will be optimized in lower_Rotl() */
+ return;
+ }
+ }
+
+ /* replace the Rotl(x,y) by an Or(Shl(x,y), Shr(x,64-y)) and lower those */
+ dbg = get_irn_dbg_info(node);
+ omode = get_irn_mode(node);
+ left = get_Rotl_left(node);
+ irg = current_ir_graph;
+ block = get_nodes_block(node);
+ shl = new_rd_Shl(dbg, irg, block, left, right, omode);
+ rmode = get_irn_mode(right);
+ c = new_Const_long(rmode, get_mode_size_bits(omode));
+ sub = new_rd_Sub(dbg, irg, block, c, right, rmode);
+ shr = new_rd_Shr(dbg, irg, block, left, sub, omode);
+
+ /* optimization must be switched off here, or we will get the Rotl back */
+ save_optimization_state(&state);
+ set_opt_algebraic_simplification(0);
+ or = new_rd_Or(dbg, irg, block, shl, shr, omode);
+ restore_optimization_state(&state);
+
+ exchange(node, or);
+
+ /* do lowering on the new nodes */
+ prepare_links(shl, env);
+ prepare_links(c, env);
+ prepare_links(sub, env);
+ prepare_links(shr, env);
+ prepare_links(or, env);
+ }
+ } else {
+ prepare_links(node, env);
+ }
+}
- env->entries[idx]->low_word = h;
- env->entries[idx]->high_word = l;
+/**
+ * Translate a special case Rotl(x, sizeof(w)).
+ */
+static void lower_Rotl(ir_node *node, ir_mode *mode, lower_env_t *env) {
+ ir_node *right = get_Rotl_right(node);
+ ir_node *left = get_Rotl_left(node);
+ ir_node *h, *l;
+ int idx = get_irn_idx(left);
+ (void) right;
+ (void) mode;
+
+ assert(get_mode_arithmetic(mode) == irma_twos_complement &&
+ is_Const(right) && tarval_is_long(get_Const_tarval(right)) &&
+ get_tarval_long(get_Const_tarval(right)) == (long)get_mode_size_bits(mode));
+
+ l = env->entries[idx]->low_word;
+ h = env->entries[idx]->high_word;
+ idx = get_irn_idx(node);
- return;
- } /* if */
- } /* if */
- lower_Shiftop(node, mode, env);
-} /* lower_Rot */
+ env->entries[idx]->low_word = h;
+ env->entries[idx]->high_word = l;
+} /* lower_Rotl */
/**
* Translate an Unop.
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irg, block, irn, mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
} /* lower_Unop */
/**
idx = get_irn_idx(node);
assert(idx < env->n_entries);
irg = current_ir_graph;
- env->entries[idx]->low_word = constr_rd(dbg, irg, block, lop_l, rop_l, mode);
+ env->entries[idx]->low_word = constr_rd(dbg, irg, block, lop_l, rop_l, env->params->low_unsigned);
env->entries[idx]->high_word = constr_rd(dbg, irg, block, lop_h, rop_h, mode);
} /* lower_Binop_logical */
-/** create a logical operation tranformation */
+/** create a logical operation transformation */
#define lower_logical(op) \
static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \
lower_Binop_logical(node, mode, env, new_rd_##op); \
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Not(dbg, current_ir_graph, block, op_l, mode);
+ env->entries[idx]->low_word = new_rd_Not(dbg, current_ir_graph, block, op_l, env->params->low_unsigned);
env->entries[idx]->high_word = new_rd_Not(dbg, current_ir_graph, block, op_h, mode);
} /* lower_Not */
-/**
- * Translate a Minus.
- *
- * Create two Minus'.
- */
-static void lower_Minus(ir_node *node, ir_mode *mode, lower_env_t *env) {
- ir_node *block, *irn;
- ir_node *op_l, *op_h;
- dbg_info *dbg;
- int idx;
- ir_graph *irg;
- node_entry_t *entry;
-
- irn = get_Minus_op(node);
- entry = env->entries[get_irn_idx(irn)];
- assert(entry);
-
- if (! entry->low_word) {
- /* not ready yet, wait */
- pdeq_putr(env->waitq, node);
- return;
- } /* if */
-
- op_l = entry->low_word;
- op_h = entry->high_word;
-
- dbg = get_irn_dbg_info(node);
- block = get_nodes_block(node);
- irg = current_ir_graph;
-
- idx = get_irn_idx(node);
- assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Minus(dbg, current_ir_graph, block, op_l, mode);
- env->entries[idx]->high_word = new_rd_Minus(dbg, current_ir_graph, block, op_h, mode);
-} /* lower_Minus */
-
/**
* Translate a Cond.
*/
ir_node *sel = get_Cond_selector(node);
ir_mode *m = get_irn_mode(sel);
int idx;
+ (void) mode;
if (m == mode_b) {
node_entry_t *lentry, *rentry;
pn_Cmp pnc;
dbg_info *dbg;
+ if(!is_Proj(sel))
+ return;
+
cmp = get_Proj_pred(sel);
+ if(!is_Cmp(cmp))
+ return;
+
left = get_Cmp_left(cmp);
idx = get_irn_idx(left);
lentry = env->entries[idx];
assert(projT && projF);
/* create a new high compare */
- block = get_nodes_block(cmp);
+ block = get_nodes_block(node);
dbg = get_irn_dbg_info(cmp);
irg = current_ir_graph;
+ pnc = get_Proj_proj(sel);
+
+ if (is_Const(right) && is_Const_null(right)) {
+ if (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) {
+ /* x ==/!= 0 ==> or(low,high) ==/!= 0 */
+ ir_mode *mode = env->params->low_unsigned;
+ ir_node *low = new_r_Conv(irg, block, lentry->low_word, mode);
+ ir_node *high = new_r_Conv(irg, block, lentry->high_word, mode);
+ ir_node *or = new_rd_Or(dbg, irg, block, low, high, mode);
+ ir_node *cmp = new_rd_Cmp(dbg, irg, block, or, new_Const_long(mode, 0));
+
+ ir_node *proj = new_r_Proj(irg, block, cmp, mode_b, pnc);
+ set_Cond_selector(node, proj);
+ return;
+ }
+ }
cmpH = new_rd_Cmp(dbg, irg, block, lentry->high_word, rentry->high_word);
- pnc = get_Proj_proj(sel);
if (pnc == pn_Cmp_Eq) {
/* simple case:a == b <==> a_h == b_h && a_l == b_l */
pmap_entry *entry = pmap_find(env->proj_2_block, projF);
static void lower_Conv_to_Ls(ir_node *node, lower_env_t *env) {
ir_node *op = get_Conv_op(node);
ir_mode *imode = get_irn_mode(op);
- ir_mode *dst_mode = env->params->low_signed;
+ ir_mode *dst_mode_l = env->params->low_unsigned;
+ ir_mode *dst_mode_h = env->params->low_signed;
int idx = get_irn_idx(node);
ir_graph *irg = current_ir_graph;
ir_node *block = get_nodes_block(node);
pdeq_putr(env->waitq, node);
return;
} /* if */
- env->entries[idx]->low_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->low_word, dst_mode);
- env->entries[idx]->high_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->high_word, dst_mode);
+ env->entries[idx]->low_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->low_word, dst_mode_l);
+ env->entries[idx]->high_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->high_word, dst_mode_h);
} else {
/* simple case: create a high word */
- if (imode != dst_mode)
- op = new_rd_Conv(dbg, irg, block, op, dst_mode);
+ if (imode != dst_mode_l)
+ op = new_rd_Conv(dbg, irg, block, op, dst_mode_l);
env->entries[idx]->low_word = op;
- env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
- new_Const_long(mode_Iu, get_mode_size_bits(dst_mode) - 1), dst_mode);
+
+ if (mode_is_signed(imode)) {
+ ir_node *op_conv = new_rd_Conv(dbg, irg, block, op, dst_mode_h);
+ env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op_conv,
+ new_Const_long(mode_Iu, get_mode_size_bits(dst_mode_h) - 1), dst_mode_h);
+ } else {
+ env->entries[idx]->high_word = new_Const(dst_mode_h, get_mode_null(dst_mode_h));
+ } /* if */
} /* if */
} else {
ir_node *irn, *call;
set_irn_pinned(call, get_irn_pinned(node));
irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
- env->entries[idx]->low_word = new_r_Proj(irg, block, irn, dst_mode, 0);
- env->entries[idx]->high_word = new_r_Proj(irg, block, irn, dst_mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irg, block, irn, dst_mode_l, 0);
+ env->entries[idx]->high_word = new_r_Proj(irg, block, irn, dst_mode_h, 1);
} /* if */
} /* lower_Conv_to_Ls */
op = new_rd_Conv(dbg, irg, block, op, dst_mode);
env->entries[idx]->low_word = op;
- env->entries[idx]->high_word = new_Const(dst_mode, get_mode_null(dst_mode));
+
+ if (mode_is_signed(imode)) {
+ env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
+ new_Const_long(mode_Iu, get_mode_size_bits(dst_mode) - 1), dst_mode);
+ } else {
+ env->entries[idx]->high_word = new_Const(dst_mode, get_mode_null(dst_mode));
+ } /* if */
} /* if */
} else {
ir_node *irn, *call;
assert(idx < env->n_entries);
+ if (! env->entries[idx]->low_word) {
+ /* not ready yet, wait */
+ pdeq_putr(env->waitq, node);
+ return;
+ } /* if */
+
if (mode_is_int(omode) || mode_is_reference(omode)) {
op = env->entries[idx]->low_word;
assert(idx < env->n_entries);
+ if (! env->entries[idx]->low_word) {
+ /* not ready yet, wait */
+ pdeq_putr(env->waitq, node);
+ return;
+ } /* if */
+
if (mode_is_int(omode) || mode_is_reference(omode)) {
op = env->entries[idx]->low_word;
ir_mode *mode = get_type_mode(tp);
if (mode == env->params->high_signed) {
- set_method_param_type(res, n_param++, tp_s);
+ set_method_param_type(res, n_param++, tp_u);
set_method_param_type(res, n_param++, tp_s);
} else if (mode == env->params->high_unsigned) {
set_method_param_type(res, n_param++, tp_u);
ir_mode *mode = get_type_mode(tp);
if (mode == env->params->high_signed) {
- set_method_res_type(res, n_res++, tp_s);
+ set_method_res_type(res, n_res++, tp_u);
set_method_res_type(res, n_res++, tp_s);
} else if (mode == env->params->high_unsigned) {
set_method_res_type(res, n_res++, tp_u);
ir_node **in;
int i, j, n, idx;
int need_conv = 0;
+ (void) mode;
/* check if this return must be lowered */
for (i = 0, n = get_Return_n_ress(node); i < n; ++i) {
long *new_projs;
int i, j, n_params, rem;
ir_node *proj, *args;
+ (void) mode;
if (is_lowered_type(tp)) {
mtp = get_associated_type(tp);
idx = get_irn_idx(proj);
if (env->entries[idx]) {
+ ir_mode *low_mode = env->params->low_unsigned;
+
mode = get_irn_mode(proj);
if (mode == env->params->high_signed) {
dbg = get_irn_dbg_info(proj);
env->entries[idx]->low_word =
- new_rd_Proj(dbg, irg, get_nodes_block(proj), args, mode, new_projs[proj_nr]);
+ new_rd_Proj(dbg, irg, get_nodes_block(proj), args, low_mode, new_projs[proj_nr]);
env->entries[idx]->high_word =
new_rd_Proj(dbg, irg, get_nodes_block(proj), args, mode, new_projs[proj_nr] + 1);
} /* if */
int n_params, n_res, need_lower = 0;
int i, j;
long *res_numbers = NULL;
+ (void) mode;
if (is_lowered_type(tp)) {
call_tp = get_associated_type(tp);
idx = get_irn_idx(proj);
if (env->entries[idx]) {
ir_mode *mode = get_irn_mode(proj);
+ ir_mode *low_mode = env->params->low_unsigned;
dbg_info *dbg;
if (mode == env->params->high_signed) {
dbg = get_irn_dbg_info(proj);
env->entries[idx]->low_word =
- new_rd_Proj(dbg, irg, get_nodes_block(proj), results, mode, res_numbers[proj_nr]);
+ new_rd_Proj(dbg, irg, get_nodes_block(proj), results, low_mode, res_numbers[proj_nr]);
env->entries[idx]->high_word =
new_rd_Proj(dbg, irg, get_nodes_block(proj), results, mode, res_numbers[proj_nr] + 1);
} /* if */
* Translate an Unknown into two.
*/
static void lower_Unknown(ir_node *node, ir_mode *mode, lower_env_t *env) {
- int idx = get_irn_idx(node);
+ int idx = get_irn_idx(node);
ir_graph *irg = current_ir_graph;
+ ir_mode *low_mode = env->params->low_unsigned;
- env->entries[idx]->low_word =
+ env->entries[idx]->low_word = new_r_Unknown(irg, low_mode);
env->entries[idx]->high_word = new_r_Unknown(irg, mode);
} /* lower_Unknown */
* First step: just create two templates
*/
static void lower_Phi(ir_node *phi, ir_mode *mode, lower_env_t *env) {
+ ir_mode *mode_l = env->params->low_unsigned;
ir_graph *irg = current_ir_graph;
- ir_node *block, *unk;
+ ir_node *block, *unk_l, *unk_h, *phi_l, *phi_h;
ir_node **inl, **inh;
dbg_info *dbg;
int idx, i, arity = get_Phi_n_preds(phi);
/* first create a new in array */
NEW_ARR_A(ir_node *, inl, arity);
NEW_ARR_A(ir_node *, inh, arity);
- unk = new_r_Unknown(irg, mode);
+ unk_l = new_r_Unknown(irg, mode_l);
+ unk_h = new_r_Unknown(irg, mode);
for (i = 0; i < arity; ++i) {
ir_node *pred = get_Phi_pred(phi, i);
inl[i] = env->entries[idx]->low_word;
inh[i] = env->entries[idx]->high_word;
} else {
- inl[i] = unk;
- inh[i] = unk;
+ inl[i] = unk_l;
+ inh[i] = unk_h;
enq = 1;
} /* if */
} /* for */
idx = get_irn_idx(phi);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Phi(dbg, irg, block, arity, inl, mode);
- env->entries[idx]->high_word = new_rd_Phi(dbg, irg, block, arity, inh, mode);
+ env->entries[idx]->low_word = phi_l = new_rd_Phi(dbg, irg, block, arity, inl, mode_l);
+ env->entries[idx]->high_word = phi_h = new_rd_Phi(dbg, irg, block, arity, inh, mode);
+
+ /* Don't forget to link the new Phi nodes into the block! */
+ set_irn_link(phi_l, get_irn_link(block));
+ set_irn_link(phi_h, phi_l);
+ set_irn_link(block, phi_h);
if (enq) {
/* not yet finished */
} /* lower_Phi */
/**
- * Translate a Psi.
+ * Translate a Mux.
*/
-static void lower_Psi(ir_node *psi, ir_mode *mode, lower_env_t *env) {
+static void lower_Mux(ir_node *mux, ir_mode *mode, lower_env_t *env) {
ir_graph *irg = current_ir_graph;
ir_node *block, *val;
- ir_node **valsl, **valsh, **conds;
+ ir_node *true_l, *true_h, *false_l, *false_h, *sel;
dbg_info *dbg;
- int idx, i, n_conds = get_Psi_n_conds(psi);
+ int idx;
- /* first create a new in array */
- NEW_ARR_A(ir_node *, valsl, n_conds + 1);
- NEW_ARR_A(ir_node *, valsh, n_conds + 1);
+ val = get_Mux_true(mux);
+ idx = get_irn_idx(val);
+ if (env->entries[idx]->low_word) {
+ /* Values already build */
+ true_l = env->entries[idx]->low_word;
+ true_h = env->entries[idx]->high_word;
+ } else {
+ /* still not ready */
+ pdeq_putr(env->waitq, mux);
+ return;
+ } /* if */
- for (i = 0; i < n_conds; ++i) {
- val = get_Psi_val(psi, i);
- idx = get_irn_idx(val);
- if (env->entries[idx]->low_word) {
- /* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
- } else {
- /* still not ready */
- pdeq_putr(env->waitq, psi);
- return;
- } /* if */
- } /* for */
- val = get_Psi_default(psi);
+ val = get_Mux_false(mux);
idx = get_irn_idx(val);
if (env->entries[idx]->low_word) {
/* Values already build */
- valsl[i] = env->entries[idx]->low_word;
- valsh[i] = env->entries[idx]->high_word;
+ false_l = env->entries[idx]->low_word;
+ false_h = env->entries[idx]->high_word;
} else {
/* still not ready */
- pdeq_putr(env->waitq, psi);
+ pdeq_putr(env->waitq, mux);
return;
} /* if */
- NEW_ARR_A(ir_node *, conds, n_conds);
- for (i = 0; i < n_conds; ++i) {
- conds[i] = get_Psi_cond(psi, i);
- } /* for */
+ sel = get_Mux_sel(mux);
- dbg = get_irn_dbg_info(psi);
- block = get_nodes_block(psi);
+ dbg = get_irn_dbg_info(mux);
+ block = get_nodes_block(mux);
- idx = get_irn_idx(psi);
+ idx = get_irn_idx(mux);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsl, mode);
- env->entries[idx]->high_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsh, mode);
-} /* lower_Psi */
+ env->entries[idx]->low_word = new_rd_Mux(dbg, irg, block, sel, false_l, true_l, mode);
+ env->entries[idx]->high_word = new_rd_Mux(dbg, irg, block, sel, false_h, true_h, mode);
+} /* lower_Mux */
+
+static void lower_ASM(ir_node *asmn, ir_mode *mode, lower_env_t *env)
+{
+ ir_mode *his = env->params->high_signed;
+ ir_mode *hiu = env->params->high_unsigned;
+ int i;
+ ir_node *n;
+
+ (void)mode;
+
+ for (i = get_irn_arity(asmn) - 1; i >= 0; --i) {
+ ir_mode *op_mode = get_irn_mode(get_irn_n(asmn, i));
+ if (op_mode == his || op_mode == hiu) {
+ panic("lowering ASM unimplemented");
+ }
+ }
+
+ for (n = asmn;;) {
+ ir_mode *proj_mode;
+
+ n = get_irn_link(n);
+ if (n == NULL)
+ break;
+
+ proj_mode = get_irn_mode(n);
+ if (proj_mode == his || proj_mode == hiu) {
+ panic("lowering ASM unimplemented");
+ }
+ }
+}
/**
* check for opcodes that must always be lowered.
*/
static int always_lower(ir_opcode code) {
switch (code) {
+ case iro_ASM:
case iro_Proj:
case iro_Start:
case iro_Call:
int idx = get_irn_idx(node);
ir_mode *mode = get_irn_mode(node);
- if (mode == mode_b || get_irn_op(node) == op_Psi) {
+ if (mode == mode_b || is_Mux(node) || is_Conv(node)) {
int i;
for (i = get_irn_arity(node) - 1; i >= 0; --i) {
static int cmp_op_mode(const void *elt, const void *key, size_t size) {
const op_mode_entry_t *e1 = elt;
const op_mode_entry_t *e2 = key;
+ (void) size;
return (e1->op - e2->op) | (e1->imode - e2->imode) | (e1->omode - e2->omode);
} /* cmp_op_mode */
static int cmp_conv_tp(const void *elt, const void *key, size_t size) {
const conv_tp_entry_t *e1 = elt;
const conv_tp_entry_t *e2 = key;
+ (void) size;
return (e1->imode - e2->imode) | (e1->omode - e2->omode);
} /* static int cmp_conv_tp */
+/**
+ * Enter a lowering function into an ir_op.
+ */
+static void enter_lower_func(ir_op *op, lower_func func) {
+ op->ops.generic = (op_func)func;
+}
+
/*
* Do the lowering.
*/
if (! prim_types)
prim_types = pmap_create();
if (! intrinsic_fkt)
- intrinsic_fkt = new_set(cmp_op_mode, iro_MaxOpcode);
+ intrinsic_fkt = new_set(cmp_op_mode, iro_Last + 1);
if (! conv_types)
conv_types = new_set(cmp_conv_tp, 16);
if (! lowered_type)
} /* if */
if (! binop_tp_s) {
binop_tp_s = new_type_method(IDENT("binop_s_intrinsic"), 4, 2);
- set_method_param_type(binop_tp_s, 0, tp_s);
+ set_method_param_type(binop_tp_s, 0, tp_u);
set_method_param_type(binop_tp_s, 1, tp_s);
- set_method_param_type(binop_tp_s, 2, tp_s);
+ set_method_param_type(binop_tp_s, 2, tp_u);
set_method_param_type(binop_tp_s, 3, tp_s);
- set_method_res_type(binop_tp_s, 0, tp_s);
+ set_method_res_type(binop_tp_s, 0, tp_u);
set_method_res_type(binop_tp_s, 1, tp_s);
} /* if */
if (! shiftop_tp_u) {
} /* if */
if (! shiftop_tp_s) {
shiftop_tp_s = new_type_method(IDENT("shiftop_s_intrinsic"), 3, 2);
- set_method_param_type(shiftop_tp_s, 0, tp_s);
+ set_method_param_type(shiftop_tp_s, 0, tp_u);
set_method_param_type(shiftop_tp_s, 1, tp_s);
/* beware: shift count is always mode_Iu */
set_method_param_type(shiftop_tp_s, 2, tp_u);
- set_method_res_type(shiftop_tp_s, 0, tp_s);
+ set_method_res_type(shiftop_tp_s, 0, tp_u);
set_method_res_type(shiftop_tp_s, 1, tp_s);
} /* if */
if (! unop_tp_u) {
} /* if */
if (! unop_tp_s) {
unop_tp_s = new_type_method(IDENT("unop_s_intrinsic"), 2, 2);
- set_method_param_type(unop_tp_s, 0, tp_s);
+ set_method_param_type(unop_tp_s, 0, tp_u);
set_method_param_type(unop_tp_s, 1, tp_s);
- set_method_res_type(unop_tp_s, 0, tp_s);
+ set_method_res_type(unop_tp_s, 0, tp_u);
set_method_res_type(unop_tp_s, 1, tp_s);
} /* if */
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
-#define LOWER2(op, fkt) op_##op->ops.generic = (op_func)fkt
+#define LOWER2(op, fkt) enter_lower_func(op_##op, fkt)
#define LOWER(op) LOWER2(op, lower_##op)
#define LOWER_BIN(op) LOWER2(op, lower_Binop)
#define LOWER_UN(op) LOWER2(op, lower_Unop)
/* the table of all operations that must be lowered follows */
+ LOWER(ASM);
LOWER(Load);
LOWER(Store);
LOWER(Const);
LOWER(Call);
LOWER(Unknown);
LOWER(Phi);
- LOWER(Psi);
+ LOWER(Mux);
LOWER(Start);
LOWER_BIN(Add);
LOWER(Shl);
LOWER(Shr);
LOWER(Shrs);
- LOWER(Rot);
- LOWER(Minus);
+ LOWER(Rotl);
LOWER(DivMod);
LOWER(Div);
LOWER(Mod);
LOWER_UN(Abs);
+ LOWER_UN(Minus);
LOWER(Conv);
obstack_init(&lenv.obst);
n_idx = get_irg_last_idx(irg);
+ n_idx = n_idx + (n_idx >> 2); /* add 25% */
lenv.n_entries = n_idx;
- lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0]));
+ lenv.entries = NEW_ARR_F(node_entry_t *, n_idx);
memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0]));
/* first step: link all nodes and allocate data */
lenv.flags = 0;
lenv.proj_2_block = pmap_create();
- irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv);
+ irg_walk_graph(irg, firm_clear_link, prepare_links_and_handle_rotl, &lenv);
if (lenv.flags & MUST_BE_LOWERED) {
DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg));
} /* if */
} /* if */
pmap_destroy(lenv.proj_2_block);
- free(lenv.entries);
+ DEL_ARR_F(lenv.entries);
obstack_free(&lenv.obst, NULL);
} /* for */
del_pdeq(lenv.waitq);
char buf[64];
ident *id;
ir_entity *ent;
+ (void) context;
if (imode == omode) {
snprintf(buf, sizeof(buf), "__l%s%s", get_op_name(op), get_mode_name(imode));
projects / libfirm / blobdiff