* @file
* @brief Check irnodes for correctness.
* @author Christian Schaefer, Goetz Lindenmaier, Till Riedel, Michael Beck
- * @version $Id$
*/
#include "config.h"
#include "irflag_t.h"
#include "irpass_t.h"
#include "irnodeset.h"
+#include "ircons.h"
/** if this flag is set, verify entity types in Load & Store nodes */
static int verify_entities = 0;
const char *firm_verify_failure_msg;
-/* enable verification of Load/Store entities */
void verify_enable_entity_tests(int enable)
{
verify_entities = enable;
static int verify_node_Proj_Cond(const ir_node *p)
{
ir_mode *mode = get_irn_mode(p);
- ir_node *pred = get_Proj_pred(p);
- long proj = get_Proj_proj(p);
+ long proj = get_Proj_proj(p);
ASSERT_AND_RET_DBG(
- (
- (proj >= 0 && mode == mode_X && get_irn_mode(get_Cond_selector(pred)) == mode_b) || /* compare */
- (mode == mode_X && mode_is_int(get_irn_mode(get_Cond_selector(pred)))) /* switch */
- ),
+ mode == mode_X && (proj == pn_Cond_false || proj == pn_Cond_true),
"wrong Proj from Cond", 0,
show_proj_failure(p);
);
return 1;
}
+static int verify_node_Proj_Switch(const ir_node *p)
+{
+ ir_mode *mode = get_irn_mode(p);
+ long pn = get_Proj_proj(p);
+ ir_node *pred = get_Proj_pred(p);
+ ASSERT_AND_RET_DBG(
+ mode == mode_X && (pn >= 0 && pn < (long)get_Switch_n_outs(pred)),
+ "wrong Proj from Switch", 0,
+ show_proj_failure(p);
+ );
+ return 1;
+}
+
/**
* verify a Proj(Raise) node
*/
(proj >= 0 && mode_is_datab(mode)),
"wrong Proj from Proj from Call", 0);
mt = get_Call_type(pred);
- ASSERT_AND_RET(mt == get_unknown_type() || is_Method_type(mt),
+ ASSERT_AND_RET(is_unknown_type(mt) || is_Method_type(mt),
"wrong call type on call", 0);
ASSERT_AND_RET(
(proj < (int)get_method_n_ress(mt)),
ir_mode *mymode = get_irn_mode(n);
ir_mode *op1mode = get_irn_mode(get_Cond_selector(n));
- ASSERT_AND_RET(
- /* Cond: BB x b --> X x X */
- (op1mode == mode_b ||
- /* Cond: BB x int --> X^n */
- mode_is_int(op1mode) ), "Cond node", 0
- );
+ ASSERT_AND_RET(op1mode == mode_b, "Cond operand not mode_b", 0);
ASSERT_AND_RET(mymode == mode_T, "Cond mode is not a tuple", 0);
+ return 1;
+}
+
+static int verify_switch_table(const ir_node *n)
+{
+ const ir_switch_table *table = get_Switch_table(n);
+ unsigned n_outs = get_Switch_n_outs(n);
+ ir_node *selector = get_Switch_selector(n);
+ ir_mode *mode = get_irn_mode(selector);
+ size_t n_entries;
+ size_t e;
+
+ ASSERT_AND_RET(table != NULL, "switch table is NULL", 0);
+
+ n_entries = ir_switch_table_get_n_entries(table);
+ for (e = 0; e < n_entries; ++e) {
+ const ir_switch_table_entry *entry
+ = ir_switch_table_get_entry_const(table, e);
+ if (entry->pn == 0)
+ continue;
+ ASSERT_AND_RET(entry->min != NULL && entry->max != NULL,
+ "switch table entry without min+max value", 0);
+ ASSERT_AND_RET(get_tarval_mode(entry->min) == mode &&
+ get_tarval_mode(entry->max) == mode,
+ "switch table entry with wrong modes", 0);
+ ASSERT_AND_RET(tarval_cmp(entry->min, entry->max) != ir_relation_greater,
+ "switch table entry without min+max value", 0);
+ ASSERT_AND_RET(entry->pn >= 0 && entry->pn < (long)n_outs,
+ "switch table entry with invalid proj number", 0);
+ }
+ return 1;
+}
+
+static int verify_node_Switch(const ir_node *n)
+{
+ ir_mode *mymode = get_irn_mode(n);
+ ir_mode *op1mode = get_irn_mode(get_Switch_selector(n));
+ if (!verify_switch_table(n))
+ return 0;
+ ASSERT_AND_RET(mode_is_int(op1mode), "Switch operand not integer", 0);
+ ASSERT_AND_RET(mymode == mode_T, "Switch mode is not a tuple", 0);
return 1;
}
*/
static int verify_node_Conv(const ir_node *n)
{
- ir_graph *irg = get_irn_irg(n);
- ir_mode *mymode = get_irn_mode(n);
- ir_mode *op1mode = get_irn_mode(get_Conv_op(n));
+ ir_mode *mymode = get_irn_mode(n);
+ ir_mode *op1mode = get_irn_mode(get_Conv_op(n));
- ASSERT_AND_RET_DBG(
- is_irg_state(irg, IR_GRAPH_STATE_BCONV_ALLOWED) ||
- (mode_is_datab(op1mode) && mode_is_data(mymode)),
+ ASSERT_AND_RET_DBG(mode_is_data(op1mode) && mode_is_data(mymode),
"Conv node", 0,
- show_unop_failure(n, "/* Conv: BB x datab --> data */");
+ show_unop_failure(n, "/* Conv: BB x data --> data */");
);
return 1;
}
return 1;
}
-/* Tests the modes of n and its predecessors. */
int irn_verify_irg(const ir_node *n, ir_graph *irg)
{
ir_op *op;
op = get_irn_op(n);
- if (_get_op_pinned(op) >= op_pin_state_exc_pinned) {
+ if (get_op_pinned(op) >= op_pin_state_exc_pinned) {
op_pin_state state = get_irn_pinned(n);
ASSERT_AND_RET_DBG(
state == op_pin_state_floats ||
ir_printf("node %+F", n);
);
} else if (!is_Block(n) && is_irn_pinned_in_irg(n)
- && !is_irg_state(irg, IR_GRAPH_STATE_BAD_BLOCK)) {
+ && irg_has_properties(irg, IR_GRAPH_PROPERTY_NO_BADS)) {
ASSERT_AND_RET_DBG(is_Block(get_nodes_block(n)) || is_Anchor(n),
"block input is not a block", 0,
ir_printf("node %+F", n);
if (is_Cond(branch)) {
long pn = get_Proj_proj(branch_proj);
- if (get_irn_mode(get_Cond_selector(branch)) == mode_b) {
- if (pn == pn_Cond_true)
- ir_nodeset_insert(&env->true_projs, branch);
- if (pn == pn_Cond_false)
- ir_nodeset_insert(&env->false_projs, branch);
- } else {
- long default_pn = get_Cond_default_proj(branch);
- if (pn == default_pn)
- ir_nodeset_insert(&env->true_projs, branch);
- }
+ if (pn == pn_Cond_true)
+ ir_nodeset_insert(&env->true_projs, branch);
+ if (pn == pn_Cond_false)
+ ir_nodeset_insert(&env->false_projs, branch);
+ } else if (is_Switch(branch)) {
+ long pn = get_Proj_proj(branch_proj);
+ if (pn == pn_Switch_default)
+ ir_nodeset_insert(&env->true_projs, branch);
}
}
static int verify_cond_projs(const ir_node *cond, check_cfg_env_t *env)
{
- if (get_irn_mode(get_Cond_selector(cond)) == mode_b) {
- ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->true_projs, cond),
- "Cond node lacks true proj", 0,
- ir_printf("Cond %+F\n", cond);
- );
- ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->false_projs, cond),
- "Cond node lacks false proj", 0,
- ir_printf("Cond %+F\n", cond);
- );
- } else {
- ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->true_projs, cond),
- "Cond node lacks default Proj", 0,
- ir_printf("Cond %+F\n", cond);
- );
- }
+ ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->true_projs, cond),
+ "Cond node lacks true proj", 0,
+ ir_printf("Cond %+F\n", cond);
+ );
+ ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->false_projs, cond),
+ "Cond node lacks false proj", 0,
+ ir_printf("Cond %+F\n", cond);
+ );
+ return 1;
+}
+
+static int verify_switch_projs(const ir_node *sw, check_cfg_env_t *env)
+{
+ ASSERT_AND_RET_DBG(ir_nodeset_contains(&env->true_projs, sw),
+ "Switch node lacks default Proj", 0,
+ ir_printf("Switch %+F\n", sw);
+ );
return 1;
}
env->res &= verify_block_branch(node, env);
} else if (is_Cond(node)) {
env->res &= verify_cond_projs(node, env);
+ } else if (is_Switch(node)) {
+ env->res &= verify_switch_projs(node, env);
}
}
return env.res;
}
-/*
- * Calls irn_verify for each node in irg.
- * Graph must be in state "op_pin_state_pinned".
- * If dominance info is available, check the SSA property.
- */
int irg_verify(ir_graph *irg, unsigned flags)
{
int res = 1;
irg_walk_anchors(
irg,
- pinned && get_irg_dom_state(irg) == dom_consistent
+ pinned && irg_has_properties(irg, IR_GRAPH_PROPERTY_CONSISTENT_DOMINANCE)
? verify_wrap_ssa : verify_wrap,
NULL,
&res
return 0;
}
-/* Creates an ir_graph pass for irg_verify(). */
ir_graph_pass_t *irg_verify_pass(const char *name, unsigned flags)
{
pass_t *pass = XMALLOCZ(pass_t);
return &pass->pass;
}
-/* create a verify pass */
int irn_verify_irg_dump(const ir_node *n, ir_graph *irg,
const char **bad_string)
{
firm_verify_failure_msg = NULL;
do_node_verification(FIRM_VERIFICATION_ERROR_ONLY);
res = irn_verify_irg(n, irg);
- if (res && get_irg_dom_state(irg) == dom_consistent &&
+ if (res && irg_has_properties(irg, IR_GRAPH_PROPERTY_CONSISTENT_DOMINANCE) &&
get_irg_pinned(irg) == op_pin_state_pinned)
res = check_dominance_for_node(n);
do_node_verification(old);
}
}
-/*
- * verify occurrence of bad nodes
- */
int irg_verify_bads(ir_graph *irg, int flags)
{
verify_bad_env_t env;
return env.res;
}
-/*
- * set the default verify operation
- */
void firm_set_default_verifier(unsigned code, ir_op_ops *ops)
{
#define CASE(a) \
break
switch (code) {
- CASE(Proj);
+ CASE(Add);
+ CASE(Alloc);
+ CASE(And);
CASE(Block);
- CASE(Start);
- CASE(Jmp);
- CASE(IJmp);
+ CASE(Bound);
+ CASE(Call);
+ CASE(Cast);
+ CASE(Cmp);
CASE(Cond);
- CASE(Return);
- CASE(Raise);
+ CASE(Confirm);
CASE(Const);
- CASE(SymConst);
- CASE(Sel);
+ CASE(Conv);
+ CASE(CopyB);
+ CASE(Div);
+ CASE(Eor);
+ CASE(Free);
+ CASE(IJmp);
CASE(InstOf);
- CASE(Call);
- CASE(Add);
- CASE(Sub);
+ CASE(Jmp);
+ CASE(Load);
CASE(Minus);
+ CASE(Mod);
CASE(Mul);
CASE(Mulh);
- CASE(Div);
- CASE(Mod);
- CASE(And);
- CASE(Or);
- CASE(Eor);
+ CASE(Mux);
CASE(Not);
- CASE(Cmp);
+ CASE(Or);
+ CASE(Phi);
+ CASE(Proj);
+ CASE(Raise);
+ CASE(Return);
+ CASE(Rotl);
+ CASE(Sel);
CASE(Shl);
CASE(Shr);
CASE(Shrs);
- CASE(Rotl);
- CASE(Conv);
- CASE(Cast);
- CASE(Phi);
- CASE(Load);
+ CASE(Start);
CASE(Store);
- CASE(Alloc);
- CASE(Free);
+ CASE(Sub);
+ CASE(Switch);
+ CASE(SymConst);
CASE(Sync);
- CASE(Confirm);
- CASE(Mux);
- CASE(CopyB);
- CASE(Bound);
default:
break;
}
break
switch (code) {
- CASE(Start);
- CASE(Cond);
- CASE(Raise);
- CASE(InstOf);
+ CASE(Alloc);
+ CASE(Bound);
CASE(Call);
+ CASE(Cond);
+ CASE(CopyB);
CASE(Div);
- CASE(Mod);
+ CASE(InstOf);
CASE(Load);
- CASE(Store);
- CASE(Alloc);
+ CASE(Mod);
CASE(Proj);
+ CASE(Raise);
+ CASE(Start);
+ CASE(Store);
+ CASE(Switch);
CASE(Tuple);
- CASE(CopyB);
- CASE(Bound);
default:
break;
}
projects / libfirm / blobdiff