if (get_irg_phase_state(irg) == phase_backend) {
be_info_new_node(res);
}
+ // Init the VRP structures
+ res->vrp.range_type = VRP_UNDEFINED;
+ res->vrp.valid = 0;
+ if(mode_is_int(mode)) {
+ // We are assuming that 0 is always represented as 0x0000
+ res->vrp.bits_set = new_tarval_from_long(0, mode);
+ res->vrp.bits_not_set = new_tarval_from_long(0, mode);
+ res->vrp.range_bottom = get_tarval_top();
+ res->vrp.range_top = get_tarval_top();
+ } else {
+ res->vrp.bits_set = get_tarval_bad();
+ res->vrp.bits_not_set = get_tarval_bad();
+ res->vrp.range_bottom = get_tarval_bad();
+ res->vrp.range_top = get_tarval_bad();
+ }
+ res->vrp.bits_node = NULL;
+ res->vrp.range_node = NULL;
+ res->vrp.range_op = VRP_NONE;
+
return res;
}
glob = get_glob_type();
entity = new_entity(glob, id_unique("block_%u"), get_code_type());
+ set_entity_visibility(entity, ir_visibility_local);
+ set_entity_linkage(entity, IR_LINKAGE_CONSTANT);
nr = get_irp_next_label_nr();
set_entity_label(entity, nr);
set_entity_compiler_generated(entity, 1);
- set_entity_allocation(entity, allocation_static);
block->attr.block.entity = entity;
}