static ir_node *get_jump_target(const ir_node *jump)
{
- return get_irn_link(jump);
+ return (ir_node*)get_irn_link(jump);
}
/**
static bool ba_is_fallthrough(const ir_node *node)
{
ir_node *block = get_nodes_block(node);
- ir_node *next_block = get_irn_link(block);
+ ir_node *next_block = (ir_node*)get_irn_link(block);
return get_irn_link(node) == next_block;
}
if (src_reg == dest_reg)
return true;
}
+ if (be_is_IncSP(node) && be_get_IncSP_offset(node) == 0)
+ return true;
/* Ba is not emitted if it is a simple fallthrough */
if (is_sparc_Ba(node) && ba_is_fallthrough(node))
return true;
return is_sparc_Bicc(node) || is_sparc_fbfcc(node) || is_sparc_Ba(node)
|| is_sparc_SwitchJmp(node) || is_sparc_Call(node)
- || is_sparc_SDiv(node) || is_sparc_UDiv(node);
+ || is_sparc_SDiv(node) || is_sparc_UDiv(node)
+ || be_is_Return(node);
}
/** returns true if the emitter for this sparc node can produce more than one
return true;
return is_sparc_Mulh(node) || is_sparc_SDiv(node) || is_sparc_UDiv(node)
- || be_is_MemPerm(node) || be_is_Perm(node) || be_is_Return(node);
+ || be_is_MemPerm(node) || be_is_Perm(node);
}
/**
/* the Call also destroys the value of %o7, but since this is currently
* marked as ignore register in the backend, it should never be used by
* the instruction in the delay slot. */
+ } else if (be_is_Return(node)) {
+ /* we only have to check the jump destination value */
+ int arity = get_irn_arity(node);
+ int i;
+
+ check = NULL;
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ const arch_register_t *reg = arch_get_irn_register(in);
+ if (reg == &sparc_registers[REG_O7]) {
+ check = skip_Proj(in);
+ break;
+ }
+ }
} else {
check = node;
}
while (sched_has_prev(schedpoint)) {
schedpoint = sched_prev(schedpoint);
- if (tries++ >= PICK_DELAY_SLOT_MAX_DISTANCE)
- break;
-
if (has_delay_slot(schedpoint))
break;
if (is_no_instruction(schedpoint))
continue;
+ if (tries++ >= PICK_DELAY_SLOT_MAX_DISTANCE)
+ break;
+
if (emits_multiple_instructions(schedpoint))
continue;
be_emit_finish_line_gas(irn);
}
-/**
- * emits code for save instruction with min. required stack space
- */
-static void emit_sparc_Save(const ir_node *irn)
-{
- const sparc_save_attr_t *save_attr = get_sparc_save_attr_const(irn);
- be_emit_cstring("\tsave ");
- sparc_emit_source_register(irn, 0);
- be_emit_irprintf(", %d, ", -save_attr->initial_stacksize);
- sparc_emit_dest_register(irn, 0);
- be_emit_finish_line_gas(irn);
-}
-
/**
* emits code for mulh
*/
emit_sparc_Div(node, false);
}
-/**
- * Emits code for return node
- */
-static void emit_be_Return(const ir_node *irn)
-{
- be_emit_cstring("\tret");
- //be_emit_cstring("\tjmp %i7+8");
- be_emit_finish_line_gas(irn);
- be_emit_cstring("\trestore");
- be_emit_finish_line_gas(irn);
-}
-
/**
* Emits code for Call node
*/
assert(sp_change == 0);
}
+static void emit_be_Return(const ir_node *node)
+{
+ const char *destreg = "%o7";
+
+ /* hack: we don't explicitely model register changes because of the
+ * restore node. So we have to do it manually here */
+ if (delay_slot_filler != NULL &&
+ (is_sparc_Restore(delay_slot_filler)
+ || is_sparc_RestoreZero(delay_slot_filler))) {
+ destreg = "%i7";
+ }
+ be_emit_cstring("\tjmp ");
+ be_emit_string(destreg);
+ be_emit_cstring("+8");
+ be_emit_finish_line_gas(node);
+ fill_delay_slot();
+}
+
static void emit_sparc_FrameAddr(const ir_node *node)
{
const sparc_attr_t *attr = get_sparc_attr_const(node);
block = get_nodes_block(node);
/* we have a block schedule */
- next_block = get_irn_link(block);
+ next_block = (ir_node*)get_irn_link(block);
if (get_irn_link(proj_true) == next_block) {
/* exchange both proj's so the second one can be omitted */
set_emitter(op_sparc_fbfcc, emit_sparc_fbfcc);
set_emitter(op_sparc_FrameAddr, emit_sparc_FrameAddr);
set_emitter(op_sparc_Mulh, emit_sparc_Mulh);
- set_emitter(op_sparc_Save, emit_sparc_Save);
set_emitter(op_sparc_SDiv, emit_sparc_SDiv);
set_emitter(op_sparc_SwitchJmp, emit_sparc_SwitchJmp);
set_emitter(op_sparc_UDiv, emit_sparc_UDiv);