change backends to produce 1 big array with all registers

[libfirm] / ir / be / sparc / bearch_sparc.c

diff --git a/ir/be/sparc/bearch_sparc.c b/ir/be/sparc/bearch_sparc.c
index 6e6282f..a6f1cf9 100644 (file)
--- a/ir/be/sparc/bearch_sparc.c
+++ b/ir/be/sparc/bearch_sparc.c
@@ -50,7 +50,6 @@
 #include "../besched.h"
 #include "be.h"
 #include "../bemachine.h"
-#include "../beilpsched.h"
 #include "../bemodule.h"
 #include "../beirg.h"
 #include "../bespillslots.h"
@@ -196,7 +195,8 @@ static void transform_Spill(ir_node *node)
        ir_node   *block  = get_nodes_block(node);
        dbg_info  *dbgi   = get_irn_dbg_info(node);
        ir_node   *ptr    = get_irn_n(node, be_pos_Spill_frame);
-       ir_node   *mem    = new_NoMem();
+       ir_graph  *irg    = get_irn_irg(node);
+       ir_node   *mem    = new_r_NoMem(irg);
        ir_node   *val    = get_irn_n(node, be_pos_Spill_val);
        ir_mode   *mode   = get_irn_mode(val);
        ir_entity *entity = be_get_frame_entity(node);
@@ -295,8 +295,10 @@ const arch_isa_if_t sparc_isa_if;
 static sparc_isa_t sparc_isa_template = {
        {
                &sparc_isa_if,                      /* isa interface implementation */
-               &sparc_gp_regs[REG_SP],             /* stack pointer register */
-               &sparc_gp_regs[REG_FRAME_POINTER],  /* base pointer register */
+               N_SPARC_REGISTERS,
+               sparc_registers,
+               &sparc_registers[REG_SP],           /* stack pointer register */
+               &sparc_registers[REG_FRAME_POINTER],/* base pointer register */
                &sparc_reg_classes[CLASS_sparc_gp], /* link pointer register class */
                -1,                                 /* stack direction */
                3,                                  /* power of two stack alignment
@@ -372,10 +374,10 @@ static void rewrite_unsigned_float_Conv(ir_node *node)
 
 static int sparc_rewrite_Conv(ir_node *node, void *ctx)
 {
-       (void) ctx;
        ir_mode *to_mode   = get_irn_mode(node);
        ir_node *op        = get_Conv_op(node);
        ir_mode *from_mode = get_irn_mode(op);
+       (void) ctx;
 
        if (mode_is_float(to_mode) && mode_is_int(from_mode)
                        && get_mode_size_bits(from_mode) == 32
@@ -507,12 +509,12 @@ static void sparc_done(void *self)
 
 static unsigned sparc_get_n_reg_class(void)
 {
-       return N_CLASSES;
+       return N_SPARC_CLASSES;
 }
 
 static const arch_register_class_t *sparc_get_reg_class(unsigned i)
 {
-       assert(i < N_CLASSES);
+       assert(i < N_SPARC_CLASSES);
        return &sparc_reg_classes[i];
 }
 
@@ -532,39 +534,6 @@ static const arch_register_class_t *sparc_get_reg_class_for_mode(const ir_mode *
                return &sparc_reg_classes[CLASS_sparc_gp];
 }
 
-static int sparc_to_appear_in_schedule(void *block_env, const ir_node *irn)
-{
-       (void) block_env;
-
-       if (!is_sparc_irn(irn))
-               return -1;
-
-       return 1;
-}
-
-list_sched_selector_t sparc_sched_selector;
-
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
- */
-static const list_sched_selector_t *sparc_get_list_sched_selector(
-               const void *self, list_sched_selector_t *selector)
-{
-       (void) self;
-       (void) selector;
-
-       sparc_sched_selector = trivial_selector;
-       sparc_sched_selector.to_appear_in_schedule = sparc_to_appear_in_schedule;
-       return &sparc_sched_selector;
-}
-
-static const ilp_sched_selector_t *sparc_get_ilp_sched_selector(
-               const void *self)
-{
-       (void) self;
-       return NULL;
-}
-
 /**
  * Returns the necessary byte alignment for storing a register of given class.
  */
@@ -587,6 +556,15 @@ static void sparc_lower_for_target(void)
        }
 }
 
+static int sparc_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+                                ir_node *mux_true)
+{
+       (void) sel;
+       (void) mux_false;
+       (void) mux_true;
+       return false;
+}
+
 /**
  * Returns the libFirm configuration parameter for this backend.
  */
@@ -607,7 +585,7 @@ static const backend_params *sparc_get_backend_params(void)
                1,     /* big endian */
                sparc_lower_for_target, /* lowering callback */
                &arch_dep,              /* will be set later */
-               NULL,  /* parameter for if conversion */
+               sparc_is_mux_allowed,   /* parameter for if conversion */
                NULL,  /* float arithmetic mode */
                0,     /* no trampoline support: size 0 */
                0,     /* no trampoline support: align 0 */
@@ -617,21 +595,6 @@ static const backend_params *sparc_get_backend_params(void)
        return &p;
 }
 
-static const be_execution_unit_t ***sparc_get_allowed_execution_units(
-               const ir_node *irn)
-{
-       (void) irn;
-       /* TODO */
-       panic("sparc_get_allowed_execution_units not implemented yet");
-}
-
-static const be_machine_t *sparc_get_machine(const void *self)
-{
-       (void) self;
-       /* TODO */
-       panic("sparc_get_machine not implemented yet");
-}
-
 static ir_graph **sparc_get_backend_irg_list(const void *self,
                                              ir_graph ***irgs)
 {
@@ -660,12 +623,8 @@ const arch_isa_if_t sparc_isa_if = {
        sparc_get_reg_class,
        sparc_get_reg_class_for_mode,
        NULL,
-       sparc_get_list_sched_selector,
-       sparc_get_ilp_sched_selector,
        sparc_get_reg_class_alignment,
        sparc_get_backend_params,
-       sparc_get_allowed_execution_units,
-       sparc_get_machine,
        sparc_get_backend_irg_list,
        NULL,                    /* mark remat */
        sparc_parse_asm_constraint,