#include "array_t.h"
#include "error.h"
#include "util.h"
-
+#include "be_t.h"
#include "bearch.h"
#include "benode.h"
#include "belower.h"
#include "besched.h"
-#include "be.h"
-#include "bemachine.h"
#include "bemodule.h"
-#include "beirg.h"
#include "begnuas.h"
#include "belistsched.h"
#include "beflags.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-static arch_irn_class_t sparc_classify(const ir_node *node)
-{
- (void) node;
- return arch_irn_class_none;
-}
-
static ir_entity *sparc_get_frame_entity(const ir_node *node)
{
if (is_sparc_FrameAddr(node)) {
/* fill register allocator interface */
const arch_irn_ops_t sparc_irn_ops = {
- sparc_classify,
sparc_get_frame_entity,
sparc_set_frame_offset,
sparc_get_sp_bias,
- NULL, /* get_inverse */
NULL, /* get_op_estimated_cost */
NULL, /* possible_memory_operand */
NULL, /* perform_memory_operand */
static bool sparc_modifies_flags(const ir_node *node)
{
- return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_flags;
+ be_foreach_out(node, o) {
+ const arch_register_req_t *req = arch_get_irn_register_req_out(node, o);
+ if (req->cls == &sparc_reg_classes[CLASS_sparc_flags_class])
+ return true;
+ }
+ return false;
}
static bool sparc_modifies_fp_flags(const ir_node *node)
{
- return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_fp_flags;
+ be_foreach_out(node, o) {
+ const arch_register_req_t *req = arch_get_irn_register_req_out(node, o);
+ if (req->cls == &sparc_reg_classes[CLASS_sparc_fpflags_class])
+ return true;
+ }
+ return false;
}
static void sparc_before_ra(ir_graph *irg)
NULL, sparc_modifies_fp_flags);
}
-static void sparc_init_graph(ir_graph *irg)
-{
- (void) irg;
-}
-
extern const arch_isa_if_t sparc_isa_if;
static sparc_isa_t sparc_isa_template = {
{
- &sparc_isa_if, /* isa interface implementation */
+ &sparc_isa_if, /* isa interface implementation */
N_SPARC_REGISTERS,
sparc_registers,
N_SPARC_CLASSES,
sparc_reg_classes,
- &sparc_registers[REG_SP], /* stack pointer register */
- &sparc_registers[REG_FRAME_POINTER],/* base pointer register */
- &sparc_reg_classes[CLASS_sparc_gp], /* link pointer register class */
- 3, /* power of two stack alignment
- for calls */
- NULL, /* main environment */
- 7, /* costs for a spill instruction */
- 5, /* costs for a reload instruction */
- true, /* custom abi handling */
+ &sparc_registers[REG_SP], /* stack pointer register */
+ &sparc_registers[REG_FRAME_POINTER], /* base pointer register */
+ 3, /* power of two stack alignment
+ for calls */
+ NULL, /* main environment */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
+ true, /* custom abi handling */
},
- NULL, /* constants */
- SPARC_FPU_ARCH_FPU, /* FPU architecture */
+ NULL, /* constants */
+ SPARC_FPU_ARCH_FPU, /* FPU architecture */
};
/**
}
}
+/**
+ * rewrite float->unsigned conversions.
+ * Sparc has no instruction for this so instead we do the following:
+ *
+ * if (x >= 2147483648.) {
+ * converted ^= (int)(x-2147483648.) ^ 0x80000000;
+ * } else {
+ * converted = (int)x;
+ * }
+ * return (unsigned)converted;
+ */
+static void rewrite_float_unsigned_Conv(ir_node *node)
+{
+ ir_graph *irg = get_irn_irg(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *lower_block = get_nodes_block(node);
+
+ part_block(node);
+
+ {
+ ir_node *block = get_nodes_block(node);
+ ir_node *float_x = get_Conv_op(node);
+ ir_mode *mode_u = get_irn_mode(node);
+ ir_mode *mode_s = find_signed_mode(mode_u);
+ ir_mode *mode_f = get_irn_mode(float_x);
+ ir_tarval *limit = new_tarval_from_double(2147483648., mode_f);
+ ir_node *limitc = new_r_Const(irg, limit);
+ ir_node *cmp = new_rd_Cmp(dbgi, block, float_x, limitc,
+ ir_relation_greater_equal);
+ ir_node *cond = new_rd_Cond(dbgi, block, cmp);
+ ir_node *proj_true = new_r_Proj(cond, mode_X, pn_Cond_true);
+ ir_node *proj_false = new_r_Proj(cond, mode_X, pn_Cond_false);
+ ir_node *in_true[1] = { proj_true };
+ ir_node *in_false[1] = { proj_false };
+ ir_node *true_block = new_r_Block(irg, ARRAY_SIZE(in_true), in_true);
+ ir_node *false_block = new_r_Block(irg, ARRAY_SIZE(in_false),in_false);
+ ir_node *true_jmp = new_r_Jmp(true_block);
+ ir_node *false_jmp = new_r_Jmp(false_block);
+
+ ir_tarval *correction = new_tarval_from_long(0x80000000l, mode_s);
+ ir_node *c_const = new_r_Const(irg, correction);
+ ir_node *sub = new_rd_Sub(dbgi, true_block, float_x, limitc,
+ mode_f);
+ ir_node *sub_conv = new_rd_Conv(dbgi, true_block, sub, mode_s);
+ ir_node *xorn = new_rd_Eor(dbgi, true_block, sub_conv, c_const,
+ mode_s);
+
+ ir_node *converted = new_rd_Conv(dbgi, false_block, float_x,mode_s);
+
+ ir_node *lower_in[2] = { true_jmp, false_jmp };
+ ir_node *phi_in[2] = { xorn, converted };
+ ir_node *phi;
+ ir_node *res_conv;
+
+ set_irn_in(lower_block, ARRAY_SIZE(lower_in), lower_in);
+ phi = new_r_Phi(lower_block, ARRAY_SIZE(phi_in), phi_in, mode_s);
+ assert(get_Block_phis(lower_block) == NULL);
+ set_Block_phis(lower_block, phi);
+ set_Phi_next(phi, NULL);
+
+ res_conv = new_rd_Conv(dbgi, lower_block, phi, mode_u);
+ exchange(node, res_conv);
+ }
+}
+
static int sparc_rewrite_Conv(ir_node *node, void *ctx)
{
ir_mode *to_mode = get_irn_mode(node);
(void) ctx;
if (mode_is_float(to_mode) && mode_is_int(from_mode)
- && get_mode_size_bits(from_mode) == 32
- && !mode_is_signed(from_mode)) {
+ && get_mode_size_bits(from_mode) == 32
+ && !mode_is_signed(from_mode)) {
rewrite_unsigned_float_Conv(node);
return 1;
}
+ if (mode_is_float(from_mode) && mode_is_int(to_mode)
+ && get_mode_size_bits(to_mode) <= 32
+ && !mode_is_signed(to_mode)) {
+ rewrite_float_unsigned_Conv(node);
+ return 1;
+ }
return 0;
}
lower_intrinsics(records, n_records, /*part_block_used=*/ true);
}
-/**
- * Initializes the backend ISA
- */
-static arch_env_t *sparc_init(const be_main_env_t *env)
+static void sparc_init(void)
+{
+ sparc_register_init();
+ sparc_create_opcodes(&sparc_irn_ops);
+ sparc_cconv_init();
+}
+
+static void sparc_finish(void)
+{
+ sparc_free_opcodes();
+}
+
+static arch_env_t *sparc_begin_codegeneration(const be_main_env_t *env)
{
sparc_isa_t *isa = XMALLOC(sparc_isa_t);
*isa = sparc_isa_template;
isa->constants = pmap_create();
- be_gas_elf_type_char = '#';
- be_gas_object_file_format = OBJECT_FILE_FORMAT_ELF;
- be_gas_elf_variant = ELF_VARIANT_SPARC;
-
- sparc_register_init();
- sparc_create_opcodes(&sparc_irn_ops);
- sparc_handle_intrinsics();
- sparc_cconv_init();
+ be_gas_elf_type_char = '#';
+ be_gas_elf_variant = ELF_VARIANT_SPARC;
be_emit_init(env->file_handle);
be_gas_begin_compilation_unit(env);
/**
* Closes the output file and frees the ISA structure.
*/
-static void sparc_done(void *self)
+static void sparc_end_codegeneration(void *self)
{
sparc_isa_t *isa = (sparc_isa_t*)self;
free(isa);
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int sparc_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
-}
-
static void sparc_lower_for_target(void)
{
+ ir_mode *mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
size_t i, n_irgs = get_irp_n_irgs();
lower_calls_with_compounds(LF_RETURN_HIDDEN);
for (i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
ir_lower_mode_b(irg, mode_Iu);
- lower_switch(irg, 4, 256, false);
- lower_alloc(irg, SPARC_STACK_ALIGNMENT, false, SPARC_MIN_STACKSIZE);
+ lower_switch(irg, 4, 256, mode_gp);
+ /* TODO: Pass SPARC_MIN_STACKSIZE as addr_delta as soon as
+ * Alloc nodes are implemented more efficiently. */
+ lower_alloc(irg, SPARC_STACK_ALIGNMENT, true, 0);
}
}
p.type_long_long = type_long_long;
p.type_unsigned_long_long = type_unsigned_long_long;
- if (sparc_isa_template.fpu_arch == SPARC_FPU_ARCH_SOFTFLOAT) {
- p.mode_float_arithmetic = NULL;
- p.type_long_double = NULL;
- } else {
- ir_type *type_long_double = new_type_primitive(mode_Q);
+ ir_type *type_long_double = new_type_primitive(mode_Q);
- set_type_alignment_bytes(type_long_double, 8);
- set_type_size_bytes(type_long_double, 16);
- p.type_long_double = type_long_double;
- }
+ set_type_alignment_bytes(type_long_double, 8);
+ set_type_size_bytes(type_long_double, 16);
+ p.type_long_double = type_long_double;
return &p;
}
-static ir_graph **sparc_get_backend_irg_list(const void *self,
- ir_graph ***irgs)
-{
- (void) self;
- (void) irgs;
- return NULL;
-}
-
static asm_constraint_flags_t sparc_parse_asm_constraint(const char **c)
{
(void) c;
const arch_isa_if_t sparc_isa_if = {
sparc_init,
- sparc_lower_for_target,
- sparc_done,
- NULL, /* handle intrinsics */
- NULL,
- sparc_get_reg_class_alignment,
+ sparc_finish,
sparc_get_backend_params,
- sparc_get_backend_irg_list,
- NULL, /* mark remat */
+ sparc_lower_for_target,
sparc_parse_asm_constraint,
sparc_is_valid_clobber,
- sparc_init_graph,
- NULL, /* get_pic_base */
- NULL, /* before_abi */
+ sparc_begin_codegeneration,
+ sparc_end_codegeneration,
+ NULL,
+ NULL, /* get call abi */
+ NULL, /* mark remat */
+ NULL, /* get_pic_base */
+ sparc_new_spill,
+ sparc_new_reload,
+ NULL, /* register_saved_by */
+
+ sparc_handle_intrinsics,
+ NULL, /* before_abi */
sparc_prepare_graph,
sparc_before_ra,
- sparc_finish,
+ sparc_finish_graph,
sparc_emit_routine,
- NULL, /* register_saved_by */
- sparc_new_spill,
- sparc_new_reload
};
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_sparc)
projects / libfirm / blobdiff