#!/usr/bin/perl -w
#
-# Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+# Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
#
# This file is part of libFirm.
#
our %nodes;
our %operands;
our %cpu;
+our $default_op_attr_type;
our $default_attr_type;
our $default_cmp_attr;
+our $default_copy_attr;
our %init_attr;
+our $custom_init_attr_func;
our %compare_attr;
+our %copy_attr;
+our %reg_classes;
# include spec file
}
if(!defined(%init_attr)) {
%init_attr = (
- "$default_attr_type" => "\tinit_${arch}_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
+ "$default_attr_type" => "\tinit_${arch}_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
);
}
if(!defined($default_cmp_attr)) {
}
$op_node{op_flags} = "O";
$op_node{cmp_attr} = 'return 1;';
- $op_node{mode} = 'mode_any';
+ $op_node{mode} = 'mode_ANY';
$nodes{$op} = \%op_node;
}
# create c code file from specs
+my @obst_limit_func;
+my @obst_reg_reqs;
my @obst_opvar; # stack for the "ir_op *op_<arch>_<op-name> = NULL;" statements
my @obst_get_opvar; # stack for the get_op_<arch>_<op-name>() functions
my @obst_constructor; # stack for node constructor functions
my $n_opcodes = 0; # number of opcodes
my $ARITY_VARIABLE = -1;
my $ARITY_DYNAMIC = -2;
+my %requirements = ();
+my %limit_bitsets = ();
+my %reg2class = ();
+my %regclass2len = ();
+
+# build register->class hashes
+foreach my $class_name (keys(%reg_classes)) {
+ my @class = @{ $reg_classes{"$class_name"} };
+ my $old_classname = $class_name;
+
+ pop(@class);
+
+ $class_name = $arch."_".$class_name;
+
+ my $idx = 0;
+ foreach (@class) {
+ $reg2class{$_->{name}} = {
+ "class" => $old_classname,
+ "index" => $idx
+ };
+ $idx++;
+ }
+
+ $regclass2len{$old_classname} = $idx;
+}
+
# for registering additional opcodes
$n_opcodes += $additional_opcodes if (defined($additional_opcodes));
-push(@obst_header, "void ".$arch."_create_opcodes(void);\n");
+push(@obst_header, "void ".$arch."_create_opcodes(const arch_irn_ops_t *be_ops);\n");
push(@obst_enum_op, "typedef enum _$arch\_opcodes {\n");
foreach my $op (keys(%nodes)) {
$attr_type = $default_attr_type;
}
+ # determine hash function
+ my $hash_func;
+ if (exists($n{"hash_func"})) {
+ $hash_func = $n{"hash_func"};
+ }
+
# determine compare function
my $cmp_attr_func;
if (exists($n{"cmp_attr"})) {
$temp .= "\tint n_res = ${out_arity};\n";
}
- my $latency = $n{"latency"};
- if (!defined($latency)) {
- $latency = 1;
- }
- $temp .= "\tunsigned latency = ${latency};\n";
-
if (defined($known_mode)) {
$temp .= "\tir_mode *mode = ${known_mode};\n";
}
undef my @out;
@out = @{ $req{"out"} } if exists(($req{"out"}));
+ for(my $idx = 0; $idx < $#in; $idx++) {
+ my $req = $in[$idx];
+ generate_requirements($req, \%n, $op, $idx, 1);
+ }
+ for(my $idx = 0; $idx < $#out; $idx++) {
+ my $req = $out[$idx];
+ generate_requirements($req, \%n, $op, $idx, 0);
+ }
+
if (@in) {
if($arity >= 0 && scalar(@in) != $arity) {
die "Fatal error: Arity and number of in requirements don't match for ${op}\n";
$temp .= "\tstatic const arch_register_req_t *in_reqs[] =\n";
$temp .= "\t{\n";
for ($idx = 0; $idx <= $#in; $idx++) {
- $temp .= "\t\t&".$op."_reg_req_in_".$idx.",\n";
+ my $req = $in[$idx];
+ my $reqstruct = generate_requirements($req, \%n, $op, $idx, 1);
+ $temp .= "\t\t& ${reqstruct},\n";
}
$temp .= "\t};\n";
} else {
$temp .= "\tstatic const arch_register_req_t *out_reqs[] =\n";
$temp .= "\t{\n";
for ($idx = 0; $idx <= $#out; $idx++) {
- $temp .= "\t\t&".$op."_reg_req_out_".$idx.",\n";
+ my $req = $out[$idx];
+ my $reqstruct = generate_requirements($req, \%n, $op, $idx, 0);
+ $temp .= "\t\t& ${reqstruct},\n";
}
$temp .= "\t};\n";
} else {
die "Fatal error: Couldn't find attribute initialisation code for type '${attr_type}'";
}
$temp .= "${attr_init_code}\n";
+ if(defined($custom_init_attr_func)) {
+ $temp .= &$custom_init_attr_func(\%n, $op);
+ }
$temp .= "\n";
# set flags for outs
- if ($#out_flags >= 0) {
- $temp .= "\t/* set flags for outs */\n";
- for (my $idx = 0; $idx <= $#out_flags; $idx++) {
- my $flags = "";
- my $prefix = "";
-
- foreach my $flag (split(/\|/, $out_flags[$idx])) {
- if ($flag eq "I") {
- $flags .= $prefix."arch_irn_flags_ignore";
- $prefix = " | ";
- }
- elsif ($flag eq "S") {
- $flags .= $prefix."arch_irn_flags_modify_sp";
- $prefix = " | ";
+ if (exists($n{"outs"})) {
+ undef my @outs;
+ @outs = @{ $n{"outs"} };
+
+ for (my $idx = 0; $idx <= $#outs; $idx++) {
+ # check, if we have additional flags annotated to out
+ if ($outs[$idx] =~ /:((S|I)(\|(S|I))*)/) {
+ my $flag_string = $1;
+ my $prefix = "";
+ my $flags = "";
+
+ foreach my $flag (split(/\|/, $flag_string)) {
+ if ($flag eq "I") {
+ $flags .= $prefix."arch_irn_flags_ignore";
+ $prefix = " | ";
+ } elsif ($flag eq "S") {
+ $flags .= $prefix."arch_irn_flags_modify_sp";
+ $prefix = " | ";
+ }
}
- }
- $temp .= "\tset_$arch\_out_flags(res, $flags, $idx);\n";
+ $temp .= "\tset_$arch\_out_flags(res, $flags, $idx);\n";
+ }
}
- $temp .= "\n";
}
-
if (exists($n{"init_attr"})) {
$temp .= "\tattr = get_irn_generic_attr(res);\n";
$temp .= "\t".$n{"init_attr"}."\n";
push(@obst_new_irop, "\n\tmemset(&ops, 0, sizeof(ops));\n");
+ push(@obst_new_irop, "\tops.be_ops = be_ops;\n");
push(@obst_new_irop, "\tops.dump_node = $arch\_dump_node;\n");
if (defined($cmp_attr_func)) {
push(@obst_new_irop, "\tops.node_cmp_attr = ${cmp_attr_func};\n");
}
+ my $copy_attr_func = $copy_attr{$attr_type};
+ if (!defined($copy_attr_func)) {
+ $copy_attr_func = $default_copy_attr;
+ }
+ if (defined($copy_attr_func)) {
+ push(@obst_new_irop, "\tops.copy_attr = ${copy_attr_func};\n");
+ }
+ if (defined($hash_func)) {
+ push(@obst_new_irop, "\tops.hash = ${hash_func};\n");
+ }
$n_opcodes++;
my $n_res = $out_arity;
$temp = "\top_$op = new_ir_op(cur_opcode + iro_$op, \"$op\", op_pin_state_".$n{"state"}.", ".$n{"op_flags"};
$temp .= "|M, ".translate_arity($arity).", 0, sizeof(${attr_type}), &ops);\n";
push(@obst_new_irop, $temp);
- push(@obst_new_irop, "\tset_op_tag(op_$op, &$arch\_op_tag);\n");
+ push(@obst_new_irop, "\tset_op_tag(op_$op, $arch\_op_tag);\n");
+ if(defined($default_op_attr_type)) {
+ push(@obst_new_irop, "\tattr = &attrs[iro_$op];\n");
+ if(defined($n{op_attr_init})) {
+ push(@obst_new_irop, "\t".$n{op_attr_init}."\n");
+ }
+ push(@obst_new_irop, "\tset_op_attr(op_$op, attr);\n");
+ }
+
push(@obst_enum_op, "\tiro_$op,\n");
push(@obst_header, "\n");
open(OUT, ">$target_c") || die("Fatal error: Could not open $target_c, reason: $!\n");
-print OUT "#include \"gen_$arch\_regalloc_if_t.h\"\n\n";
+print OUT "#include \"gen_$arch\_regalloc_if.h\"\n\n";
print OUT @obst_cmp_attr;
print OUT "\n";
print OUT @obst_opvar;
print OUT<<ENDOFISIRN;
/** A tag for the $arch opcodes. Note that the address is used as a tag value, NOT the FOURCC code. */
-static unsigned $arch\_op_tag = FOURCC('$a', '$b', '$c', '$d');
+#define $arch\_op_tag FOURCC('$a', '$b', '$c', '$d')
/** Return the opcode number of the first $arch opcode. */
int get_$arch\_opcode_first(void) {
/** Return 1 if the given opcode is a $arch machine op, 0 otherwise */
int is_$arch\_op(const ir_op *op) {
- return get_op_tag(op) == &$arch\_op_tag;
+ return get_op_tag(op) == $arch\_op_tag;
}
/** Return 1 if the given node is a $arch machine node, 0 otherwise */
ENDOFISIRN
+print OUT <<END;
+#ifdef BIT
+#undef BIT
+#endif
+#define BIT(x) (1 << (x % 32))
+
+END
+
+print OUT @obst_limit_func;
+print OUT "\n";
+
+print OUT @obst_reg_reqs;
+print OUT "\n";
+
print OUT @obst_constructor;
print OUT<<ENDOFMAIN;
* Creates the $arch specific Firm machine operations
* needed for the assembler irgs.
*/
-void $arch\_create_opcodes(void) {
+void $arch\_create_opcodes(const arch_irn_ops_t *be_ops) {
#define N irop_flag_none
#define L irop_flag_labeled
#define C irop_flag_commutative
#define K irop_flag_keep
#define M irop_flag_machine
#define O irop_flag_machine_op
+#define NB irop_flag_dump_noblock
+#define NI irop_flag_dump_noinput
#define R (irop_flag_user << 0)
ir_op_ops ops;
int cur_opcode;
static int run_once = 0;
+ int i;
+ENDOFMAIN
+
+ if (defined($default_op_attr_type)) {
+ print OUT "\t$default_op_attr_type *attr, *attrs;\n";
+ }
+
+print OUT<<ENDOFMAIN;
if (run_once)
return;
run_once = 1;
+ /* we handle all middleend nodes as well that have no other handler */
+ for (i = 0; i <= iro_Last; ++i) {
+ ir_op *op = get_irp_opcode(i);
+ if (op->ops.be_ops == NULL)
+ op->ops.be_ops = be_ops;
+ }
+
cur_opcode = get_next_ir_opcodes(iro_$arch\_last);
$arch\_opcode_start = cur_opcode;
ENDOFMAIN
+ if (defined($default_op_attr_type)) {
+ print OUT "\tattrs = xmalloc(sizeof(attr[0]) * iro_$arch\_last);\n";
+ print OUT "\tmemset(attrs, 0, sizeof(attr[0]) * iro_$arch\_last);\n";
+ }
+
print OUT @obst_new_irop;
print OUT "\n";
print OUT "\t$arch\_register_additional_opcodes(cur_opcode);\n" if (defined($additional_opcodes));
return $ret;
}
+
+sub mangle_requirements {
+ my $reqs = shift;
+ my $class = shift;
+
+ my @alternatives = split(/ /, $reqs);
+ for(my $idx = 0; $idx < scalar(@alternatives); $idx++) {
+ $alternatives[$idx] =~ s/!/not_/g;
+ }
+
+ @alternatives = sort @alternatives;
+
+ my $name = $class."_".join('_', @alternatives);
+
+ return $name;
+}
+
+###
+# Determines whether $name is a specified register class or not.
+# @return 1 if name is register class, 0 otherwise
+###
+sub is_reg_class {
+ my $name = shift;
+ return 1 if exists($reg_classes{"$name"});
+ return 0;
+}
+
+###
+# Returns the register class for a given register.
+# @return class or undef
+###
+sub get_reg_class {
+ my $reg = shift;
+ $reg = substr($reg, 1) if ($reg =~ /!.*/);
+ return $reg2class{"$reg"}{"class"} if (exists($reg2class{"$reg"}));
+ return undef;
+}
+
+###
+# Returns the index of a given register within it's register class.
+# @return index or undef
+###
+sub get_reg_index {
+ my $reg = shift;
+ return $reg2class{"$reg"}{"index"} if (exists($reg2class{"$reg"}));
+ return undef;
+}
+
+###
+# Remember the register class for each index in the given requirements.
+# We need this information for requirements like "in_sX" or "out_dX"
+# @return array of classes corresponding to the requirement for each index
+###
+sub build_inout_idx_class {
+ my $n = shift;
+ my $op = shift;
+ my $is_in = shift;
+ my @idx_class;
+
+ my $inout = ($is_in ? "in" : "out");
+
+ if (exists($n->{"reg_req"}{"$inout"})) {
+ my @reqs = @{ $n->{"reg_req"}{"$inout"} };
+
+ for (my $idx = 0; $idx <= $#reqs; $idx++) {
+ my $class = undef;
+
+ if ($reqs[$idx] eq "none") {
+ $class = "none";
+ } elsif (is_reg_class($reqs[$idx])) {
+ $class = $reqs[$idx];
+ } else {
+ my @regs = split(/ /, $reqs[$idx]);
+GET_CLASS: foreach my $reg (@regs) {
+ if ($reg =~ /!?(in|out)\_r\d+/ || $reg =~ /!in/) {
+ $class = "UNKNOWN_CLASS";
+ } else {
+ $class = get_reg_class($reg);
+ if (!defined $class) {
+ die("Fatal error: Could not get ".uc($inout)." register class for '$op' pos $idx (reg $reg) ... exiting.\n");
+ } else {
+ last GET_CLASS;
+ } # !defined class
+ } # if (reg =~ ...
+ } # foreach
+ } # if
+
+ push(@idx_class, $class);
+ } # for
+ } # if
+
+ return @idx_class;
+}
+
+###
+# Generates the function for a given $op and a given IN-index
+# which returns a subset of possible register from a register class
+# @return classname from which the subset is derived or undef and
+# pos which corresponds to in/out reference position or undef
+###
+sub build_subset_class_func {
+ my $neg = undef;
+ my $class = undef;
+ my $has_limit = 0;
+ my $limit_name;
+ my $same_pos = 0;
+ my $different_pos = 0;
+ my $temp;
+ my @obst_init;
+ my @obst_limits;
+ my @obst_ignore;
+ my @limit_array;
+ my $limit_reqs; #used for name mangling
+
+ # build function header
+ my $node = shift;
+ my $op = shift;
+ my $idx = shift;
+ my $is_in = shift;
+ my @regs = split(/ /, shift);
+
+ my @idx_class = build_inout_idx_class($node, $op, !$is_in);
+
+ # set/unset registers
+CHECK_REQS: foreach (@regs) {
+ if (!$is_in && /(!)?in_r(\d+)/) {
+ my $bit_pos = 1 << ($2 - 1);
+ if ($different_pos & $bit_pos) {
+ if ($1) {
+ print STDERR "duplicate !in constraint\n";
+ } else {
+ print STDERR "conflicting !in and in constraints\n";
+ }
+ return (undef, undef, undef, undef);
+ }
+
+ if ($same_pos & $bit_pos) {
+ if ($1) {
+ print STDERR "conflicting !in and in constraints\n";
+ } else {
+ print STDERR "duplicate in constraint\n";
+ }
+ return (undef, undef, undef, undef);
+ }
+
+ if ($1) {
+ $different_pos |= $bit_pos;
+ } else {
+ $same_pos |= $bit_pos;
+ }
+
+ $class = $idx_class[$2 - 1];
+ next CHECK_REQS;
+ }
+
+ # check for negate
+ if (substr($_, 0, 1) eq "!") {
+ if (defined($neg) && $neg == 0) {
+ # we have seen a positiv constraint as first one but this one is negative
+ # this doesn't make sense
+ print STDERR "Mixed positive and negative constraints for the same slot are not allowed.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ if (!defined($neg)) {
+ $has_limit = 1;
+ }
+
+ $_ = substr($_, 1); # skip '!'
+ $neg = 1;
+ } else {
+ if (defined($neg) && $neg == 1) {
+ # we have seen a negative constraint as first one but this one is positive
+ # this doesn't make sense
+ print STDERR "Mixed positive and negative constraints for the same slot are not allowed.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ $has_limit = 1;
+ $neg = 0;
+ }
+
+ # check if register belongs to one of the given classes
+ $temp = get_reg_class($_);
+ if (!defined($temp)) {
+ print STDERR "Unknown register '$_'!\n";
+ return (undef, undef, undef, undef);
+ }
+
+ # set class
+ if (!defined($class)) {
+ $class = $temp;
+ } elsif ($class ne $temp) {
+ # all registers must belong to the same class
+ print STDERR "Registerclass mismatch. '$_' is not member of class '$class'.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ # calculate position inside the initializer bitfield (only 32 bits per
+ # element)
+ my $regidx = get_reg_index($_);
+ my $arrayp = $regidx / 32;
+ push(@{$limit_array[$arrayp]}, $_);
+ $limit_reqs .= "$_ ";
+ }
+
+ # don't allow ignore regs in negative constraints
+ if($neg) {
+ my @cur_class = @{ $reg_classes{"$class"} };
+ for (my $idx = 0; $idx <= $#cur_class; $idx++) {
+ if (defined($cur_class[$idx]{"type"}) && ($cur_class[$idx]{"type"} & 4)) {
+ my $reg = $cur_class[$idx]{"name"};
+ my $regix = get_reg_index($reg);
+ my $arrayp = $regix / 32;
+ push(@{$limit_array[$arrayp]}, $reg);
+ $limit_reqs .= "$reg ";
+ }
+ }
+ }
+
+ if ($has_limit == 1) {
+ $limit_name = "${arch}_limit_".mangle_requirements($limit_reqs, $class);
+
+ if(defined($limit_bitsets{$limit_name})) {
+ $limit_name = $limit_bitsets{$limit_name};
+ return ($class, $limit_name, $same_pos, $different_pos);
+ }
+
+ $limit_bitsets{$limit_name} = $limit_name;
+
+ push(@obst_limit_func, "static const unsigned " . $limit_name . "[] = { ");
+ my $first = 1;
+ my $limitbitsetlen = $regclass2len{$class};
+ my $limitarraylen = $limitbitsetlen / 32 + ($limitbitsetlen % 32 > 0 ? 1 : 0);
+ for(my $i = 0; $i < $limitarraylen; $i++) {
+
+ my $limitarraypart = $limit_array[$i];
+ if($first) {
+ $first = 0;
+ } else {
+ push(@obst_limit_func, ", ");
+ }
+ my $temp;
+ if($neg) {
+ $temp = "0xFFFFFFFF";
+ }
+ foreach my $reg (@{$limitarraypart}) {
+ if($neg) {
+ $temp .= " & ~";
+ } elsif(defined($temp)) {
+ $temp .= " | ";
+ }
+ $temp .= "BIT(REG_".uc(${reg}).")";
+ }
+ if(defined($temp)) {
+ push(@obst_limit_func, "${temp}");
+ } else {
+ push(@obst_limit_func, "0");
+ }
+ }
+ push(@obst_limit_func, " };\n");
+ }
+
+ return ($class, $limit_name, $same_pos, $different_pos);
+}
+
+###
+# Generate register requirements structure
+###
+sub generate_requirements {
+ my $reqs = shift;
+ my $node = shift;
+ my $op = shift;
+ my $idx = shift;
+ my $is_in = shift;
+ my $class = "";
+ my $result;
+
+ if ($reqs eq "none") {
+
+ $result = <<EOF;
+{
+ arch_register_req_type_none,
+ NULL, /* regclass */
+ NULL, /* limit bitset */
+ 0, /* same pos */
+ 0 /* different pos */
+};
+
+EOF
+ } elsif ($reqs =~ /^new_reg_(.*)$/) {
+ if(!is_reg_class($1)) {
+ die "$1 is not a register class in requirements for $op\n";
+ }
+ $class = $1;
+ $result = <<EOF;
+{
+ arch_register_req_type_should_be_different_from_all,
+ & ${arch}_reg_classes[CLASS_${arch}_${class}],
+ NULL, /* limit bitset */
+ 0, /* same pos */
+ 0 /* different pos */
+};
+
+EOF
+ } elsif (is_reg_class($reqs)) {
+ $class = $reqs;
+ $result = <<EOF;
+{
+ arch_register_req_type_normal,
+ & ${arch}_reg_classes[CLASS_${arch}_${class}],
+ NULL, /* limit bitset */
+ 0, /* same pos */
+ 0 /* different pos */
+};
+
+EOF
+
+ } else {
+ my @req_type_mask;
+ my ($regclass, $limit_bitset, $same_pos, $different_pos)
+ = build_subset_class_func($node, $op, $idx, $is_in, $reqs);
+
+ if (!defined($regclass)) {
+ die("Fatal error: Could not build subset for requirements '$reqs' of '$op' pos $idx ... exiting.\n");
+ }
+
+ if (defined($limit_bitset) && $limit_bitset ne "NULL") {
+ push(@req_type_mask, "arch_register_req_type_limited");
+ }
+ if ($same_pos != 0) {
+ push(@req_type_mask, "arch_register_req_type_should_be_same");
+ }
+ if ($different_pos != 0) {
+ push(@req_type_mask, "arch_register_req_type_must_be_different");
+ }
+ my $reqtype = join(" | ", @req_type_mask);
+
+ if(!defined($limit_bitset)) {
+ $limit_bitset = "NULL";
+ }
+
+ $class = $regclass;
+ $result = <<EOF;
+{
+ ${reqtype},
+ & ${arch}_reg_classes[CLASS_${arch}_${class}],
+ ${limit_bitset},
+ ${same_pos}, /* same pos */
+ ${different_pos} /* different pos */
+};
+
+EOF
+ }
+
+ my $name = "${arch}_requirements_".mangle_requirements($reqs, $class);
+ if(defined($requirements{$name})) {
+ return $name;
+ }
+ $requirements{$name} = $name;
+ push(@obst_reg_reqs, <<EOF);
+static const arch_register_req_t ${name} = ${result}
+EOF
+
+ return $name;
+}
projects / libfirm / blobdiff