* @author Moritz Kroll, Jens Mueller
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "debug.h"
#include "error.h"
-#include "../bearch_t.h" /* the general register allocator interface */
-#include "../benode_t.h"
+#include "../bearch.h"
+#include "../benode.h"
#include "../belower.h"
-#include "../besched_t.h"
+#include "../besched.h"
#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
#include "../bemodule.h"
#include "../bespillslots.h"
#include "../beblocksched.h"
-#include "../beirg_t.h"
+#include "../beirg.h"
#include "../begnuas.h"
+#include "../belistsched.h"
#include "pset.h"
#include "bearch_ppc32_t.h"
-#include "ppc32_new_nodes.h" /* ppc nodes interface */
-#include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "ppc32_new_nodes.h"
+#include "gen_ppc32_regalloc_if.h"
#include "ppc32_transform.h"
#include "ppc32_transform_conv.h"
#include "ppc32_emitter.h"
* |___/
**************************************************/
-/**
- * Return register requirements for a ppc node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const
-arch_register_req_t *ppc32_get_irn_reg_req(const void *self,
- const ir_node *irn, int pos) {
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
- FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
- (void) self;
-
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
- return arch_no_register_req;
- }
-
- if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
- return arch_no_register_req;
- }
-
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
- if (is_Proj(irn)) {
- /* in case of a proj, we need to get the correct OUT slot */
- /* of the node corresponding to the proj number */
- if (pos == -1) {
- node_pos = ppc32_translate_proj_pos(irn);
- } else {
- node_pos = pos;
- }
-
- irn = skip_Proj_const(irn);
-
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
- }
-
- /* get requirements for our own nodes */
- if (is_ppc32_irn(irn)) {
- const arch_register_req_t *req;
- if (pos >= 0) {
- req = get_ppc32_in_req(irn, pos);
- } else {
- req = get_ppc32_out_req(irn, node_pos);
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
- return req;
- }
-
- /* unknowns should be transformed by now */
- assert(!is_Unknown(irn));
-
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- return arch_no_register_req;
-}
-
-static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
- int pos = 0;
- (void) self;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- pos = ppc32_translate_proj_pos(irn);
- irn = skip_Proj(irn);
- }
-
- if (is_ppc32_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_ppc32_slots(irn);
- slots[pos] = reg;
- }
- else {
- /* here we set the registers for the Phi nodes */
- ppc32_set_firm_reg(irn, reg, cur_reg_set);
- }
-}
-
-static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
- int pos = 0;
- const arch_register_t *reg = NULL;
- (void) self;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return NULL;
- }
-
- pos = ppc32_translate_proj_pos(irn);
- irn = skip_Proj_const(irn);
- }
-
- if (is_ppc32_irn(irn)) {
- const arch_register_t **slots;
- slots = get_ppc32_slots(irn);
- reg = slots[pos];
- }
- else {
- reg = ppc32_get_firm_reg(irn, cur_reg_set);
- }
-
- return reg;
-}
-
-static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
- (void) self;
- irn = skip_Proj_const(irn);
-
- if (is_cfop(irn)) {
- return arch_irn_class_branch;
- }
- else if (is_ppc32_irn(irn)) {
- return arch_irn_class_normal;
- }
-
- return 0;
-}
-
-static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
- (void) self;
- irn = skip_Proj_const(irn);
-
- if (is_ppc32_irn(irn)) {
- return get_ppc32_flags(irn);
- }
- else if (is_Unknown(irn)) {
- return arch_irn_flags_ignore;
- }
-
+static arch_irn_class_t ppc32_classify(const ir_node *irn)
+{
+ (void) irn;
return 0;
}
-static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
- (void) self;
+static ir_entity *ppc32_get_frame_entity(const ir_node *irn)
+{
if(!is_ppc32_irn(irn)) return NULL;
if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
return get_ppc32_frame_entity(irn);
}
-static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
- (void) self;
+static void ppc32_set_frame_entity(ir_node *irn, ir_entity *ent)
+{
if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
return;
set_ppc32_frame_entity(irn, ent);
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
- (void) self;
+static void ppc32_set_stack_bias(ir_node *irn, int bias)
+{
set_ppc32_offset(irn, bias);
}
-static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
- (void) self;
+static int ppc32_get_sp_bias(const ir_node *irn)
+{
(void) irn;
return 0;
}
*/
static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
{
- ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
+ ppc32_abi_env *env = XMALLOC(ppc32_abi_env);
(void) aenv;
env->call = call;
if(!between_type) {
ir_entity *ret_addr_ent;
- ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
- ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
+ ir_type *ret_addr_type = new_type_primitive(mode_P);
+ ir_type *old_bp_type = new_type_primitive(mode_P);
between_type = new_type_class(new_id_from_str("ppc32_between_type"));
old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
return between_type;
}
-/**
- * Put all registers which are saved by the prologue/epilogue in a set.
- * @param self The callback object.
- * @param regs A set.
- */
-static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
-{
- (void) self;
- (void) regs;
-}
-
/**
* Generate the prologue.
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
* @return The register which shall be used as a stack frame base.
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
ppc32_abi_env *env = (ppc32_abi_env *) self;
be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
(void) mem;
(void) reg_map;
+ (void) stack_bias;
isleaf = flags.bits.irg_is_leaf;
- if(flags.bits.try_omit_fp)
+ if (flags.bits.try_omit_fp)
return &ppc32_gp_regs[REG_R1];
else
return &ppc32_gp_regs[REG_R31];
ppc32_abi_init,
ppc32_abi_done,
ppc32_abi_get_between_type,
- ppc32_abi_regs_saved_by_me,
ppc32_abi_prologue,
ppc32_abi_epilogue,
};
/* fill register allocator interface */
-static const arch_irn_ops_if_t ppc32_irn_ops_if = {
- ppc32_get_irn_reg_req,
- ppc32_set_irn_reg,
- ppc32_get_irn_reg,
+static const arch_irn_ops_t ppc32_irn_ops = {
+ get_ppc32_in_req,
ppc32_classify,
- ppc32_get_flags,
ppc32_get_frame_entity,
ppc32_set_frame_entity,
ppc32_set_stack_bias,
NULL, /* perform_memory_operand */
};
-ppc32_irn_ops_t ppc32_irn_ops = {
- &ppc32_irn_ops_if,
- NULL
-};
-
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
}
-/**
- * These are some hooks which must be filled but are probably not needed.
- */
-static void ppc32_before_sched(void *self) {
- (void) self;
- /* Some stuff you need to do after scheduling but before register allocation */
-}
-
/**
* Called before the register allocator.
* Calculate a block schedule here. We need it for the x87
static void ppc32_transform_spill(ir_node *node, void *env)
{
- ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
+ (void)env;
if(be_is_Spill(node))
{
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
- const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
+ const arch_register_class_t *regclass = arch_get_irn_reg_class(node, 1);
if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
{
- store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
- get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+ store = new_bd_ppc32_Stw(dbg, block,
+ get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
}
else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
{
- store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
- get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+ store = new_bd_ppc32_Stfd(dbg, block,
+ get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
}
else panic("Spill for register class not supported yet!");
set_ppc32_frame_entity(store, be_get_frame_entity(node));
- proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
+ proj = new_rd_Proj(dbg, block, store, mode_M, pn_Store_M);
if (sched_is_scheduled(node)) {
sched_add_after(sched_prev(node), store);
ir_node *block = get_nodes_block(node);
ir_mode *mode = get_irn_mode(node);
- const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
+ const arch_register_class_t *regclass = arch_get_irn_reg_class_out(node);
if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
{
- load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
+ load = new_bd_ppc32_Lwz(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
{
- load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
+ load = new_bd_ppc32_Lfd(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
else panic("Reload for register class not supported yet!");
set_ppc32_frame_entity(load, be_get_frame_entity(node));
- proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
+ proj = new_rd_Proj(dbg, block, load, mode, pn_Load_res);
if (sched_is_scheduled(node)) {
sched_add_after(sched_prev(node), load);
}
/* copy the register from the old node to the new Load */
- reg = arch_get_irn_register(cgenv->arch_env, node);
- arch_set_irn_register(cgenv->arch_env, load, reg);
+ reg = arch_get_irn_register(node);
+ arch_set_irn_register(load, reg);
exchange(node, proj);
}
static void ppc32_after_ra(void *self) {
ppc32_code_gen_t *cg = self;
be_coalesce_spillslots(cg->birg);
- irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
+ irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, NULL);
}
/**
ppc32_before_abi,
ppc32_prepare_graph,
NULL, /* spill */
- ppc32_before_sched, /* before scheduling hook */
ppc32_before_ra, /* before register allocation hook */
ppc32_after_ra,
ppc32_finish_irg,
* Initializes the code generator.
*/
static void *ppc32_cg_init(be_irg_t *birg) {
- ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
- ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
+ ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env;
+ ppc32_code_gen_t *cg = XMALLOC(ppc32_code_gen_t);
cg->impl = &ppc32_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
- cg->arch_env = birg->main_env->arch_env;
cg->isa = isa;
cg->birg = birg;
cg->area_size = 0;
FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
cur_reg_set = cg->reg_set;
- ppc32_irn_ops.cg = cg;
return (arch_code_generator_t *)cg;
}
&ppc32_isa_if, /* isa interface */
&ppc32_gp_regs[REG_R1], /* stack pointer */
&ppc32_gp_regs[REG_R31], /* base pointer */
+ &ppc32_reg_classes[CLASS_ppc32_gp], /* static link pointer class */
-1, /* stack is decreasing */
- 1, /* call stack alignment */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
if (is_SymConst(node)) {
ir_entity *ent = get_SymConst_entity(node);
- set_entity_backend_marked(ent, 1);
- if (! is_direct_entity(ent))
- pset_insert_ptr(symbol_set, ent);
+ pset_insert_ptr(symbol_set, ent);
}
}
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *ppc32_init(FILE *file_handle) {
+static arch_env_t *ppc32_init(FILE *file_handle) {
static int inited = 0;
ppc32_isa_t *isa;
int i;
if (inited)
return NULL;
- isa = xmalloc(sizeof(*isa));
+ isa = XMALLOC(ppc32_isa_t);
memcpy(isa, &ppc32_isa_template, sizeof(*isa));
be_emit_init(file_handle);
ppc32_register_init();
- ppc32_create_opcodes();
+ ppc32_create_opcodes(&ppc32_irn_ops);
inited = 1;
*/
inc_master_type_visited();
- return isa;
+ return &isa->arch_env;
}
static void ppc32_dump_indirect_symbols(ppc32_isa_t *isa) {
static void ppc32_done(void *self) {
ppc32_isa_t *isa = self;
- be_gas_emit_decls(isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env);
be_gas_emit_switch_section(GAS_SECTION_DATA);
ppc32_dump_indirect_symbols(isa);
-static unsigned ppc32_get_n_reg_class(const void *self) {
- (void) self;
+static unsigned ppc32_get_n_reg_class(void)
+{
return N_CLASSES;
}
-static const arch_register_class_t *ppc32_get_reg_class(const void *self,
- unsigned i) {
- (void) self;
+static const arch_register_class_t *ppc32_get_reg_class(unsigned i)
+{
assert(i < N_CLASSES && "Invalid ppc register class requested.");
return &ppc32_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
- (void) self;
+const arch_register_class_t *ppc32_get_reg_class_for_mode(const ir_mode *mode)
+{
if (mode_is_float(mode))
return &ppc32_reg_classes[CLASS_ppc32_fp];
else
be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
(void) self;
- if(get_type_visibility(method_type)!=visibility_external_allocated)
- call_flags.bits.call_has_imm = 1;
+ call_flags.bits.call_has_imm = 1;
/* set stack parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
}
}
-static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- (void) self;
- (void) irn;
- return &ppc32_irn_ops;
-}
-
-const arch_irn_handler_t ppc32_irn_handler = {
- ppc32_get_irn_ops
-};
-
-const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
- (void) self;
- return &ppc32_irn_handler;
-}
-
int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
(void) block_env;
if(!is_ppc32_irn(irn))
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+static int ppc32_get_reg_class_alignment(const arch_register_class_t *cls)
+{
ir_mode *mode = arch_register_class_mode(cls);
- (void) self;
-
return get_mode_size_bytes(mode);
}
-static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
- (void) self;
+static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const ir_node *irn) {
(void) irn;
/* TODO */
- assert(0);
+ panic("Unimplemented ppc32_get_allowed_execution_units()");
return NULL;
}
static const be_machine_t *ppc32_get_machine(const void *self) {
(void) self;
/* TODO */
- assert(0);
+ panic("Unimplemented ppc32_get_machine()");
return NULL;
}
static const backend_params *ppc32_get_libfirm_params(void) {
static backend_params p = {
1, /* need dword lowering */
- 0, /* don't support inlien assembler yet */
- NULL, /* no additional opcodes */
+ 0, /* don't support inline assembler yet */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
NULL, /* no if conversion settings */
+ NULL, /* no float arithmetic mode (TODO) */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL, /* no trampoline support: no trampoline builder */
+ 4 /* alignment of stack parameter */
};
return &p;
}
+static asm_constraint_flags_t ppc32_parse_asm_constraint(const char **c)
+{
+ /* no asm support yet */
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int ppc32_is_valid_clobber(const char *clobber)
+{
+ /* no asm support yet */
+ (void) clobber;
+ return 0;
+}
+
const arch_isa_if_t ppc32_isa_if = {
ppc32_init,
ppc32_done,
+ NULL, /* handle intrinsics */
ppc32_get_n_reg_class,
ppc32_get_reg_class,
ppc32_get_reg_class_for_mode,
ppc32_get_call_abi,
- ppc32_get_irn_handler,
ppc32_get_code_generator_if,
ppc32_get_list_sched_selector,
ppc32_get_ilp_sched_selector,
ppc32_get_allowed_execution_units,
ppc32_get_machine,
ppc32_get_irg_list,
+ NULL, /* mark remat */
+ ppc32_parse_asm_constraint,
+ ppc32_is_valid_clobber
};
void be_init_arch_ppc32(void)
projects / libfirm / blobdiff