-/* The main ppc backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+/**
+ * @file
+ * @brief The main ppc backend driver file.
+ * @author Moritz Kroll, Jens Mueller
+ * @version $Id$
+ */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "bitset.h"
#include "debug.h"
+#include "error.h"
-#include "../bearch.h" /* the general register allocator interface */
+#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
#include "../beabi.h"
+#include "../bemachine.h"
+#include "../bemodule.h"
+#include "../bespillslots.h"
+#include "../beblocksched.h"
+#include "../beirg_t.h"
+#include "../begnuas.h"
#include "pset.h"
#include "ppc32_new_nodes.h" /* ppc nodes interface */
#include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
-#include "ppc32_gen_decls.h" /* interface declaration emitter */
#include "ppc32_transform.h"
#include "ppc32_transform_conv.h"
#include "ppc32_emitter.h"
#define DEBUG_MODULE "firm.be.ppc.isa"
int isleaf;
-pset *symbol_pset = NULL;
/* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
static set *cur_reg_set = NULL;
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
/**
* Return register requirements for a ppc node.
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const ppc32_register_req_t *irn_req;
+static const arch_register_req_t *ppc32_get_irn_reg_req(const ir_node *irn,
+ int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(irn);
FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
if (is_Block(irn) || mode == mode_X || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
- return NULL;
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
- return NULL;
+ return arch_no_register_req;
}
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
/* of the node corresponding to the proj number */
if (pos == -1) {
node_pos = ppc32_translate_proj_pos(irn);
- }
- else {
+ } else {
node_pos = pos;
}
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
}
/* get requirements for our own nodes */
if (is_ppc32_irn(irn)) {
+ const arch_register_req_t *req;
if (pos >= 0) {
- irn_req = get_ppc32_in_req(irn, pos);
- }
- else {
- irn_req = get_ppc32_out_req(irn, node_pos);
+ req = get_ppc32_in_req(irn, pos);
+ } else {
+ req = get_ppc32_out_req(irn, node_pos);
}
DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
-
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
+ return req;
}
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- memcpy(req, &(ppc32_default_req_ppc32_fp.req), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(ppc32_default_req_ppc32_gp.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
+ /* unknowns should be transformed by now */
+ assert(!is_Unknown(irn));
- return req;
+ DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
+ return arch_no_register_req;
}
-static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void ppc32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
+{
int pos = 0;
if (is_Proj(irn)) {
}
pos = ppc32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_ppc32_irn(irn)) {
}
}
-static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *ppc32_get_irn_reg(const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
}
pos = ppc32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
}
if (is_ppc32_irn(irn)) {
return reg;
}
-static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+static arch_irn_class_t ppc32_classify(const ir_node *irn)
+{
+ irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return arch_irn_class_branch;
return 0;
}
-static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+static arch_irn_flags_t ppc32_get_flags(const ir_node *irn)
+{
+ irn = skip_Proj_const(irn);
if (is_ppc32_irn(irn)) {
return get_ppc32_flags(irn);
return 0;
}
-static entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *ppc32_get_frame_entity(const ir_node *irn)
+{
if(!is_ppc32_irn(irn)) return NULL;
if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
return get_ppc32_frame_entity(irn);
}
+static void ppc32_set_frame_entity(ir_node *irn, ir_entity *ent)
+{
+ if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
+ return;
+ set_ppc32_frame_entity(irn, ent);
+}
+
/**
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
+static void ppc32_set_stack_bias(ir_node *irn, int bias)
+{
set_ppc32_offset(irn, bias);
}
+static int ppc32_get_sp_bias(const ir_node *irn)
+{
+ (void) irn;
+ return 0;
+}
+
typedef struct
{
const be_abi_call_t *call;
static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
{
ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
+ (void) aenv;
+
env->call = call;
env->irg = irg;
return env;
static ir_type *ppc32_abi_get_between_type(void *self)
{
static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
+ static ir_entity *old_bp_ent = NULL;
+ (void) self;
if(!between_type) {
- entity *ret_addr_ent;
+ ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_entity_offset(old_bp_ent, 0);
+ set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
}
*/
static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
{
+ (void) self;
+ (void) regs;
}
/**
* Generate the prologue.
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
* @return The register which shall be used as a stack frame base.
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
ppc32_abi_env *env = (ppc32_abi_env *) self;
be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
+ (void) mem;
+ (void) reg_map;
+ (void) stack_bias;
isleaf = flags.bits.irg_is_leaf;
- if(flags.bits.try_omit_fp)
+ if (flags.bits.try_omit_fp)
return &ppc32_gp_regs[REG_R1];
else
return &ppc32_gp_regs[REG_R31];
*/
static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
+ (void) self;
+ (void) bl;
+ (void) mem;
+ (void) reg_map;
}
static const be_abi_callbacks_t ppc32_abi_callbacks = {
/* fill register allocator interface */
-static const arch_irn_ops_if_t ppc32_irn_ops_if = {
+static const arch_irn_ops_t ppc32_irn_ops = {
ppc32_get_irn_reg_req,
ppc32_set_irn_reg,
ppc32_get_irn_reg,
ppc32_classify,
ppc32_get_flags,
ppc32_get_frame_entity,
- ppc32_set_stack_bias
-};
-
-ppc32_irn_ops_t ppc32_irn_ops = {
- &ppc32_irn_ops_if,
- NULL
+ ppc32_set_frame_entity,
+ ppc32_set_stack_bias,
+ ppc32_get_sp_bias,
+ NULL, /* get_inverse */
+ NULL, /* get_op_estimated_cost */
+ NULL, /* possible_memory_operand */
+ NULL, /* perform_memory_operand */
};
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
/**
* Called immediatly before emit phase.
*/
-static void ppc32_finish_irg(ir_graph *irg, ppc32_code_gen_t *cg) {
+static void ppc32_finish_irg(void *self) {
+ (void) self;
/* TODO: - fix offsets for nodes accessing stack
- ...
*/
* These are some hooks which must be filled but are probably not needed.
*/
static void ppc32_before_sched(void *self) {
+ (void) self;
/* Some stuff you need to do after scheduling but before register allocation */
}
*/
static void ppc32_before_ra(void *self) {
ppc32_code_gen_t *cg = self;
- cg->blk_sched = sched_create_block_schedule(cg->irg);
+ cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
}
static void ppc32_transform_spill(ir_node *node, void *env)
store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
}
- else assert(0 && "Spill for register class not supported yet!");
+ else panic("Spill for register class not supported yet!");
set_ppc32_frame_entity(store, be_get_frame_entity(node));
{
load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
- else assert(0 && "Reload for register class not supported yet!");
+ else panic("Reload for register class not supported yet!");
set_ppc32_frame_entity(load, be_get_frame_entity(node));
*/
static void ppc32_after_ra(void *self) {
ppc32_code_gen_t *cg = self;
+ be_coalesce_spillslots(cg->birg);
irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
}
*/
static void ppc32_emit_and_done(void *self) {
ppc32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->isa->out;
-
- if (cg->emit_decls) {
- ppc32_gen_decls(out);
- cg->emit_decls = 0;
- }
+ ir_graph *irg = cg->irg;
- ppc32_finish_irg(irg, cg);
dump_ir_block_graph_sched(irg, "-ppc-finished");
- ppc32_gen_routine(out, irg, cg);
+ ppc32_gen_routine(cg, irg);
cur_reg_set = NULL;
/* de-allocate code generator */
del_set(cg->reg_set);
free(self);
-
- if(symbol_pset)
- {
- del_pset(symbol_pset);
- symbol_pset = NULL;
- }
}
-int is_direct_entity(entity *ent);
+int is_direct_entity(ir_entity *ent);
-/**
- * Collects all SymConsts which need to be accessed "indirectly"
- *
- * @param node the firm node
- * @param env the debug module
- */
-void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
- if(get_irn_op(node) == op_SymConst)
- {
- entity *ent = get_SymConst_entity(node);
- if(!is_direct_entity(ent))
- pset_insert_ptr(symbol_pset, ent);
- }
-}
-
-static void *ppc32_cg_init(const be_irg_t *birg);
+static void *ppc32_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t ppc32_code_gen_if = {
ppc32_cg_init,
+ NULL, /* get_pic_base */
ppc32_before_abi,
ppc32_prepare_graph,
+ NULL, /* spill */
ppc32_before_sched, /* before scheduling hook */
ppc32_before_ra, /* before register allocation hook */
ppc32_after_ra,
+ ppc32_finish_irg,
ppc32_emit_and_done
};
/**
* Initializes the code generator.
*/
-static void *ppc32_cg_init(const be_irg_t *birg) {
- ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
+static void *ppc32_cg_init(be_irg_t *birg) {
+ ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env;
ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
cg->impl = &ppc32_code_gen_if;
cg->blk_sched = NULL;
FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- {
- int i;
- cg->emit_decls = 1;
- symbol_pset = pset_new_ptr(8);
- for(i=0; i<get_irp_n_irgs(); i++)
- {
- cg->irg = get_irp_irg(i);
- irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
- }
- cg->irg = birg->irg;
- }
-
cur_reg_set = cg->reg_set;
- ppc32_irn_ops.cg = cg;
-
return (arch_code_generator_t *)cg;
}
*****************************************************************/
static ppc32_isa_t ppc32_isa_template = {
- &ppc32_isa_if,
- &ppc32_gp_regs[REG_R1], // stack pointer
- &ppc32_gp_regs[REG_R31], // base pointer
- -1, // stack is decreasing
- 0, // num codegens... ??
- NULL
+ {
+ &ppc32_isa_if, /* isa interface */
+ &ppc32_gp_regs[REG_R1], /* stack pointer */
+ &ppc32_gp_regs[REG_R31], /* base pointer */
+ -1, /* stack is decreasing */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
+ NULL, /* main environment */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ },
+ NULL /* symbol set */
};
+/**
+ * Collects all SymConsts which need to be accessed "indirectly"
+ *
+ * @param node the firm node
+ * @param env the symbol set
+ */
+static void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
+ pset *symbol_set = env;
+
+ if (is_SymConst(node)) {
+ ir_entity *ent = get_SymConst_entity(node);
+ set_entity_backend_marked(ent, 1);
+ if (! is_direct_entity(ent))
+ pset_insert_ptr(symbol_set, ent);
+ }
+}
+
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *ppc32_init(FILE *file_handle) {
+static arch_env_t *ppc32_init(FILE *file_handle) {
static int inited = 0;
ppc32_isa_t *isa;
+ int i;
- if(inited)
+ if (inited)
return NULL;
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ppc32_isa_template, sizeof(*isa));
- isa->out = file_handle;
+ be_emit_init(file_handle);
- ppc32_register_init(isa);
- ppc32_create_opcodes();
+ ppc32_register_init();
+ ppc32_create_opcodes(&ppc32_irn_ops);
inited = 1;
- return isa;
+ isa->symbol_set = pset_new_ptr(8);
+ for (i = 0; i < get_irp_n_irgs(); ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ irg_walk_blkwise_graph(irg, NULL, ppc32_collect_symconsts_walk, isa->symbol_set);
+ }
+
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
+
+ return &isa->arch_env;
}
+static void ppc32_dump_indirect_symbols(ppc32_isa_t *isa) {
+ ir_entity *ent;
+ foreach_pset(isa->symbol_set, ent) {
+ const char *ld_name = get_entity_ld_name(ent);
+ be_emit_irprintf(".non_lazy_symbol_pointer\n%s:\n\t.indirect_symbol _%s\n\t.long 0\n\n", ld_name, ld_name);
+ be_emit_write_line();
+ }
+}
/**
* Closes the output file and frees the ISA structure.
*/
static void ppc32_done(void *self) {
+ ppc32_isa_t *isa = self;
+
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
+ be_gas_emit_switch_section(GAS_SECTION_DATA);
+ ppc32_dump_indirect_symbols(isa);
+
+ be_emit_exit();
+ del_pset(isa->symbol_set);
+
free(self);
}
-static int ppc32_get_n_reg_class(const void *self) {
+static unsigned ppc32_get_n_reg_class(const void *self) {
+ (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
+static const arch_register_class_t *ppc32_get_reg_class(const void *self,
+ unsigned i) {
+ (void) self;
+ assert(i < N_CLASSES && "Invalid ppc register class requested.");
return &ppc32_reg_classes[i];
}
* @return A register class which can hold values of the given mode.
*/
const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+ (void) self;
if (mode_is_float(mode))
return &ppc32_reg_classes[CLASS_ppc32_fp];
else
const arch_register_t *reg;
be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
+ (void) self;
if(get_type_visibility(method_type)!=visibility_external_allocated)
call_flags.bits.call_has_imm = 1;
for (i = 0; i < n; i++) {
tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
if(is_atomic_type(tp))
{
- mode = get_type_mode(tp);
-
if(mode_is_float(mode))
{
if(fpregi <= REG_F13)
be_abi_call_param_reg(abi, i, reg);
else
{
- be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
+ be_abi_call_param_stack(abi, i, mode, 4, stackoffs - lastoffs, 0);
lastoffs = stackoffs+stackparamsize;
}
stackoffs += stackparamsize;
}
else
{
- be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
+ be_abi_call_param_stack(abi, i, mode, 4, stackoffs - lastoffs, 0);
stackoffs += (get_type_size_bytes(tp)+3) & -4;
lastoffs = stackoffs;
}
}
}
-static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- return &ppc32_irn_ops;
-}
-
-const arch_irn_handler_t ppc32_irn_handler = {
- ppc32_get_irn_ops
-};
-
-const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
- return &ppc32_irn_handler;
-}
-
int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ppc32_irn(irn);
+ (void) block_env;
+ if(!is_ppc32_irn(irn))
+ return -1;
+
+ return 1;
}
/**
* Initializes the code generator interface.
*/
static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
+ (void) self;
return &ppc32_code_gen_if;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self) {
- memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
+static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+ (void) self;
+ (void) selector;
+ ppc32_sched_selector = trivial_selector;
ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
return &ppc32_sched_selector;
}
+static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
+ (void) self;
+ return NULL;
+}
+
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
ir_mode *mode = arch_register_class_mode(cls);
+ (void) self;
+
return get_mode_size_bytes(mode);
}
-#ifdef WITH_LIBCORE
-static void ppc32_register_options(lc_opt_entry_t *ent)
+static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ (void) self;
+ (void) irn;
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+static const be_machine_t *ppc32_get_machine(const void *self) {
+ (void) self;
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+/**
+ * Return irp irgs in the desired order.
+ */
+static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) {
+ (void) self;
+ (void) irg_list;
+ return NULL;
+}
+
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *ppc32_get_libfirm_params(void) {
+ static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ 0, /* no immediate floating point mode. */
+ NULL, /* no additional opcodes */
+ NULL, /* will be set later */
+ NULL, /* but yet no creator function */
+ NULL, /* context for create_intrinsic_fkt */
+ NULL, /* no if conversion settings */
+ NULL /* no immediate fp mode */
+ };
+
+ return &p;
+}
+
+static asm_constraint_flags_t ppc32_parse_asm_constraint(const void *self, const char **c)
+{
+ /* no asm support yet */
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int ppc32_is_valid_clobber(const void *self, const char *clobber)
{
+ /* no asm support yet */
+ (void) self;
+ (void) clobber;
+ return 0;
}
-#endif /* WITH_LIBCORE */
const arch_isa_if_t ppc32_isa_if = {
ppc32_init,
ppc32_get_reg_class,
ppc32_get_reg_class_for_mode,
ppc32_get_call_abi,
- ppc32_get_irn_handler,
ppc32_get_code_generator_if,
ppc32_get_list_sched_selector,
+ ppc32_get_ilp_sched_selector,
ppc32_get_reg_class_alignment,
-#ifdef WITH_LIBCORE
- ppc32_register_options
-#endif
+ ppc32_get_libfirm_params,
+ ppc32_get_allowed_execution_units,
+ ppc32_get_machine,
+ ppc32_get_irg_list,
+ ppc32_parse_asm_constraint,
+ ppc32_is_valid_clobber
};
+
+void be_init_arch_ppc32(void)
+{
+ be_register_isa_if("ppc32", &ppc32_isa_if);
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);
projects / libfirm / blobdiff