/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "bitset.h"
#include "debug.h"
+#include "error.h"
#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
#include "../bemodule.h"
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const
-arch_register_req_t *ppc32_get_irn_reg_req(const void *self,
- const ir_node *irn, int pos) {
+static const arch_register_req_t *ppc32_get_irn_reg_req(const ir_node *irn,
+ int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(irn);
FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
return arch_no_register_req;
}
-static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void ppc32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
+{
int pos = 0;
if (is_Proj(irn)) {
}
}
-static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *ppc32_get_irn_reg(const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
return reg;
}
-static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
+static arch_irn_class_t ppc32_classify(const ir_node *irn)
+{
irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return 0;
}
-static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
+static arch_irn_flags_t ppc32_get_flags(const ir_node *irn)
+{
irn = skip_Proj_const(irn);
if (is_ppc32_irn(irn)) {
return 0;
}
-static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *ppc32_get_frame_entity(const ir_node *irn)
+{
if(!is_ppc32_irn(irn)) return NULL;
if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
return get_ppc32_frame_entity(irn);
}
-static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+static void ppc32_set_frame_entity(ir_node *irn, ir_entity *ent)
+{
if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
return;
set_ppc32_frame_entity(irn, ent);
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
+static void ppc32_set_stack_bias(ir_node *irn, int bias)
+{
set_ppc32_offset(irn, bias);
}
-static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
+static int ppc32_get_sp_bias(const ir_node *irn)
+{
+ (void) irn;
return 0;
}
static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
{
ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
+ (void) aenv;
+
env->call = call;
env->irg = irg;
return env;
{
static ir_type *between_type = NULL;
static ir_entity *old_bp_ent = NULL;
+ (void) self;
if(!between_type) {
ir_entity *ret_addr_ent;
*/
static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
{
+ (void) self;
+ (void) regs;
}
/**
* Generate the prologue.
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
* @return The register which shall be used as a stack frame base.
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
ppc32_abi_env *env = (ppc32_abi_env *) self;
be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
+ (void) mem;
+ (void) reg_map;
+ (void) stack_bias;
isleaf = flags.bits.irg_is_leaf;
- if(flags.bits.try_omit_fp)
+ if (flags.bits.try_omit_fp)
return &ppc32_gp_regs[REG_R1];
else
return &ppc32_gp_regs[REG_R31];
*/
static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
+ (void) self;
+ (void) bl;
+ (void) mem;
+ (void) reg_map;
}
static const be_abi_callbacks_t ppc32_abi_callbacks = {
/* fill register allocator interface */
-static const arch_irn_ops_if_t ppc32_irn_ops_if = {
+static const arch_irn_ops_t ppc32_irn_ops = {
ppc32_get_irn_reg_req,
ppc32_set_irn_reg,
ppc32_get_irn_reg,
NULL, /* perform_memory_operand */
};
-ppc32_irn_ops_t ppc32_irn_ops = {
- &ppc32_irn_ops_if,
- NULL
-};
-
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
* Called immediatly before emit phase.
*/
static void ppc32_finish_irg(void *self) {
+ (void) self;
/* TODO: - fix offsets for nodes accessing stack
- ...
*/
* These are some hooks which must be filled but are probably not needed.
*/
static void ppc32_before_sched(void *self) {
+ (void) self;
/* Some stuff you need to do after scheduling but before register allocation */
}
store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
}
- else assert(0 && "Spill for register class not supported yet!");
+ else panic("Spill for register class not supported yet!");
set_ppc32_frame_entity(store, be_get_frame_entity(node));
{
load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
- else assert(0 && "Reload for register class not supported yet!");
+ else panic("Reload for register class not supported yet!");
set_ppc32_frame_entity(load, be_get_frame_entity(node));
static const arch_code_generator_if_t ppc32_code_gen_if = {
ppc32_cg_init,
+ NULL, /* get_pic_base */
ppc32_before_abi,
ppc32_prepare_graph,
NULL, /* spill */
* Initializes the code generator.
*/
static void *ppc32_cg_init(be_irg_t *birg) {
- ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
+ ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env;
ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
cg->impl = &ppc32_code_gen_if;
FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
cur_reg_set = cg->reg_set;
- ppc32_irn_ops.cg = cg;
return (arch_code_generator_t *)cg;
}
&ppc32_gp_regs[REG_R1], /* stack pointer */
&ppc32_gp_regs[REG_R31], /* base pointer */
-1, /* stack is decreasing */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
},
- { NULL, }, /* emitter environment */
NULL /* symbol set */
};
if (is_SymConst(node)) {
ir_entity *ent = get_SymConst_entity(node);
- mark_entity_visited(ent);
+ set_entity_backend_marked(ent, 1);
if (! is_direct_entity(ent))
pset_insert_ptr(symbol_set, ent);
}
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *ppc32_init(FILE *file_handle) {
+static arch_env_t *ppc32_init(FILE *file_handle) {
static int inited = 0;
ppc32_isa_t *isa;
int i;
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ppc32_isa_template, sizeof(*isa));
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
- ppc32_register_init(isa);
- ppc32_create_opcodes();
+ ppc32_register_init();
+ ppc32_create_opcodes(&ppc32_irn_ops);
inited = 1;
*/
inc_master_type_visited();
- return isa;
+ return &isa->arch_env;
}
static void ppc32_dump_indirect_symbols(ppc32_isa_t *isa) {
foreach_pset(isa->symbol_set, ent) {
const char *ld_name = get_entity_ld_name(ent);
- be_emit_irprintf(&isa->emit, ".non_lazy_symbol_pointer\n%s:\n\t.indirect_symbol _%s\n\t.long 0\n\n", ld_name, ld_name);
- be_emit_write_line(&isa->emit);
+ be_emit_irprintf(".non_lazy_symbol_pointer\n%s:\n\t.indirect_symbol _%s\n\t.long 0\n\n", ld_name, ld_name);
+ be_emit_write_line();
}
}
static void ppc32_done(void *self) {
ppc32_isa_t *isa = self;
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
- be_gas_emit_switch_section(&isa->emit, GAS_SECTION_DATA);
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
+ be_gas_emit_switch_section(GAS_SECTION_DATA);
ppc32_dump_indirect_symbols(isa);
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
del_pset(isa->symbol_set);
free(self);
-static int ppc32_get_n_reg_class(const void *self) {
+static unsigned ppc32_get_n_reg_class(const void *self) {
+ (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
+static const arch_register_class_t *ppc32_get_reg_class(const void *self,
+ unsigned i) {
+ (void) self;
+ assert(i < N_CLASSES && "Invalid ppc register class requested.");
return &ppc32_reg_classes[i];
}
* @return A register class which can hold values of the given mode.
*/
const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+ (void) self;
if (mode_is_float(mode))
return &ppc32_reg_classes[CLASS_ppc32_fp];
else
const arch_register_t *reg;
be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
+ (void) self;
if(get_type_visibility(method_type)!=visibility_external_allocated)
call_flags.bits.call_has_imm = 1;
for (i = 0; i < n; i++) {
tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
if(is_atomic_type(tp))
{
- mode = get_type_mode(tp);
-
if(mode_is_float(mode))
{
if(fpregi <= REG_F13)
be_abi_call_param_reg(abi, i, reg);
else
{
- be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
+ be_abi_call_param_stack(abi, i, mode, 4, stackoffs - lastoffs, 0);
lastoffs = stackoffs+stackparamsize;
}
stackoffs += stackparamsize;
}
else
{
- be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
+ be_abi_call_param_stack(abi, i, mode, 4, stackoffs - lastoffs, 0);
stackoffs += (get_type_size_bytes(tp)+3) & -4;
lastoffs = stackoffs;
}
}
}
-static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- return &ppc32_irn_ops;
-}
-
-const arch_irn_handler_t ppc32_irn_handler = {
- ppc32_get_irn_ops
-};
-
-const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
- return &ppc32_irn_handler;
-}
-
int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ppc32_irn(irn);
+ (void) block_env;
+ if(!is_ppc32_irn(irn))
+ return -1;
+
+ return 1;
}
/**
* Initializes the code generator interface.
*/
static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
+ (void) self;
return &ppc32_code_gen_if;
}
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
- memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
+ (void) self;
+ (void) selector;
+ ppc32_sched_selector = trivial_selector;
ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
return &ppc32_sched_selector;
}
static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
+ (void) self;
return NULL;
}
*/
static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
ir_mode *mode = arch_register_class_mode(cls);
+ (void) self;
+
return get_mode_size_bytes(mode);
}
static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ (void) self;
+ (void) irn;
/* TODO */
assert(0);
return NULL;
}
static const be_machine_t *ppc32_get_machine(const void *self) {
+ (void) self;
/* TODO */
assert(0);
return NULL;
* Return irp irgs in the desired order.
*/
static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) {
+ (void) self;
+ (void) irg_list;
return NULL;
}
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *ppc32_get_libfirm_params(void) {
- static arch_dep_params_t ad = {
- 1, /* allow subs */
- 0, /* Muls are fast enough on ARM */
- 31, /* shift would be ok */
- 0, /* SMUL is needed, only in Arch M*/
- 0, /* UMUL is needed, only in Arch M */
- 32, /* SMUL & UMUL available for 32 bit */
- };
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ 0, /* no immediate floating point mode. */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ NULL, /* no if conversion settings */
+ NULL /* no immediate fp mode */
};
- p.dep_param = &ad;
return &p;
}
+static asm_constraint_flags_t ppc32_parse_asm_constraint(const void *self, const char **c)
+{
+ /* no asm support yet */
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int ppc32_is_valid_clobber(const void *self, const char *clobber)
+{
+ /* no asm support yet */
+ (void) self;
+ (void) clobber;
+ return 0;
+}
+
const arch_isa_if_t ppc32_isa_if = {
ppc32_init,
ppc32_done,
ppc32_get_reg_class,
ppc32_get_reg_class_for_mode,
ppc32_get_call_abi,
- ppc32_get_irn_handler,
ppc32_get_code_generator_if,
ppc32_get_list_sched_selector,
ppc32_get_ilp_sched_selector,
ppc32_get_allowed_execution_units,
ppc32_get_machine,
ppc32_get_irg_list,
+ ppc32_parse_asm_constraint,
+ ppc32_is_valid_clobber
};
void be_init_arch_ppc32(void)
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