const ppc32_register_req_t *irn_req;
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
+ FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
if (is_Block(irn) || mode == mode_X || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
if(be_is_Spill(node))
{
- ir_node *store, *proj;
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_node *store, *proj;
+ dbg_info *dbg = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
{
ir_node *load, *proj;
const arch_register_t *reg;
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbg = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_mode *mode = get_irn_mode(node);
const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
* @param env the debug module
*/
void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
- ppc32_code_gen_t *cg = env;
- if(get_irn_op(node)==op_SymConst)
+ if(get_irn_op(node) == op_SymConst)
{
entity *ent = get_SymConst_entity(node);
if(!is_direct_entity(ent))
cg->impl = &ppc32_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.ppc.cg");
cg->out = F;
cg->arch_env = birg->main_env->arch_env;
cg->birg = birg;
cg->area = NULL;
cg->start_succ_block = NULL;
cg->blk_sched = NULL;
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
isa->num_codegens++;
int fpregi = REG_F1;
const arch_register_t *reg;
- be_abi_call_flags_t call_flags = { 0, 0, 1, 0, 0, 0, 1 };
+ be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
if(get_type_visibility(method_type)!=visibility_external_allocated)
call_flags.bits.call_has_imm = 1;
return &ppc32_sched_selector;
}
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+ ir_mode *mode = arch_register_class_mode(cls);
+ return get_mode_size_bytes(mode);
+}
+
#ifdef WITH_LIBCORE
static void ppc32_register_options(lc_opt_entry_t *ent)
{
ppc32_get_irn_handler,
ppc32_get_code_generator_if,
ppc32_get_list_sched_selector,
+ ppc32_get_reg_class_alignment
};