if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
{
- store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
- get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+ store = new_bd_ppc32_Stw(dbg, block,
+ get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
}
else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
{
- store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
- get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+ store = new_bd_ppc32_Stfd(dbg, block,
+ get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
}
else panic("Spill for register class not supported yet!");
if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
{
- load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
+ load = new_bd_ppc32_Lwz(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
{
- load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
+ load = new_bd_ppc32_Lfd(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1));
}
else panic("Reload for register class not supported yet!");
static backend_params p = {
1, /* need dword lowering */
0, /* don't support inline assembler yet */
- 0, /* no immediate floating point mode. */
- NULL, /* no additional opcodes */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
NULL, /* no if conversion settings */
- NULL /* no immediate fp mode */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL /* no trampoline support: no trampoline builder */
};
return &p;