Fix comments.

[libfirm] / ir / be / ppc32 / bearch_ppc32.c

diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c
index 07a43b7..0bd4af4 100644 (file)
--- a/ir/be/ppc32/bearch_ppc32.c
+++ b/ir/be/ppc32/bearch_ppc32.c
@@ -137,59 +137,6 @@ static const arch_register_req_t *ppc32_get_irn_reg_req(const ir_node *irn,
        return arch_no_register_req;
 }
 
-static void ppc32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
-{
-       int pos = 0;
-
-       if (is_Proj(irn)) {
-
-               if (get_irn_mode(irn) == mode_X) {
-                       return;
-               }
-
-               pos = ppc32_translate_proj_pos(irn);
-               irn = skip_Proj(irn);
-       }
-
-       if (is_ppc32_irn(irn)) {
-               const arch_register_t **slots;
-
-               slots      = get_ppc32_slots(irn);
-               slots[pos] = reg;
-       }
-       else {
-               /* here we set the registers for the Phi nodes */
-               ppc32_set_firm_reg(irn, reg, cur_reg_set);
-       }
-}
-
-static const arch_register_t *ppc32_get_irn_reg(const ir_node *irn)
-{
-       int pos = 0;
-       const arch_register_t *reg = NULL;
-
-       if (is_Proj(irn)) {
-
-               if (get_irn_mode(irn) == mode_X) {
-                       return NULL;
-               }
-
-               pos = ppc32_translate_proj_pos(irn);
-               irn = skip_Proj_const(irn);
-       }
-
-       if (is_ppc32_irn(irn)) {
-               const arch_register_t **slots;
-               slots = get_ppc32_slots(irn);
-               reg   = slots[pos];
-       }
-       else {
-               reg = ppc32_get_firm_reg(irn, cur_reg_set);
-       }
-
-       return reg;
-}
-
 static arch_irn_class_t ppc32_classify(const ir_node *irn)
 {
        irn = skip_Proj_const(irn);
@@ -201,20 +148,6 @@ static arch_irn_class_t ppc32_classify(const ir_node *irn)
        return 0;
 }
 
-static arch_irn_flags_t ppc32_get_flags(const ir_node *irn)
-{
-       irn = skip_Proj_const(irn);
-
-       if (is_ppc32_irn(irn)) {
-               return get_ppc32_flags(irn);
-       }
-       else if (is_Unknown(irn)) {
-               return arch_irn_flags_ignore;
-       }
-
-       return 0;
-}
-
 static ir_entity *ppc32_get_frame_entity(const ir_node *irn)
 {
        if(!is_ppc32_irn(irn)) return NULL;
@@ -304,17 +237,6 @@ static ir_type *ppc32_abi_get_between_type(void *self)
        return between_type;
 }
 
-/**
- * Put all registers which are saved by the prologue/epilogue in a set.
- * @param self The callback object.
- * @param regs A set.
- */
-static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
-{
-       (void) self;
-       (void) regs;
-}
-
 /**
  * Generate the prologue.
  * @param self       The callback object.
@@ -362,7 +284,6 @@ static const be_abi_callbacks_t ppc32_abi_callbacks = {
        ppc32_abi_init,
        ppc32_abi_done,
        ppc32_abi_get_between_type,
-       ppc32_abi_regs_saved_by_me,
        ppc32_abi_prologue,
        ppc32_abi_epilogue,
 };
@@ -371,10 +292,7 @@ static const be_abi_callbacks_t ppc32_abi_callbacks = {
 
 static const arch_irn_ops_t ppc32_irn_ops = {
        ppc32_get_irn_reg_req,
-       ppc32_set_irn_reg,
-       ppc32_get_irn_reg,
        ppc32_classify,
-       ppc32_get_flags,
        ppc32_get_frame_entity,
        ppc32_set_frame_entity,
        ppc32_set_stack_bias,
@@ -457,14 +375,6 @@ static void ppc32_finish_irg(void *self) {
 }
 
 
-/**
- * These are some hooks which must be filled but are probably not needed.
- */
-static void ppc32_before_sched(void *self) {
-       (void) self;
-       /* Some stuff you need to do after scheduling but before register allocation */
-}
-
 /**
  * Called before the register allocator.
  * Calculate a block schedule here. We need it for the x87
@@ -489,13 +399,13 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 
                if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
                {
-                       store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+                       store = new_bd_ppc32_Stw(dbg, block,
+                               get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
                }
                else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
                {
-                       store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
+                       store = new_bd_ppc32_Stfd(dbg, block,
+                               get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem());
                }
                else panic("Spill for register class not supported yet!");
 
@@ -525,11 +435,11 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 
                if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
                {
-                       load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block,   get_irn_n(node, 0), get_irn_n(node, 1));
+                       load = new_bd_ppc32_Lwz(dbg, block,     get_irn_n(node, 0), get_irn_n(node, 1));
                }
                else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
                {
-                       load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block,   get_irn_n(node, 0), get_irn_n(node, 1));
+                       load = new_bd_ppc32_Lfd(dbg, block,     get_irn_n(node, 0), get_irn_n(node, 1));
                }
                else panic("Reload for register class not supported yet!");
 
@@ -589,7 +499,6 @@ static const arch_code_generator_if_t ppc32_code_gen_if = {
        ppc32_before_abi,
        ppc32_prepare_graph,
        NULL,                 /* spill */
-       ppc32_before_sched,   /* before scheduling hook */
        ppc32_before_ra,      /* before register allocation hook */
        ppc32_after_ra,
        ppc32_finish_irg,
@@ -911,13 +820,13 @@ static const backend_params *ppc32_get_libfirm_params(void) {
        static backend_params p = {
                1,     /* need dword lowering */
                0,     /* don't support inline assembler yet */
-               0,     /* no immediate floating point mode. */
-               NULL,  /* no additional opcodes */
                NULL,  /* will be set later */
                NULL,  /* but yet no creator function */
                NULL,  /* context for create_intrinsic_fkt */
                NULL,  /* no if conversion settings */
-               NULL   /* no immediate fp mode */
+               0,     /* no trampoline support: size 0 */
+               0,     /* no trampoline support: align 0 */
+               NULL   /* no trampoline support: no trampoline builder */
        };
 
        return &p;
@@ -942,6 +851,7 @@ static int ppc32_is_valid_clobber(const void *self, const char *clobber)
 const arch_isa_if_t ppc32_isa_if = {
        ppc32_init,
        ppc32_done,
+       NULL,             /* handle intrinsics */
        ppc32_get_n_reg_class,
        ppc32_get_reg_class,
        ppc32_get_reg_class_for_mode,