# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
$arch = "mips";
-
-# this strings mark the beginning and the end of a comment in emit
-$comment_string = "#";
-$comment_string_end = "";
-
-# The node description is done as a perl hash initializer with the
-# following structure:
-#
-# %nodes = (
-#
-# <op-name> => {
-# op_flags => "N|L|C|X|I|F|Y|H|c|K",
-# "arity" => "0|1|2|3 ... |variable|dynamic|any",
-# "state" => "floats|pinned|mem_pinned|exc_pinned",
-# "args" => [
-# { "type" => "type 1", "name" => "name 1" },
-# { "type" => "type 2", "name" => "name 2" },
-# ...
-# ],
-# "comment" => "any comment for constructor",
-# reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
-# "cmp_attr" => "c source code for comparing node attributes",
-# emit => "emit code with templates",
-# "rd_constructor" => "c source code which constructs an ir_node"
-# },
-#
-# ... # (all nodes you need to describe)
-#
-# ); # close the %nodes initializer
-
-# op_flags: flags for the operation, OPTIONAL (default is "N")
-# the op_flags correspond to the firm irop_flags:
-# N irop_flag_none
-# L irop_flag_labeled
-# C irop_flag_commutative
-# X irop_flag_cfopcode
-# I irop_flag_ip_cfopcode
-# F irop_flag_fragile
-# Y irop_flag_forking
-# H irop_flag_highlevel
-# c irop_flag_constlike
-# K irop_flag_keep
-#
-# R rematerializeable
-# N not spillable
-# I ignore for register allocation
-#
-# state: state of the operation, OPTIONAL (default is "floats")
-#
-# arity: arity of the operation, MUST NOT BE OMITTED
-#
-# args: the OPTIONAL arguments of the node constructor (debug, irg and block
-# are always the first 3 arguments and are always autmatically
-# created)
-# If this key is missing the following arguments will be created:
-# for i = 1 .. arity: ir_node *op_i
-# ir_mode *mode
-#
-# outs: if a node defines more than one output, the names of the projections
-# nodes having outs having automatically the mode mode_T
-#
-# comment: OPTIONAL comment for the node constructor
-#
-# rd_constructor: for every operation there will be a
-# new_rd_<arch>_<op-name> function with the arguments from above
-# which creates the ir_node corresponding to the defined operation
-# you can either put the complete source code of this function here
-#
-# This key is OPTIONAL. If omitted, the following constructor will
-# be created:
-# if (!op_<arch>_<op-name>) assert(0);
-# for i = 1 to arity
-# set in[i] = op_i
-# done
-# res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
-# return res
-#
-# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
+$new_emit_syntax = 1;
# register types:
# 0 - no special type
# NOTE: Last entry of each class is the largest Firm-Mode a register can hold\
%reg_classes = (
"gp" => [
- { name => "zero", type => 4+2 }, # always zero
+ { name => "zero", type => 4 }, # always zero
{ name => "at", type => 4 }, # reserved for assembler
{ name => "v0", realname => "2", type => 1 }, # first return value
{ name => "v1", realname => "3", type => 1 }, # second return value
{ name => "sp", type => 4 }, # stack pointer
{ name => "fp", type => 4 }, # frame pointer
{ name => "ra", type => 2+1 }, # return address
+ { name => "gp_NOREG", realname => "!NOREG_INVALID!", type => 4 | 8 | 16 }, #dummy register for immediate nodes
{ mode => "mode_Iu" }
],
); # %reg_classes
+%emit_templates = (
+ S0 => "${arch}_emit_source_register(node, 0);",
+ S1 => "${arch}_emit_source_register(node, 1);",
+ S2 => "${arch}_emit_source_register(node, 2);",
+ SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
+ D0 => "${arch}_emit_dest_register(node, 0);",
+ D1 => "${arch}_emit_dest_register(node, 1);",
+ D2 => "${arch}_emit_dest_register(node, 2);",
+ A0 => "${arch}_emit_load_store_address(node, 0);",
+ I => "${arch}_emit_immediate_suffix(node, 1);",
+ C => "${arch}_emit_immediate(node);",
+ JumpTarget => "${arch}_emit_jump_target(node);",
+ JumpTarget1 => "${arch}_emit_jump_target_proj(node, 1);",
+ JumpOrFallthrough => "${arch}_emit_jump_or_fallthrough(node, 0);",
+);
+
+$default_attr_type = "mips_attr_t";
+$default_copy_attr = "mips_copy_attr";
+
+$mode_gp = "mode_Iu";
+
+%init_attr = (
+ mips_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
+
+ mips_immediate_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_mips_immediate_attributes(res, imm_type, entity, val);",
+
+ mips_load_store_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_mips_load_store_attributes(res, entity, offset);",
+);
+
+%compare_attr = (
+ mips_attr_t => "mips_compare_nodes_attr",
+ mips_immediate_attr_t => "mips_compare_immediate_attr",
+ mips_load_store_attr_t => "mips_compare_load_store_attr",
+);
+
#--------------------------------------------------#
# _ #
# (_) #
%nodes = (
+Immediate => {
+ state => "pinned",
+ op_flags => "c",
+ reg_req => { out => [ "gp_NOREG:I" ] },
+ attr => "mips_immediate_type_t imm_type, ir_entity *entity, long val",
+ attr_type => "mips_immediate_attr_t",
+ mode => $mode_gp,
+},
+
#-----------------------------------------------------------------#
# _ _ _ #
# (_) | | | | #
# commutative operations
addu => {
- op_flags => "C",
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. addu %D1, %S1, %S2',
- mode => "mode_Iu",
-},
-
-addiu => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. addiu %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. add%I%.u %D0, %S0, %SI1',
+ mode => $mode_gp,
},
and => {
- op_flags => "C",
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. and %D1, %S1, %S2',
- mode => "mode_Iu",
-},
-
-andi => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. andi %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. and%I %D0, %S0, %SI1',
+ mode => $mode_gp,
},
div => {
- reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
- emit => '. div %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] },
+ ins => [ "left", "right" ],
+ outs => [ "lohi", "M" ],
+ emit => '. div %S0, %S1',
mode => "mode_M",
},
divu => {
- reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
- emit => '. divu %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] },
+ ins => [ "left", "right" ],
+ outs => [ "lohi", "M" ],
+ emit => '. divu %S0, %S1',
mode => "mode_M",
},
mult => {
- op_flags => "C",
reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
- emit => '. mult %S1, %S2',
+ ins => [ "left", "right" ],
+ emit => '. mult %S0, %S1',
mode => "mode_M"
},
multu => {
- op_flags => "C",
reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
- emit => '. multu %S1, %S2',
+ ins => [ "left", "right" ],
+ emit => '. multu %S0, %S1',
mode => "mode_M",
},
nor => {
- op_flags => "C",
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. nor %D1, %S1, %S2',
- mode => "mode_Iu"
-},
-
-not => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. nor %D1, %S1, $zero',
- mode => "mode_Iu"
+ emit => '. nor%I %D0, %S0, %SI1',
+ mode => $mode_gp
},
or => {
- op_flags => "C",
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. or %D1, %S1, %S2',
- mode => "mode_Iu"
+ ins => [ "left", "right" ],
+ emit => '. or%I %D0, %S0, %SI1',
+ mode => $mode_gp
},
-ori => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. ori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu"
-},
-
-sl => {
+sll => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sal %D1, %S1, %S2
- } else {
-2. sll %D1, %S1, %S2
- }
-',
- mode => "mode_Iu",
-},
-
-sli => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sal %D1, %S1, %C
- } else {
-2. sll %D1, %S1, %C
- }
-',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. sll %D0, %S0, %SI1',
+ mode => $mode_gp,
},
sra => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. sra %D1, %S1, %S2',
- mode => "mode_Iu"
+ ins => [ "left", "right" ],
+ emit => '. sra %D0, %S0, %SI1',
+ mode => $mode_gp
},
-srai => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. sra %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
-},
-
-sr => {
+srl => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sra %D1, %S1, %S2
- } else {
-2. srl %D1, %S1, %S2
- }
-',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. srl %D0, %S0, %SI1',
+ mode => $mode_gp,
},
-sri => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sra %D1, %S1, %C
- } else {
-2. srl %D1, %S1, %C
- }
-',
- mode => "mode_Iu"
-},
-
-srlv => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. srlv %D1, %S1, %S2',
- mode => "mode_Iu"
-},
-
-sllv => {
+subu => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. sllv %D1, %S1, %S2',
- mode => "mode_Iu"
-},
-
-sub => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. subu %D1, %S1, %S2',
- mode => "mode_Iu"
-},
-
-subuzero => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. subu %D1, $zero, %S1',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. subu %D0, %S0, %S1',
+ mode => $mode_gp
},
xor => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. xor %D1, %S1, %S2',
- mode => "mode_Iu",
+ ins => [ "left", "right" ],
+ emit => '. xor%I %D0, %S0, %SI1',
+ mode => $mode_gp,
},
-xori => {
+seb => {
+ op_flags => "R",
reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. xori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
+ ins => [ "val" ],
+ emit => '.seb %D0, %S0',
+ mode => $mode_gp,
},
-# ____ _ _
-# / ___|___ _ __ ___| |_ __ _ _ __ | |_ ___
-# | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
-# | |__| (_) | | | \__ \ || (_| | | | | |_\__ \
-# \____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
-#
-
-# load upper imediate
-lui => {
- op_flags => "c",
- reg_req => { out => [ "gp" ] },
- emit => '. lui %D1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
-},
-
-# load lower immediate
-lli => {
- op_flags => "c",
+seh => {
+ op_flags => "R",
reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. ori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
+ ins => [ "val" ],
+ emit => '.seh %D0, %S0',
+ mode => $mode_gp,
},
-la => {
+lui => {
op_flags => "c",
+ irn_flags => "R",
reg_req => { out => [ "gp" ] },
- emit => '. la %D1, %C',
- cmp_attr => 'return attr_a->symconst_id != attr_b->symconst_id;',
- mode => "mode_Iu",
+ emit => '.lui %D0, %C',
+ attr_type => "mips_immediate_attr_t",
+ attr => "mips_immediate_type_t imm_type, ir_entity *entity, long val",
+ mode => $mode_gp,
},
mflo => {
+ irn_flags => "R",
reg_req => { in => [ "none" ], out => [ "gp" ] },
- emit => '. mflo %D1',
- mode => "mode_Iu"
+ ins => [ "lohi" ],
+ emit => '. mflo %D0',
+ mode => $mode_gp
},
mfhi => {
+ irn_flags => "R",
reg_req => { in => [ "none" ], out => [ "gp" ] },
- emit => '. mfhi %D1',
- mode => "mode_Iu"
+ ins => [ "lohi" ],
+ emit => '. mfhi %D0',
+ mode => $mode_gp
},
zero => {
- reg_req => { out => [ "zero" ] },
+ state => "pinned",
+ op_flags => "c",
+ reg_req => { out => [ "zero:I" ] },
emit => '',
- mode => "mode_Iu"
+ mode => $mode_gp
},
#
#
slt => {
+ op_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. slt %D1, %S1, %S2
- }
- else {
-2. sltu %D1, %S1, %S2
- }
-',
- mode => "mode_Iu",
-},
-
-slti => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. slti %D1, %S1, %C
- }
- else {
-2. sltiu %D1, %S1, %C
- }
-',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
- mode => "mode_Iu",
+ emit => '. slt%I %D0, %S0, %SI1',
+ mode => $mode_gp,
},
-beq => {
- op_flags => "X|Y",
- # TxT -> TxX
- reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
+sltu => {
+ op_flags => "R",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. slt%I%.u %D0, %S0, %SI1',
+ mode => $mode_gp,
+},
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbeq %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock));
-'
+beq => {
+ op_flags => "X|Y",
+ reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] },
+ outs => [ "false", "true" ],
+ emit => '. beq %S0, %S1, %JumpTarget1
+ . %JumpOrFallthrough'
},
bne => {
- op_flags => "X|Y",
- # TxT -> TxX
- reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbne %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock));
-'
+ op_flags => "X|Y",
+ reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] },
+ outs => [ "false", "true" ],
+ emit => '. bne %S0, %S1, %JumpTarget1
+ . %JumpOrFallthrough'
},
bgtz => {
- op_flags => "X|Y",
- # TxT -> TxX
- reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbgtz %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock));
-'
+ op_flags => "X|Y",
+ reg_req => { in => [ "gp" ], out => [ "none", "none" ] },
+ outs => [ "false", "true" ],
+ emit => '. bgtz %S0, %JumpTarget1
+ . %JumpOrFallthrough'
},
blez => {
- op_flags => "X|Y",
- # TxT -> TxX
- reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tblez %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock));
-'
-},
-
-j => {
- op_flags => "X",
- reg_req => { in => [ "gp" ] },
- emit => '. j %S1',
+ op_flags => "X|Y",
+ reg_req => { in => [ "gp" ], out => [ "none", "none" ] },
+ outs => [ "false", "true" ],
+ emit => '. blez %S0, %JumpTarget1
+ . %JumpOrFallthrough'
},
b => {
op_flags => "X",
- # -> X
- reg_req => { in => [ ], out => [ "none" ] },
- emit => '
- ir_node *jumpblock = get_irn_link(n);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tb BLOCK_%d\t\t\t# mips_b\n", get_irn_node_nr(jumpblock));
-'
+ reg_req => { in => [ ], out => [ "none" ] },
+ emit => '. b %JumpTarget',
+ mode => 'mode_X'
},
-fallthrough => {
+jr => {
op_flags => "X",
- # -> X
- reg_req => { in => [ ], out => [ "none" ] },
- emit => '. # fallthrough'
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
+ emit => '. jr %S0',
+ mode => 'mode_X'
},
SwitchJump => {
op_flags => "X",
- # -> X,X,...
- reg_req => { in => [ "gp" ], out => [ "none" ] },
- emit => '. j %S1'
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
+ emit => '. jr %S0'
},
-# _ _
-# | | ___ __ _ __| |
-# | | / _ \ / _` |/ _` |
-# | |__| (_) | (_| | (_| |
-# |_____\___/ \__,_|\__,_|
-#
-
-load_r => {
- reg_req => { in => [ "none", "gp" ], out => [ "none", "none", "gp" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
- ir_mode *mode;
-
- mode = attr->modes.load_store_mode;
-
- switch (get_mode_size_bits(mode)) {
- case 8:
- if (mode_is_signed(mode)) {
-3. lb %D3, %C(%S2)
- } else {
-3. lbu %D3, %C(%S2)
- }
- break;
- case 16:
- if (mode_is_signed(mode)) {
-3. lh %D3, %C(%S2)
- } else {
-3. lhu %D3, %C(%S2)
- }
- break;
- case 32:
-2. lw %D3, %C(%S2)
- break;
- default:
- assert(! "Only 8, 16 and 32 bit loads supported");
- break;
- }
-',
- cmp_attr => 'return attr_a->tv != attr_b->tv || attr_a->stack_entity != attr_b->stack_entity;',
-},
-
-
# _ _ ______ _
# | | ___ __ _ __| | / / ___|| |_ ___ _ __ ___
# | | / _ \ / _` |/ _` | / /\___ \| __/ _ \| '__/ _ \
# |_____\___/ \__,_|\__,_/_/ |____/ \__\___/|_| \___|
#
-store_r => {
- reg_req => { in => [ "none", "gp", "gp" ], out => [ "none", "none" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
- ir_mode* mode;
-
- mode = attr->modes.load_store_mode;
-
- switch (get_mode_size_bits(mode)) {
- case 8:
- if (mode_is_signed(mode))
-2. sb %S3, %C(%S2)
- break;
- case 16:
- if (mode_is_signed(mode))
-2. sh %S3, %C(%S2)
- break;
- case 32:
-2. sw %S3, %C(%S2)
- break;
- default:
- assert(! "Only 8, 16 and 32 bit stores supported");
- break;
- }
-',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
-},
-
-store_i => {
- reg_req => { in => [ "none", "none", "gp" ], out => [ "none", "none" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
- ir_mode *mode;
-
- mode = attr->modes.load_store_mode;
-
- switch (get_mode_size_bits(mode)) {
- case 8:
-2. sb %S3, %C
- break;
- case 16:
-2. sh %S3, %C
- break;
- case 32:
-2. sw %S3, %C
- break;
- default:
- assert(! "Only 8, 16 and 32 bit stores supported");
- break;
- }
-',
- cmp_attr => 'return attr_a->stack_entity != attr_b->stack_entity;',
-},
-
-move => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. move %D1, %S1',
- mode => "mode_Iu"
-},
-
-#
-# Conversion
-#
-
-reinterpret_conv => {
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
- emit => '. # reinterpret %S1 -> %D1',
- mode => "mode_Iu"
+lw => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
+ ins => [ "ptr", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. lw %D0, %A0',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+lh => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
+ ins => [ "ptr", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. lh %D0, %A0',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+lhu => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
+ ins => [ "ptr", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. lhu %D0, %A0',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+lb => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
+ ins => [ "ptr", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. lb %D0, %A0',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+lbu => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
+ ins => [ "ptr", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. lbu %D0, %A0',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+sw => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "ptr", "val", "mem" ],
+ emit => '. sw %S1, %A0',
+ mode => 'mode_M',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+sh => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "ptr", "val", "mem" ],
+ emit => '. sh %S1, %A0',
+ mode => 'mode_M',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
+},
+
+sb => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "ptr", "val", "mem" ],
+ emit => '. sb %S1, %A0',
+ mode => 'mode_M',
+ attr_type => "mips_load_store_attr_t",
+ attr => "ir_entity *entity, long offset",
},
#
projects / libfirm / blobdiff