# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
$arch = "mips";
-
-# this strings mark the beginning and the end of a comment in emit
-$comment_string = "#";
-$comment_string_end = "";
+$new_emit_syntax = 1;
# The node description is done as a perl hash initializer with the
# following structure:
"gp" => [
{ name => "zero", type => 4+2 }, # always zero
{ name => "at", type => 4 }, # reserved for assembler
- { name => "v0", type => 1 }, # first return value
- { name => "v1", type => 1 }, # second return value
- { name => "a0", type => 1 }, # first argument
- { name => "a1", type => 1 }, # second argument
- { name => "a2", type => 1 }, # third argument
- { name => "a3", type => 1 }, # fourth argument
- { name => "t0", type => 1 },
- { name => "t1", type => 1 },
- { name => "t2", type => 1 },
- { name => "t3", type => 1 },
- { name => "t4", type => 1 },
- { name => "t5", type => 1 },
- { name => "t6", type => 1 },
- { name => "t7", type => 1 },
- { name => "s0", type => 2 },
- { name => "s1", type => 2 },
- { name => "s2", type => 2 },
- { name => "s3", type => 2 },
- { name => "s4", type => 2 },
- { name => "s5", type => 2 },
- { name => "s6", type => 2 },
- { name => "s7", type => 2 },
- { name => "t8", type => 1 },
- { name => "t9", type => 1 },
- { name => "k0", type => 4 }, # reserved for OS
- { name => "k1", type => 4 }, # reserved for OS
+ { name => "v0", realname => "2", type => 1 }, # first return value
+ { name => "v1", realname => "3", type => 1 }, # second return value
+ { name => "a0", realname => "4", type => 1 }, # first argument
+ { name => "a1", realname => "5", type => 1 }, # second argument
+ { name => "a2", realname => "6", type => 1 }, # third argument
+ { name => "a3", realname => "7", type => 1 }, # fourth argument
+ { name => "t0", realname => "8", type => 1 },
+ { name => "t1", realname => "9", type => 1 },
+ { name => "t2", realname => "10", type => 1 },
+ { name => "t3", realname => "11", type => 1 },
+ { name => "t4", realname => "12", type => 1 },
+ { name => "t5", realname => "13", type => 1 },
+ { name => "t6", realname => "14", type => 1 },
+ { name => "t7", realname => "15", type => 1 },
+ { name => "s0", realname => "16", type => 2 },
+ { name => "s1", realname => "17", type => 2 },
+ { name => "s2", realname => "18", type => 2 },
+ { name => "s3", realname => "19", type => 2 },
+ { name => "s4", realname => "20", type => 2 },
+ { name => "s5", realname => "21", type => 2 },
+ { name => "s6", realname => "22", type => 2 },
+ { name => "s7", realname => "23", type => 2 },
+ { name => "t8", realname => "24", type => 1 },
+ { name => "t9", realname => "25", type => 1 },
+ { name => "kt0", type => 4 }, # reserved for OS
+ { name => "kt1", type => 4 }, # reserved for OS
{ name => "gp", type => 4 }, # general purpose
- { name => "sp", type => 4+2 }, # stack pointer
- { name => "fp", type => 4+2 }, # frame pointer
- { name => "ra", type => 2+1 }, # return address. This is also caller
- # save, because the jla instruction that
- # is used for calls modifies the ra
- # register. It is callee save too,
- # because at the last command of a
- # function (the ja $ra) it needs to have
- # it's old value.
- { mode => "mode_P" }
+ { name => "sp", type => 4 }, # stack pointer
+ { name => "fp", type => 4 }, # frame pointer
+ { name => "ra", type => 2+1 }, # return address
+ { mode => "mode_Iu" }
],
); # %reg_classes
+%emit_templates = (
+ S1 => "${arch}_emit_source_register(env, node, 0);",
+ S2 => "${arch}_emit_source_register(env, node, 1);",
+ S3 => "${arch}_emit_source_register(env, node, 2);",
+ D1 => "${arch}_emit_dest_register(env, node, 0);",
+ D2 => "${arch}_emit_dest_register(env, node, 1);",
+ D3 => "${arch}_emit_dest_register(env, node, 2);",
+ C => "${arch}_emit_immediate(env, node);",
+ JumpTarget => "${arch}_emit_jump_target(env, node);",
+ JumpTarget1 => "${arch}_emit_jump_target_proj(env, node, 1);",
+);
+
+
#--------------------------------------------------#
# _ #
# (_) #
# commutative operations
-add => {
- op_flags => "C",
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. addu %D1, %S1, %S2'
+addu => {
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. addu %D1, %S1, %S2',
+ mode => "mode_Iu",
},
-addi => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. addiu %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+addiu => {
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. addiu %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
and => {
- op_flags => "C",
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. and %D1, %S1, %S2',
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. and %D1, %S1, %S2',
+ mode => "mode_Iu",
},
andi => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. andi %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. andi %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
div => {
- reg_req => { in => [ "gp", "gp" ], out => [ "none", "none", "none", "none" ] },
- emit => '
- mips_attr_t *attr = get_mips_attr(n);
- if (attr->modes.original_mode->sign) {
-2. div %S1, %S2
- } else {
-2. divu %S1, %S2
- }
-',
+ reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
+ emit => '. div %S1, %S2',
+ mode => "mode_M",
+},
+
+divu => {
+ reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
+ emit => '. divu %S1, %S2',
+ mode => "mode_M",
},
mult => {
- op_flags => "C",
- reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. mult %S1, %S2
- }
- else {
-2. multu %S1, %S2
- }
-',
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
+ emit => '. mult %S1, %S2',
+ mode => "mode_M"
+},
+
+multu => {
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "none" ] },
+ emit => '. multu %S1, %S2',
+ mode => "mode_M",
},
nor => {
- op_flags => "C",
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. nor %D1, %S1, %S2'
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. nor %D1, %S1, %S2',
+ mode => "mode_Iu"
},
not => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. nor %D1, %S1, $zero'
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. nor %D1, %S1, $zero',
+ mode => "mode_Iu"
},
or => {
- op_flags => "C",
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. or %D1, %S1, %S2'
+ op_flags => "C",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. or %D1, %S1, %S2',
+ mode => "mode_Iu"
},
ori => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. ori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. ori %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu"
},
sl => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sal %D1, %S1, %S2
- }
- else {
-2. sll %D1, %S1, %S2
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '
+ if (mode_is_signed(get_irn_mode(node))) {
+ . sal %D1, %S1, %S2
+ } else {
+ . sll %D1, %S1, %S2
}
',
+ mode => "mode_Iu",
},
sli => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sal %D1, %S1, %C
- }
- else {
-2. sll %D1, %S1, %C
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '
+ if (mode_is_signed(get_irn_mode(node))) {
+ . sal %D1, %S1, %C
+ } else {
+ . sll %D1, %S1, %C
}
',
+ mode => "mode_Iu",
},
sra => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. sra %D1, %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. sra %D1, %S1, %S2',
+ mode => "mode_Iu"
},
srai => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. sra %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. sra %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
sr => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sra %D1, %S1, %S2
- }
- else {
-2. srl %D1, %S1, %S2
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '
+ if (mode_is_signed(get_irn_mode(node))) {
+ . sra %D1, %S1, %S2
+ } else {
+ . srl %D1, %S1, %S2
}
',
+ mode => "mode_Iu",
},
sri => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. sra %D1, %S1, %C
- }
- else {
-2. srl %D1, %S1, %C
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '
+ if (mode_is_signed(get_irn_mode(node))) {
+ . sra %D1, %S1, %C
+ } else {
+ . srl %D1, %S1, %C
}
',
+ mode => "mode_Iu"
},
srlv => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. srlv %D1, %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. srlv %D1, %S1, %S2',
+ mode => "mode_Iu"
},
sllv => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. sllv %D1, %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. sllv %D1, %S1, %S2',
+ mode => "mode_Iu"
},
sub => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. subu %D1, %S1, %S2',
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. subu %D1, %S1, %S2',
+ mode => "mode_Iu"
},
subuzero => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. subu %D1, $zero, %S1',
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. subu %D1, $zero, %S1',
+ mode => "mode_Iu",
},
xor => {
- reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
- emit => '. xor %D1, %S1, %S2'
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ emit => '. xor %D1, %S1, %S2',
+ mode => "mode_Iu",
},
xori => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. xori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. xori %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
# ____ _ _
# load upper imediate
lui => {
- op_flags => "c",
- reg_req => { out => [ "gp" ] },
- emit => '. lui %D1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ op_flags => "c",
+ reg_req => { out => [ "gp" ] },
+ emit => '. lui %D1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
# load lower immediate
lli => {
- op_flags => "c",
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. ori %D1, %S1, %C',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ op_flags => "c",
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. ori %D1, %S1, %C',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
la => {
- op_flags => "c",
- reg_req => { out => [ "gp" ] },
- emit => '. la %D1, %C',
- cmp_attr => 'return attr_a->symconst_id != attr_b->symconst_id;',
+ op_flags => "c",
+ reg_req => { out => [ "gp" ] },
+ emit => '. la %D1, %C',
+ cmp_attr => 'return attr_a->symconst_id != attr_b->symconst_id;',
+ mode => "mode_Iu",
},
mflo => {
- reg_req => { in => [ "none" ], out => [ "gp" ] },
- emit => '. mflo %D1'
+ reg_req => { in => [ "none" ], out => [ "gp" ] },
+ emit => '. mflo %D1',
+ mode => "mode_Iu"
},
mfhi => {
- reg_req => { in => [ "none" ], out => [ "gp" ] },
- emit => '. mfhi %D1'
+ reg_req => { in => [ "none" ], out => [ "gp" ] },
+ emit => '. mfhi %D1',
+ mode => "mode_Iu"
},
zero => {
- reg_req => { out => [ "zero" ] },
- emit => '',
+ reg_req => { out => [ "zero" ] },
+ emit => '',
+ mode => "mode_Iu"
},
#
slt => {
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. slt %D1, %S1, %S2
+ if (mode_is_signed(get_irn_mode(node))) {
+ . slt %D1, %S1, %S2
}
else {
-2. sltu %D1, %S1, %S2
+ . sltu %D1, %S1, %S2
}
',
+ mode => "mode_Iu",
},
slti => {
reg_req => { in => [ "gp" ], out => [ "gp" ] },
emit => '
- if (mode_is_signed(get_irn_mode(n))) {
-2. slti %D1, %S1, %C
+ if (mode_is_signed(get_irn_mode(node))) {
+ . slti %D1, %S1, %C
}
else {
-2. sltiu %D1, %S1, %C
+ . sltiu %D1, %S1, %C
}
',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ mode => "mode_Iu",
},
beq => {
op_flags => "X|Y",
# TxT -> TxX
reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbeq %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock));
-'
+ emit => '. beq %S1, %S2, %JumpTarget1'
},
bne => {
op_flags => "X|Y",
# TxT -> TxX
reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbne %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock));
-'
+ emit => '. bne %S1, %S2, %JumpTarget1'
},
bgtz => {
op_flags => "X|Y",
# TxT -> TxX
reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tbgtz %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock));
-'
+ emit => '. bgtz %S1, %JumpTarget1'
},
blez => {
op_flags => "X|Y",
# TxT -> TxX
reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] },
- emit => '
- ir_node *jumpblock = mips_get_jump_block(n, 1);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tblez %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock));
-'
+ emit => '. blez %S1, %JumpTarget1'
},
j => {
},
b => {
- op_flags => "X",
- # -> X
- reg_req => { in => [ ], out => [ "none" ] },
- emit => '
- ir_node *jumpblock = get_irn_link(n);
- assert(jumpblock != NULL);
-
- (void) cmd_buf;
- (void) cmnt_buf;
- lc_efprintf(arg_env, F, "\tb BLOCK_%d\t\t\t# mips_b\n", get_irn_node_nr(jumpblock));
-'
+ op_flags => "X",
+ # -> X
+ reg_req => { in => [ ], out => [ "none" ] },
+ emit => '. b %JumpTarget'
},
fallthrough => {
- op_flags => "X",
- # -> X
- reg_req => { in => [ ], out => [ "none" ] },
- emit => '. # fallthrough'
+ op_flags => "X",
+ # -> X
+ reg_req => { in => [ ], out => [ "none" ] },
+ emit => '. /* fallthrough to %JumpTarget */'
},
SwitchJump => {
- op_flags => "X",
- # -> X,X,...
- reg_req => { in => [ "gp" ], out => [ "none" ] },
- emit => '. j %S1'
+ op_flags => "X",
+ # -> X,X,...
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
+ emit => '. j %S1'
},
# _ _
#
load_r => {
- reg_req => { in => [ "none", "gp" ], out => [ "none", "none", "gp" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
+ reg_req => { in => [ "none", "gp" ], out => [ "none", "none", "gp" ] },
+ emit => '
+ mips_attr_t* attr = get_mips_attr(node);
ir_mode *mode;
mode = attr->modes.load_store_mode;
switch (get_mode_size_bits(mode)) {
case 8:
if (mode_is_signed(mode)) {
-3. lb %D3, %C(%S2)
- }
- else {
-3. lbu %D3, %C(%S2)
+ . lb %D3, %C(%S2)
+ } else {
+ . lbu %D3, %C(%S2)
}
break;
case 16:
if (mode_is_signed(mode)) {
-3. lh %D3, %C(%S2)
- }
- else {
-3. lhu %D3, %C(%S2)
+ . lh %D3, %C(%S2)
+ } else {
+ . lhu %D3, %C(%S2)
}
break;
case 32:
-2. lw %D3, %C(%S2)
+ . lw %D3, %C(%S2)
break;
default:
assert(! "Only 8, 16 and 32 bit loads supported");
break;
}
',
- cmp_attr => 'return attr_a->tv != attr_b->tv || attr_a->stack_entity != attr_b->stack_entity;',
+ cmp_attr => 'return attr_a->tv != attr_b->tv || attr_a->stack_entity != attr_b->stack_entity;',
},
#
store_r => {
- reg_req => { in => [ "none", "gp", "gp" ], out => [ "none", "none" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
+ reg_req => { in => [ "none", "gp", "gp" ], out => [ "none", "none" ] },
+ emit => '
+ mips_attr_t* attr = get_mips_attr(node);
ir_mode* mode;
mode = attr->modes.load_store_mode;
switch (get_mode_size_bits(mode)) {
case 8:
if (mode_is_signed(mode))
-2. sb %S3, %C(%S2)
+ . sb %S3, %C(%S2)
break;
case 16:
if (mode_is_signed(mode))
-2. sh %S3, %C(%S2)
+ . sh %S3, %C(%S2)
break;
case 32:
-2. sw %S3, %C(%S2)
+ . sw %S3, %C(%S2)
break;
default:
assert(! "Only 8, 16 and 32 bit stores supported");
break;
}
',
- cmp_attr => 'return attr_a->tv != attr_b->tv;',
+ cmp_attr => 'return attr_a->tv != attr_b->tv;',
},
store_i => {
- reg_req => { in => [ "none", "none", "gp" ], out => [ "none", "none" ] },
- emit => '
- mips_attr_t* attr = get_mips_attr(n);
+ reg_req => { in => [ "none", "none", "gp" ], out => [ "none", "none" ] },
+ emit => '
+ mips_attr_t* attr = get_mips_attr(node);
ir_mode *mode;
mode = attr->modes.load_store_mode;
switch (get_mode_size_bits(mode)) {
case 8:
-2. sb %S3, %C
+ . sb %S3, %C
break;
case 16:
-2. sh %S3, %C
+ . sh %S3, %C
break;
case 32:
-2. sw %S3, %C
+ . sw %S3, %C
break;
default:
assert(! "Only 8, 16 and 32 bit stores supported");
break;
}
',
- cmp_attr => '
- return attr_a->stack_entity != attr_b->stack_entity;
-',
+ cmp_attr => 'return attr_a->stack_entity != attr_b->stack_entity;',
},
move => {
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit => '. or %D1, $zero, %S1'
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ emit => '. move %D1, %S1',
+ mode => "mode_Iu"
},
#
#
reinterpret_conv => {
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
- emit => '. # reinterpret %S1 -> %D1',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ emit => '. # reinterpret %S1 -> %D1',
+ mode => "mode_Iu"
},
#
#
nop => {
- op_flags => "K",
- reg_req => { in => [], out => [ "none" ] },
- emit => '. nop # nop',
+ op_flags => "K",
+ reg_req => { in => [], out => [ "none" ] },
+ emit => '. nop',
},
); # end of %nodes
projects / libfirm / blobdiff