* have to pass before we can access that register again
* (because mips will write the register value back in the WB phase of the pipeline)
*/
- int busy_registers[N_mips_general_purpose_REGS];
+ int busy_registers[N_mips_gp_REGS];
/// current block
ir_node* block;
ir_node* last_nop;
// attach last nop to end node (so that firm doesn't discard it)
if(sched_env->last_nop != NULL) {
ir_node* end = get_irg_end(get_irn_irg(sched_env->block));
+ (void) end;
+ // TODO
}
sched_env->block = NULL;
}
// test all nodes in the ready set and take the first non-branch that
// is allowed
for (node = nodeset_first(ready_set); node != NULL; node = nodeset_next(ready_set)) {
- if (arch_irn_classify(arch_env, node) == arch_irn_class_branch) {
+ if (arch_irn_class_is(arch_env, node, branch)) {
if (is_irn_forking(node))
condjmp = node;
continue;
return condjmp;
}
node = nodeset_first(ready_set);
- assert(arch_irn_classify(arch_env, node) == arch_irn_class_branch);
+ assert(arch_irn_class_is(arch_env, node, branch));
nodeset_break(ready_set);
return node;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-const list_sched_selector_t *mips_get_list_sched_selector(const void *self)
+const list_sched_selector_t *mips_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
{
+#if 0
memset(&mips_sched_selector, 0, sizeof(mips_sched_selector));
mips_sched_selector.init_graph = mips_scheduler_init_graph;
mips_sched_selector.init_block = mips_scheduler_init_block;
mips_sched_selector.finish_block = mips_scheduler_finish_block;
mips_sched_selector.finish_graph = mips_scheduler_finish_graph;
return &mips_sched_selector;
+#endif
+ return selector;
}