+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
/* The main mips backend driver file. */
/* $Id$ */
#ifdef HAVE_CONFIG_H
-#include <config.h>
+#include "config.h"
#endif
#include "pseudo_irg.h"
#include "bitset.h"
#include "debug.h"
-#include "../bearch.h" /* the general register allocator interface */
+#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
* Initializes the code generator.
*/
static void *mips_cg_init(be_irg_t *birg) {
- mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
+ const arch_env_t *arch_env = be_get_birg_arch_env(birg);
+ mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
mips_code_gen_t *cg = xmalloc(sizeof(*cg));
cg->impl = &mips_code_gen_if;
- cg->irg = birg->irg;
+ cg->irg = be_get_birg_irg(birg);
cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
- cg->arch_env = birg->main_env->arch_env;
+ cg->arch_env = arch_env;
cg->isa = isa;
cg->birg = birg;
cg->bl_list = NULL;
initialstackframesize = 24;
// - setup first part of stackframe
- sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
+ sp = new_rd_mips_addiu(dbg, irg, block, sp);
attr = get_mips_attr(sp);
attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
initialstackframesize = 4;
// save old framepointer
- sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
+ sp = new_rd_mips_addiu(dbg, irg, block, sp);
attr = get_mips_attr(sp);
attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
}
// setup framepointer
- fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
+ fp = new_rd_mips_addiu(dbg, irg, block, sp);
attr = get_mips_attr(fp);
attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
int fp_save_offset = env->debug ? 16 : 0;
// copy fp to sp
- sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
+ sp = new_rd_mips_move(dbg, irg, block, fp);
mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
//arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);