-/* The main mips backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
-#ifdef HAVE_CONFIG_H
+/**
+ * @file
+ * @brief The main mips backend driver file.
+ * @author Matthias Braun, Mehdi
+ * @version $Id$
+ */
#include "config.h"
-#endif
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irgmod.h"
#include "irgopt.h"
#include "irgwalk.h"
-#include "iredges.h "
+#include "iredges.h"
#include "irdump.h"
#include "irextbb.h"
+#include "irtools.h"
+#include "error.h"
#include "bitset.h"
#include "debug.h"
-#include "../bearch.h" /* the general register allocator interface */
-#include "../benode_t.h"
+#include "../bearch.h"
+#include "../benode.h"
#include "../belower.h"
-#include "../besched_t.h"
-#include "../be.h"
+#include "../besched.h"
+#include "../beblocksched.h"
+#include "../beirg.h"
+#include "be.h"
#include "../beabi.h"
+#include "../bemachine.h"
+#include "../bemodule.h"
+#include "../bespillslots.h"
+#include "../beemitter.h"
+#include "../begnuas.h"
#include "bearch_mips_t.h"
-#include "mips_new_nodes.h" /* mips nodes interface */
-#include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
-#include "mips_gen_decls.h" /* interface declaration emitter */
+#include "mips_new_nodes.h"
+#include "gen_mips_regalloc_if.h"
#include "mips_transform.h"
#include "mips_emitter.h"
#include "mips_map_regs.h"
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
+static arch_irn_class_t mips_classify(const ir_node *irn)
+{
+ (void) irn;
+ return 0;
}
-/**
- * Return register requirements for a mips node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const mips_register_req_t *irn_req;
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
-
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
- return NULL;
- }
-
- if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
- return NULL;
- }
-
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
- if (is_Proj(irn)) {
- /* in case of a proj, we need to get the correct OUT slot */
- /* of the node corresponding to the proj number */
- if (pos == -1) {
- node_pos = mips_translate_proj_pos(irn);
- }
- else {
- node_pos = pos;
- }
-
- irn = my_skip_proj(irn);
-
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
- }
-
- /* get requirements for our own nodes */
- if (is_mips_irn(irn)) {
- if (pos >= 0) {
- irn_req = get_mips_in_req(irn, pos);
- }
- else {
- irn_req = get_mips_out_req(irn, node_pos);
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
-
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
- }
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
-
- if (mode_is_float(mode)) {
- //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req));
- assert(0 && "floating point not supported (yet)");
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(mips_default_req_mips_general_purpose.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
-
- return req;
+int mips_is_Load(const ir_node *node)
+{
+ return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
+ is_mips_lb(node) || is_mips_lbu(node);
}
-static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
- int pos = 0;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- pos = mips_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
- }
-
- if (is_mips_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_mips_slots(irn);
- slots[pos] = reg;
- }
- else {
- /* here we set the registers for the Phi nodes */
- mips_set_firm_reg(irn, reg, cur_reg_set);
- }
+int mips_is_Store(const ir_node *node)
+{
+ return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
}
-static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
- int pos = 0;
- const arch_register_t *reg = NULL;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return NULL;
- }
-
- pos = mips_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
- }
+static ir_entity *mips_get_frame_entity(const ir_node *node)
+{
+ const mips_load_store_attr_t *attr;
- if (is_mips_irn(irn)) {
- const arch_register_t **slots;
- slots = get_mips_slots(irn);
- reg = slots[pos];
- }
- else {
- reg = mips_get_firm_reg(irn, cur_reg_set);
- }
+ if(!is_mips_irn(node))
+ return NULL;
+ if(!mips_is_Load(node) && !mips_is_Store(node))
+ return NULL;
- return reg;
+ attr = get_mips_load_store_attr_const(node);
+ return attr->stack_entity;
}
-static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
+{
+ mips_load_store_attr_t *attr;
- if (is_cfop(irn)) {
- return arch_irn_class_branch;
- } else if (is_mips_irn(irn)) {
- return arch_irn_class_normal;
+ if(!is_mips_irn(node)) {
+ panic("trying to set frame entity on non load/store node %+F", node);
+ }
+ if(!mips_is_Load(node) && !mips_is_Store(node)) {
+ panic("trying to set frame entity on non load/store node %+F", node);
}
- return 0;
+ attr = get_irn_generic_attr(node);
+ attr->stack_entity = entity;
}
-static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+/**
+ * This function is called by the generic backend to correct offsets for
+ * nodes accessing the stack.
+ */
+static void mips_set_frame_offset(ir_node *node, int offset)
+{
+ mips_load_store_attr_t *attr;
- if (is_mips_irn(irn)) {
- return get_mips_flags(irn);
+ if(!is_mips_irn(node)) {
+ panic("trying to set frame offset on non load/store node %+F", node);
}
- else if (is_Unknown(irn)) {
- return arch_irn_flags_ignore;
+ if(!mips_is_Load(node) && !mips_is_Store(node)) {
+ panic("trying to set frame offset on non load/store node %+F", node);
}
- return 0;
-}
+ attr = get_irn_generic_attr(node);
+ attr->offset += offset;
-static entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
- if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
- mips_attr_t *attr = get_mips_attr(irn);
-
- return attr->stack_entity;
+ if(attr->offset < -32768 || attr->offset > 32767) {
+ panic("Out of stack space! (mips supports only 16bit offsets)");
}
-
- return NULL;
}
-/**
- * This function is called by the generic backend to correct offsets for
- * nodes accessing the stack.
- */
-static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
- mips_attr_t *attr = get_mips_attr(irn);
- assert(is_mips_load_r(irn) || is_mips_store_r(irn));
-
- attr->stack_entity_offset = offset;
+static int mips_get_sp_bias(const ir_node *irn)
+{
+ (void) irn;
+ return 0;
}
/* fill register allocator interface */
-static const arch_irn_ops_if_t mips_irn_ops_if = {
- mips_get_irn_reg_req,
- mips_set_irn_reg,
- mips_get_irn_reg,
+static const arch_irn_ops_t mips_irn_ops = {
+ get_mips_in_req,
+ get_mips_out_req,
mips_classify,
- mips_get_flags,
mips_get_frame_entity,
- mips_set_frame_offset
-};
-
-mips_irn_ops_t mips_irn_ops = {
- &mips_irn_ops_if,
- NULL
+ mips_set_frame_entity,
+ mips_set_frame_offset,
+ mips_get_sp_bias,
+ NULL, /* get_inverse */
+ NULL, /* get_op_estimated_cost */
+ NULL, /* possible_memory_operand */
+ NULL, /* perform_memory_operand */
};
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
* |___/
**************************************************/
-
-typedef struct {
- ir_node *start;
- ir_node *end;
- unsigned cnt;
-} anchor;
-
-/**
- * Ext-Block walker: create a block schedule
- */
-static void create_block_list(ir_extblk *blk, void *env) {
- anchor *list = env;
- int i, n;
-
- for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
- ir_node *block = get_extbb_block(blk, i);
-
- set_irn_link(block, NULL);
- if (list->start)
- set_irn_link(list->end, block);
- else
- list->start = block;
-
- list->end = block;
- list->cnt += 1;
- }
-}
-
-/* return the scheduled block at position pos */
-ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
- if (0 <= pos && pos < ARR_LEN(cg->bl_list))
- return cg->bl_list[pos];
- return NULL;
-}
-
-/* return the number of scheduled blocks */
-int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
- return ARR_LEN(cg->bl_list);
-}
-
-/* set a block schedule number */
-void mips_set_block_sched_nr(ir_node *block, int nr) {
- set_irn_link(block, INT_TO_PTR(nr));
-}
-
-/* get a block schedule number */
-int mips_get_block_sched_nr(ir_node *block) {
- return PTR_TO_INT(get_irn_link(block));
-}
-
-/**
- * Creates a block schedule for the given graph.
- */
-static void mips_create_block_sched(mips_code_gen_t *cg) {
- anchor list;
- ir_node **bl_list, *block;
- unsigned i;
-
- if (cg->bl_list) {
- DEL_ARR_F(cg->bl_list);
- free_survive_dce(cg->bl_list_sdce);
- }
-
- /* calculate the block schedule here */
- compute_extbb(cg->irg);
-
- list.start = NULL;
- list.end = NULL;
- list.cnt = 0;
- irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
-
-
- bl_list = NEW_ARR_F(ir_node *, list.cnt);
- cg->bl_list_sdce = new_survive_dce();
- for (i = 0, block = list.start; block; block = get_irn_link(block)) {
- bl_list[i] = block;
- survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
- i++;
- }
-
- cg->bl_list = bl_list;
-}
-
-typedef struct _wenv_t {
- ir_node *list;
-} wenv_t;
-
-/**
- * Walker: link all CopyB nodes
- */
-static void collect_copyb_nodes(ir_node *node, void *env) {
- wenv_t *wenv = env;
-
- if (get_irn_op(node) == op_CopyB) {
- set_irn_link(node, wenv->list);
- wenv->list = node;
- }
-}
-
-static void replace_copyb_nodes(mips_code_gen_t *cg) {
- wenv_t env;
- ir_node *copy, *next;
- ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
- const ir_edge_t *edge;
-
- /* build code for all copyB */
- env.list = NULL;
- irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
-
- for (copy = env.list; copy; copy = next) {
- next = get_irn_link(copy);
-
- old_bl = get_nodes_block(copy);
- part_block(copy);
- jmp = get_Block_cfgpred(old_bl, 0);
- new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
-
- new_bl = new_r_Block(cg->irg, 1, &new_jmp);
- set_nodes_block(jmp, new_bl);
-
- mem = gen_code_for_CopyB(new_bl, copy);
-
- /* fix copyB's out edges */
- foreach_out_edge(copy, edge) {
- ir_node *succ = get_edge_src_irn(edge);
-
- assert(is_Proj(succ));
- switch (get_Proj_proj(succ)) {
- case pn_CopyB_M_regular:
- case pn_CopyB_M_except:
- exchange(succ, mem);
- break;
- default:
- exchange(succ, get_irg_bad(cg->irg));
- }
- }
- }
-}
-
/**
* Transforms the standard firm graph into
* a mips firm graph
*/
static void mips_prepare_graph(void *self) {
mips_code_gen_t *cg = self;
- int bl_nr, n;
- // replace all copyb nodes in the block with a loop
- // and mips store/load nodes
- replace_copyb_nodes(cg);
+ /* do local optimizations */
+ optimize_graph_df(cg->irg);
- // Calculate block schedule
- mips_create_block_sched(cg);
-
- /* enter the block number into every blocks link field */
- for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
- ir_node *bl = mips_get_sched_block(cg, bl_nr);
- mips_set_block_sched_nr(bl, bl_nr);
- }
+ /* TODO: we often have dead code reachable through out-edges here. So for
+ * now we rebuild edges (as we need correct user count for code selection)
+ */
+#if 1
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+#endif
// walk the graph and transform firm nodes into mips nodes where possible
- irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
-
+ mips_transform_graph(cg);
dump_ir_block_graph_sched(cg->irg, "-transformed");
+
+ /* do local optimizations (mainly CSE) */
+ optimize_graph_df(cg->irg);
+
+ /* do code placement, to optimize the position of constants */
+ place_code(cg->irg);
+
+ be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
}
/**
* Called immediately before emit phase.
*/
-static void mips_finish_irg(ir_graph *irg, mips_code_gen_t *cg) {
- /* TODO: - fix offsets for nodes accessing stack
- - ...
- */
-}
+static void mips_finish_irg(void *self) {
+ mips_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
+ /* create block schedule, this also removes empty blocks which might
+ * produce critical edges */
+ cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
-/**
- * These are some hooks which must be filled but are probably not needed.
- */
-static void mips_before_sched(void *self) {
- /* Some stuff you need to do after scheduling but before register allocation */
+ dump_ir_block_graph_sched(irg, "-mips-finished");
}
-static void mips_before_ra(void *self) {
- /* Some stuff you need to do immediately after register allocation */
+
+static void mips_before_ra(void *self)
+{
+ (void) self;
}
-static void mips_after_ra(void* self) {
+static void mips_after_ra(void* self)
+{
mips_code_gen_t *cg = self;
+ be_coalesce_spillslots(cg->birg);
irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
}
* Emits the code, closes the output file and frees
* the code generator interface.
*/
-static void mips_emit_and_done(void *self) {
- mips_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->out;
-
- mips_register_emitters();
-
- if (cg->emit_decls) {
- mips_gen_decls(cg->out);
- cg->emit_decls = 0;
- }
+static void mips_emit_and_done(void *self)
+{
+ mips_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
+ (void) self;
- mips_finish_irg(irg, cg);
- dump_ir_block_graph_sched(irg, "-mips-finished");
- mips_gen_routine(out, irg, cg);
+ mips_gen_routine(cg, irg);
cur_reg_set = NULL;
/* de-allocate code generator */
del_set(cg->reg_set);
- if (cg->bl_list) {
- DEL_ARR_F(cg->bl_list);
- free_survive_dce(cg->bl_list_sdce);
- }
free(cg);
}
-static void *mips_cg_init(FILE *F, const be_irg_t *birg);
+static void *mips_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t mips_code_gen_if = {
mips_cg_init,
- NULL, /* before abi introduce */
+ NULL, /* get_pic_base */
+ NULL, /* before abi introduce */
mips_prepare_graph,
- mips_before_sched, /* before scheduling hook */
+ NULL, /* spill */
mips_before_ra, /* before register allocation hook */
mips_after_ra,
+ mips_finish_irg,
mips_emit_and_done
};
/**
* Initializes the code generator.
*/
-static void *mips_cg_init(FILE *F, const be_irg_t *birg) {
- mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
- mips_code_gen_t *cg = xmalloc(sizeof(*cg));
+static void *mips_cg_init(be_irg_t *birg)
+{
+ const arch_env_t *arch_env = be_get_birg_arch_env(birg);
+ mips_isa_t *isa = (mips_isa_t *) arch_env;
+ mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
cg->impl = &mips_code_gen_if;
- cg->irg = birg->irg;
+ cg->irg = be_get_birg_irg(birg);
cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.mips.cg");
- cg->out = F;
- cg->arch_env = birg->main_env->arch_env;
+ cg->isa = isa;
cg->birg = birg;
- cg->bl_list = NULL;
-
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- cg->emit_decls = 1;
cur_reg_set = cg->reg_set;
- mips_irn_ops.cg = cg;
+ isa->cg = cg;
return (arch_code_generator_t *)cg;
}
*****************************************************************/
static mips_isa_t mips_isa_template = {
- &mips_isa_if,
- &mips_general_purpose_regs[REG_SP],
- &mips_general_purpose_regs[REG_FP],
- -1, // stack direction
- 0 // num codegens?!? TODO what is this?
+ {
+ &mips_isa_if,
+ &mips_gp_regs[REG_SP],
+ &mips_gp_regs[REG_FP],
+ &mips_reg_classes[CLASS_mips_gp],
+ -1, /* stack direction */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
+ NULL, /* main environment */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ },
+ NULL, /* cg */
};
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *mips_init(void) {
+static arch_env_t *mips_init(FILE *file_handle) {
static int inited = 0;
mips_isa_t *isa;
if(inited)
return NULL;
+ inited = 1;
- isa = xcalloc(1, sizeof(*isa));
- memcpy(isa, &mips_isa_template, sizeof(*isa));
+ isa = XMALLOC(mips_isa_t);
+ memcpy(isa, &mips_isa_template, sizeof(isa[0]));
- mips_register_init(isa);
- mips_create_opcodes();
- mips_init_opcode_transforms();
+ be_emit_init(file_handle);
- inited = 1;
+ mips_register_init();
+ mips_create_opcodes(&mips_irn_ops);
+ // mips_init_opcode_transforms();
+
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
- return isa;
+ return &isa->arch_env;
}
/**
* Closes the output file and frees the ISA structure.
*/
-static void mips_done(void *self) {
- free(self);
+static void mips_done(void *self)
+{
+ mips_isa_t *isa = self;
+
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
+
+ be_emit_exit();
+ free(isa);
}
-static int mips_get_n_reg_class(const void *self) {
+static unsigned mips_get_n_reg_class(void)
+{
return N_CLASSES;
}
-static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
+static const arch_register_class_t *mips_get_reg_class(unsigned i)
+{
+ assert(i < N_CLASSES);
return &mips_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode)
+{
+ (void) mode;
ASSERT_NO_FLOAT(mode);
- return &mips_reg_classes[CLASS_mips_general_purpose];
+ return &mips_reg_classes[CLASS_mips_gp];
}
typedef struct {
be_abi_call_flags_bits_t flags;
- const mips_isa_t *isa;
const arch_env_t *arch_env;
ir_graph *irg;
// do special handling to support debuggers
static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
{
- mips_abi_env_t *env = xmalloc(sizeof(env[0]));
+ mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- env->arch_env = arch_env;
- env->isa = (const mips_isa_t*) arch_env->isa;
- env->debug = 1;
+ env->flags = fl.bits;
+ env->irg = irg;
+ env->arch_env = arch_env;
+ env->debug = 1;
return env;
}
-static void mips_abi_dont_save_regs(void *self, pset *s)
-{
- mips_abi_env_t *env = self;
- if(env->flags.try_omit_fp)
- pset_insert_ptr(s, env->isa->fp);
-}
-
-static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
+static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
{
mips_abi_env_t *env = self;
ir_graph *irg = env->irg;
- dbg_info *dbg = NULL; // TODO where can I get this from?
- ir_node *block = get_irg_start_block(env->irg);
- mips_attr_t *attr;
- ir_node *sp = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_SP]);
- ir_node *fp = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_FP]);
+ ir_node *block = get_irg_start_block(irg);
+ ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
+ ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
int initialstackframesize;
- if(env->debug) {
+ (void) stack_bias;
+
+ if (env->debug) {
/*
* The calling conventions wants a stack frame of at least 24bytes size with
* a0-a3 saved in offset 0-12
initialstackframesize = 24;
// - setup first part of stackframe
- sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
- attr = get_mips_attr(sp);
- attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, sp, &mips_general_purpose_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), sp, &mips_general_purpose_regs[REG_SP]);
+ sp = new_bd_mips_addu(NULL, block, sp,
+ mips_create_Immediate(initialstackframesize));
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
+ panic("FIXME Use IncSP or set register requirement with ignore");
/* TODO: where to get an edge with a0-a3
int i;
for(i = 0; i < 4; ++i) {
- ir_node *reg = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_A0 + i]);
- ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
+ ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
+ ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
attr = get_mips_attr(store);
attr->load_store_mode = mode_Iu;
attr->tv = new_tarval_from_long(i * 4, mode_Is);
}
*/
- reg = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_FP]);
- store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
- attr = get_mips_attr(store);
- attr->modes.load_store_mode = mode_Iu;
- attr->tv = new_tarval_from_long(16, mode_Is);
+ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
+ store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
- mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
+ mm[4] = store;
- reg = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_RA]);
- store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
- attr = get_mips_attr(store);
- attr->modes.load_store_mode = mode_Iu;
- attr->tv = new_tarval_from_long(20, mode_Is);
+ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
+ store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
- mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
+ mm[5] = store;
- // TODO ideally we would route these mem edges directly towards the epilogue
- sync = new_r_Sync(irg, block, 2, mm+4);
+ /* Note: ideally we would route these mem edges directly towards the
+ * epilogue, but this is currently not supported so we sync all mems
+ * together */
+ sync = new_r_Sync(block, 2, mm+4);
*mem = sync;
} else {
ir_node *reg, *store;
initialstackframesize = 4;
// save old framepointer
- sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
- attr = get_mips_attr(sp);
- attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, sp, &mips_general_purpose_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), sp, &mips_general_purpose_regs[REG_SP]);
-
- reg = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_FP]);
- store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
- attr = get_mips_attr(store);
- attr->modes.load_store_mode = mode_Iu;
- attr->tv = new_tarval_from_long(0, mode_Is);
-
- *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
+ sp = new_bd_mips_addu(NULL, block, sp,
+ mips_create_Immediate(-initialstackframesize));
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
+ panic("FIXME Use IncSP or set register requirement with ignore");
+
+ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
+ store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
+
+ *mem = store;
}
// setup framepointer
- fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
- attr = get_mips_attr(fp);
- attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, fp, &mips_general_purpose_regs[REG_FP]);
- //arch_set_irn_register(mips_get_arg_env(), fp, &mips_general_purpose_regs[REG_FP]);
+ fp = new_bd_mips_addu(NULL, block, sp,
+ mips_create_Immediate(-initialstackframesize));
+ arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
+ panic("FIXME Use IncSP or set register requirement with ignore");
- be_abi_reg_map_set(reg_map, &mips_general_purpose_regs[REG_FP], fp);
- be_abi_reg_map_set(reg_map, &mips_general_purpose_regs[REG_SP], sp);
+ be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
+ be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
- return &mips_general_purpose_regs[REG_SP];
+ return &mips_gp_regs[REG_SP];
}
static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
{
- mips_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- dbg_info *dbg = NULL; // TODO where can I get this from?
- mips_attr_t *attr;
- ir_node *sp = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_SP]);
- ir_node *fp = be_abi_reg_map_get(reg_map, &mips_general_purpose_regs[REG_FP]);
+ mips_abi_env_t *env = self;
+
+ ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
+ ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
ir_node *load;
int initial_frame_size = env->debug ? 24 : 4;
int fp_save_offset = env->debug ? 16 : 0;
- // restore sp
- //sp = be_new_IncSP(&mips_general_purpose_regs[REG_SP], irg, block, sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
-
// copy fp to sp
- sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
- mips_set_irn_reg(NULL, sp, &mips_general_purpose_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), fp, &mips_general_purpose_regs[REG_SP]);
+ sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
+ panic("FIXME Use be_Copy or set register requirement with ignore");
// 1. restore fp
- load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
- attr = get_mips_attr(load);
- attr->modes.load_store_mode = mode_Iu;
- // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
- attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
+ load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
+ fp_save_offset - initial_frame_size);
+ panic("FIXME register requirement with ignore");
- fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
- mips_set_irn_reg(NULL, fp, &mips_general_purpose_regs[REG_FP]);
- //arch_set_irn_register(mips_get_arg_env(), fp, &mips_general_purpose_regs[REG_FP]);
+ fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
+ *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
+ arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
- be_abi_reg_map_set(reg_map, &mips_general_purpose_regs[REG_FP], fp);
- be_abi_reg_map_set(reg_map, &mips_general_purpose_regs[REG_SP], sp);
+ be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
+ be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
}
/**
static ir_type *debug_between_type = NULL;
static ir_type *opt_between_type = NULL;
- static entity *old_fp_ent = NULL;
+ static ir_entity *old_fp_ent = NULL;
if(env->debug && debug_between_type == NULL) {
- entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
- entity *ret_addr_ent;
+ ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
+ ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
- set_entity_offset_bytes(a0_ent, 0);
- set_entity_offset_bytes(a1_ent, 4);
- set_entity_offset_bytes(a2_ent, 8);
- set_entity_offset_bytes(a3_ent, 12);
- set_entity_offset_bytes(old_fp_ent, 16);
- set_entity_offset_bytes(ret_addr_ent, 20);
+ set_entity_offset(a0_ent, 0);
+ set_entity_offset(a1_ent, 4);
+ set_entity_offset(a2_ent, 8);
+ set_entity_offset(a3_ent, 12);
+ set_entity_offset(old_fp_ent, 16);
+ set_entity_offset(ret_addr_ent, 20);
set_type_size_bytes(debug_between_type, 24);
} else if(!env->debug && opt_between_type == NULL) {
ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
- entity *old_fp_ent;
+ ir_entity *old_fp_ent;
opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
- set_entity_offset_bytes(old_fp_ent, 0);
+ set_entity_offset(old_fp_ent, 0);
set_type_size_bytes(opt_between_type, 4);
}
mips_abi_init,
free,
mips_abi_get_between_type,
- mips_abi_dont_save_regs,
mips_abi_prologue,
mips_abi_epilogue,
};
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+static void mips_get_call_abi(const void *self, ir_type *method_type,
+ be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
int n = get_method_n_params(method_type);
ir_mode **modes;
const arch_register_t *reg;
be_abi_call_flags_t call_flags;
+ (void) self;
memset(&call_flags, 0, sizeof(call_flags));
call_flags.bits.left_to_right = 0;
be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
/* collect the mode for each type */
- modes = alloca(n * sizeof(modes[0]));
+ modes = ALLOCAN(ir_mode*, n);
for (i = 0; i < n; i++) {
tp = get_method_param_type(method_type, i);
modes[i] = get_type_mode(tp);
for (i = 0; i < n; i++) {
// first 4 params in $a0-$a3, the others on the stack
if(i < 4) {
- reg = &mips_general_purpose_regs[REG_A0 + i];
+ reg = &mips_gp_regs[REG_A0 + i];
be_abi_call_param_reg(abi, i, reg);
} else {
/* default: all parameters on stack */
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
}
}
mode = get_type_mode(tp);
ASSERT_NO_FLOAT(mode);
- reg = &mips_general_purpose_regs[REG_V0 + i];
+ reg = &mips_gp_regs[REG_V0 + i];
be_abi_call_res_reg(abi, i, reg);
}
}
-static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- return &mips_irn_ops;
+/**
+ * Initializes the code generator interface.
+ */
+static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
+{
+ (void) self;
+ return &mips_code_gen_if;
}
-const arch_irn_handler_t mips_irn_handler = {
- mips_get_irn_ops
-};
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int mips_get_reg_class_alignment(const arch_register_class_t *cls)
+{
+ ir_mode *mode = arch_register_class_mode(cls);
+ return get_mode_size_bytes(mode);
+}
-const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
- return &mips_irn_handler;
+static const be_execution_unit_t ***mips_get_allowed_execution_units(
+ const ir_node *irn)
+{
+ (void) irn;
+ /* TODO */
+ panic("Unimplemented mips_get_allowed_execution_units()");
+}
+
+static const be_machine_t *mips_get_machine(const void *self)
+{
+ (void) self;
+ /* TODO */
+ panic("Unimplemented mips_get_machine()");
}
/**
- * Initializes the code generator interface.
+ * Return irp irgs in the desired order.
*/
-static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
- return &mips_code_gen_if;
+static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
+ return NULL;
+}
+
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *mips_get_libfirm_params(void) {
+ static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ NULL, /* will be set later */
+ NULL, /* but yet no creator function */
+ NULL, /* context for create_intrinsic_fkt */
+ NULL, /* no if conversion settings */
+ NULL, /* float arithmetic mode (TODO) */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL, /* no trampoline support: no trampoline builder */
+ 4 /* alignment of stack parameter */
+ };
+
+ return &p;
+}
+
+static asm_constraint_flags_t mips_parse_asm_constraint(const char **c)
+{
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
}
-#ifdef WITH_LIBCORE
-static void mips_register_options(lc_opt_entry_t *ent)
+static int mips_is_valid_clobber(const char *clobber)
{
+ (void) clobber;
+ return 0;
}
-#endif /* WITH_LIBCORE */
const arch_isa_if_t mips_isa_if = {
-#ifdef WITH_LIBCORE
- mips_register_options,
-#endif
mips_init,
mips_done,
+ NULL, /* handle intrinsics */
mips_get_n_reg_class,
mips_get_reg_class,
mips_get_reg_class_for_mode,
mips_get_call_abi,
- mips_get_irn_handler,
mips_get_code_generator_if,
mips_get_list_sched_selector,
+ mips_get_ilp_sched_selector,
+ mips_get_reg_class_alignment,
+ mips_get_libfirm_params,
+ mips_get_allowed_execution_units,
+ mips_get_machine,
+ mips_get_irg_list,
+ NULL, /* mark remat */
+ mips_parse_asm_constraint,
+ mips_is_valid_clobber
};
+
+void be_init_arch_mips(void)
+{
+ be_register_isa_if("mips", &mips_isa_if);
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);
projects / libfirm / blobdiff