#include "bitset.h"
#include "debug.h"
-#include "../bearch_t.h"
-#include "../benode_t.h"
+#include "../bearch.h"
+#include "../benode.h"
#include "../belower.h"
-#include "../besched_t.h"
+#include "../besched.h"
#include "../beblocksched.h"
-#include "../beirg_t.h"
+#include "../beirg.h"
#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
* |___/
**************************************************/
-/**
- * Return register requirements for a mips node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const
-arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
-{
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(node);
-
- if (is_Block(node) || mode == mode_X || mode == mode_M) {
- return arch_no_register_req;
- }
-
- if (mode == mode_T && pos < 0) {
- return arch_no_register_req;
- }
-
- if (is_Proj(node)) {
- /* in case of a proj, we need to get the correct OUT slot */
- /* of the node corresponding to the proj number */
- if (pos == -1) {
- node_pos = mips_translate_proj_pos(node);
- }
- else {
- node_pos = pos;
- }
-
- node = skip_Proj_const(node);
- }
-
- /* get requirements for our own nodes */
- if (is_mips_irn(node)) {
- const arch_register_req_t *req;
- if (pos >= 0) {
- req = get_mips_in_req(node, pos);
- } else {
- req = get_mips_out_req(node, node_pos);
- }
-
- return req;
- }
-
- /* unknown should be translated by now */
- assert(!is_Unknown(node));
-
- return arch_no_register_req;
-}
-
-static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg)
-{
- int pos = 0;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- pos = mips_translate_proj_pos(irn);
- irn = skip_Proj(irn);
- }
-
- if (is_mips_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_mips_slots(irn);
- slots[pos] = reg;
- } else {
- /* here we set the registers for the Phi nodes */
- mips_set_firm_reg(irn, reg, cur_reg_set);
- }
-}
-
static arch_irn_class_t mips_classify(const ir_node *irn)
{
- irn = skip_Proj_const(irn);
-
- if (is_cfop(irn)) {
- return arch_irn_class_branch;
- }
-
+ (void) irn;
return 0;
}
/* fill register allocator interface */
static const arch_irn_ops_t mips_irn_ops = {
- mips_get_irn_reg_req,
+ get_mips_in_req,
mips_classify,
mips_get_frame_entity,
mips_set_frame_entity,
&mips_isa_if,
&mips_gp_regs[REG_SP],
&mips_gp_regs[REG_FP],
+ &mips_reg_classes[CLASS_mips_gp],
-1, /* stack direction */
2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
mips_create_opcodes(&mips_irn_ops);
// mips_init_opcode_transforms();
- /* we mark referenced global entities, so we can only emit those which
- * are actually referenced. (Note: you mustn't use the type visited flag
- * elsewhere in the backend)
- */
- inc_master_type_visited();
-
return &isa->arch_env;
}
{
mips_isa_t *isa = self;
- be_gas_emit_decls(isa->arch_env.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env);
be_emit_exit();
free(isa);
}
-static unsigned mips_get_n_reg_class(const void *self)
+static unsigned mips_get_n_reg_class(void)
{
- (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *mips_get_reg_class(const void *self,
- unsigned i)
+static const arch_register_class_t *mips_get_reg_class(unsigned i)
{
- (void) self;
assert(i < N_CLASSES);
return &mips_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
- const ir_mode *mode)
+const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode)
{
- (void) self;
(void) mode;
ASSERT_NO_FLOAT(mode);
return &mips_reg_classes[CLASS_mips_gp];
// - setup first part of stackframe
sp = new_bd_mips_addu(NULL, block, sp,
mips_create_Immediate(initialstackframesize));
- mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
panic("FIXME Use IncSP or set register requirement with ignore");
/* TODO: where to get an edge with a0-a3
/* Note: ideally we would route these mem edges directly towards the
* epilogue, but this is currently not supported so we sync all mems
* together */
- sync = new_r_Sync(irg, block, 2, mm+4);
+ sync = new_r_Sync(block, 2, mm+4);
*mem = sync;
} else {
ir_node *reg, *store;
// save old framepointer
sp = new_bd_mips_addu(NULL, block, sp,
mips_create_Immediate(-initialstackframesize));
- mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
panic("FIXME Use IncSP or set register requirement with ignore");
reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
// setup framepointer
fp = new_bd_mips_addu(NULL, block, sp,
mips_create_Immediate(-initialstackframesize));
- mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]);
+ arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
panic("FIXME Use IncSP or set register requirement with ignore");
be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
{
mips_abi_env_t *env = self;
- ir_graph *irg = env->irg;
ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
ir_node *load;
// copy fp to sp
sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
- mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
panic("FIXME Use be_Copy or set register requirement with ignore");
// 1. restore fp
fp_save_offset - initial_frame_size);
panic("FIXME register requirement with ignore");
- fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
- *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
+ fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
+ *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
if(env->debug && debug_between_type == NULL) {
ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
ir_entity *ret_addr_ent;
- ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
- ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
- ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
+ ir_type *ret_addr_type = new_type_primitive(mode_P);
+ ir_type *old_fp_type = new_type_primitive(mode_P);
+ ir_type *old_param_type = new_type_primitive(mode_Iu);
debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
set_type_size_bytes(debug_between_type, 24);
} else if(!env->debug && opt_between_type == NULL) {
- ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
+ ir_type *old_fp_type = new_type_primitive(mode_P);
ir_entity *old_fp_ent;
opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int mips_get_reg_class_alignment(const void *self,
- const arch_register_class_t *cls)
+static int mips_get_reg_class_alignment(const arch_register_class_t *cls)
{
ir_mode *mode = arch_register_class_mode(cls);
- (void) self;
return get_mode_size_bytes(mode);
}
static const be_execution_unit_t ***mips_get_allowed_execution_units(
- const void *self, const ir_node *irn)
+ const ir_node *irn)
{
- (void) self;
(void) irn;
/* TODO */
panic("Unimplemented mips_get_allowed_execution_units()");
return &p;
}
-static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
- const char **c)
+static asm_constraint_flags_t mips_parse_asm_constraint(const char **c)
{
- (void) self;
(void) c;
return ASM_CONSTRAINT_FLAG_INVALID;
}
-static int mips_is_valid_clobber(const void *self, const char *clobber)
+static int mips_is_valid_clobber(const char *clobber)
{
- (void) self;
(void) clobber;
return 0;
}
projects / libfirm / blobdiff