/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "iredges.h"
#include "irdump.h"
#include "irextbb.h"
+#include "irtools.h"
#include "error.h"
#include "bitset.h"
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
#include "../bemodule.h"
* will be asked for this information.
*/
static const
-arch_register_req_t *mips_get_irn_reg_req(const void *self,
- const ir_node *node, int pos) {
+arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(node);
return arch_no_register_req;
}
-static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg)
+{
int pos = 0;
if (is_Proj(irn)) {
slots = get_mips_slots(irn);
slots[pos] = reg;
- }
- else {
+ } else {
/* here we set the registers for the Phi nodes */
mips_set_firm_reg(irn, reg, cur_reg_set);
}
}
-static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *mips_get_irn_reg(const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
return reg;
}
-static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
+static arch_irn_class_t mips_classify(const ir_node *irn)
+{
irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return 0;
}
-static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
+static arch_irn_flags_t mips_get_flags(const ir_node *irn)
+{
irn = skip_Proj_const(irn);
- if (is_mips_irn(irn)) {
- return get_mips_flags(irn);
- }
- else if (is_Unknown(irn)) {
- return arch_irn_flags_ignore;
- }
+ if (!is_mips_irn(irn))
+ return 0;
- return 0;
+ return get_mips_flags(irn);
+}
+
+int mips_is_Load(const ir_node *node)
+{
+ return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
+ is_mips_lb(node) || is_mips_lbu(node);
+}
+
+int mips_is_Store(const ir_node *node)
+{
+ return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
}
-static
-ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) {
- mips_attr_t *attr;
+static ir_entity *mips_get_frame_entity(const ir_node *node)
+{
+ const mips_load_store_attr_t *attr;
if(!is_mips_irn(node))
return NULL;
+ if(!mips_is_Load(node) && !mips_is_Store(node))
+ return NULL;
- attr = get_mips_attr(node);
+ attr = get_mips_load_store_attr_const(node);
return attr->stack_entity;
}
-static
-void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
- mips_attr_t *attr = get_mips_attr(irn);
- attr->stack_entity = ent;
+static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
+{
+ mips_load_store_attr_t *attr;
+
+ if(!is_mips_irn(node)) {
+ panic("trying to set frame entity on non load/store node %+F", node);
+ }
+ if(!mips_is_Load(node) && !mips_is_Store(node)) {
+ panic("trying to set frame entity on non load/store node %+F", node);
+ }
+
+ attr = get_irn_generic_attr(node);
+ attr->stack_entity = entity;
}
/**
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void mips_set_frame_offset(const void *self, ir_node *irn, int offset)
+static void mips_set_frame_offset(ir_node *node, int offset)
{
- panic("TODO");
-#if 0
- mips_attr_t *attr = get_mips_attr(irn);
- attr->stack_entity_offset = offset;
-#endif
+ mips_load_store_attr_t *attr;
+
+ if(!is_mips_irn(node)) {
+ panic("trying to set frame offset on non load/store node %+F", node);
+ }
+ if(!mips_is_Load(node) && !mips_is_Store(node)) {
+ panic("trying to set frame offset on non load/store node %+F", node);
+ }
+
+ attr = get_irn_generic_attr(node);
+ attr->offset += offset;
+
+ if(attr->offset < -32768 || attr->offset > 32767) {
+ panic("Out of stack space! (mips supports only 16bit offsets)");
+ }
}
-static int mips_get_sp_bias(const void *self, const ir_node *irn) {
+static int mips_get_sp_bias(const ir_node *irn)
+{
+ (void) irn;
return 0;
}
/* fill register allocator interface */
-static const arch_irn_ops_if_t mips_irn_ops_if = {
+static const arch_irn_ops_t mips_irn_ops = {
mips_get_irn_reg_req,
mips_set_irn_reg,
mips_get_irn_reg,
NULL, /* perform_memory_operand */
};
-mips_irn_ops_t mips_irn_ops = {
- &mips_irn_ops_if,
- NULL
-};
-
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
}
// walk the graph and transform firm nodes into mips nodes where possible
- irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
-
+ mips_transform_graph(cg);
dump_ir_block_graph_sched(cg->irg, "-transformed");
}
/**
* These are some hooks which must be filled but are probably not needed.
*/
-static void mips_before_sched(void *self) {
- /* Some stuff you need to do after scheduling but before register allocation */
+static void mips_before_sched(void *self)
+{
+ (void) self;
}
-static void mips_before_ra(void *self) {
- /* Some stuff you need to do immediately after register allocation */
+static void mips_before_ra(void *self)
+{
+ (void) self;
}
-static void mips_after_ra(void* self) {
+static void mips_after_ra(void* self)
+{
mips_code_gen_t *cg = self;
be_coalesce_spillslots(cg->birg);
irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
* Emits the code, closes the output file and frees
* the code generator interface.
*/
-static void mips_emit_and_done(void *self) {
+static void mips_emit_and_done(void *self)
+{
mips_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
+ (void) self;
mips_gen_routine(cg, irg);
static const arch_code_generator_if_t mips_code_gen_if = {
mips_cg_init,
+ NULL, /* get_pic_base */
NULL, /* before abi introduce */
mips_prepare_graph,
NULL, /* spill */
/**
* Initializes the code generator.
*/
-static void *mips_cg_init(be_irg_t *birg) {
+static void *mips_cg_init(be_irg_t *birg)
+{
const arch_env_t *arch_env = be_get_birg_arch_env(birg);
- mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
+ mips_isa_t *isa = (mips_isa_t *) arch_env;
mips_code_gen_t *cg = xmalloc(sizeof(*cg));
cg->impl = &mips_code_gen_if;
cur_reg_set = cg->reg_set;
- mips_irn_ops.cg = cg;
+ isa->cg = cg;
return (arch_code_generator_t *)cg;
}
&mips_gp_regs[REG_SP],
&mips_gp_regs[REG_FP],
-1, /* stack direction */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
},
- { NULL, }, /* emitter environment */
+ NULL, /* cg */
};
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *mips_init(FILE *file_handle) {
+static arch_env_t *mips_init(FILE *file_handle) {
static int inited = 0;
mips_isa_t *isa;
isa = xcalloc(1, sizeof(isa[0]));
memcpy(isa, &mips_isa_template, sizeof(isa[0]));
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
- mips_register_init(isa);
- mips_create_opcodes();
+ mips_register_init();
+ mips_create_opcodes(&mips_irn_ops);
// mips_init_opcode_transforms();
/* we mark referenced global entities, so we can only emit those which
*/
inc_master_type_visited();
- return isa;
+ return &isa->arch_env;
}
/**
* Closes the output file and frees the ISA structure.
*/
-static void mips_done(void *self) {
+static void mips_done(void *self)
+{
mips_isa_t *isa = self;
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(isa);
}
-static int mips_get_n_reg_class(const void *self) {
+static unsigned mips_get_n_reg_class(const void *self)
+{
+ (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
+static const arch_register_class_t *mips_get_reg_class(const void *self,
+ unsigned i)
+{
+ (void) self;
+ assert(i < N_CLASSES);
return &mips_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
+ const ir_mode *mode)
+{
+ (void) self;
+ (void) mode;
ASSERT_NO_FLOAT(mode);
return &mips_reg_classes[CLASS_mips_gp];
}
typedef struct {
be_abi_call_flags_bits_t flags;
- const arch_isa_t *isa;
const arch_env_t *arch_env;
ir_graph *irg;
// do special handling to support debuggers
env->flags = fl.bits;
env->irg = irg;
env->arch_env = arch_env;
- env->isa = arch_env->isa;
env->debug = 1;
return env;
}
mips_abi_env_t *env = self;
if(env->flags.try_omit_fp)
- pset_insert_ptr(s, env->isa->bp);
+ pset_insert_ptr(s, env->arch_env->bp);
}
static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
{
mips_abi_env_t *env = self;
ir_graph *irg = env->irg;
- dbg_info *dbg = NULL; // TODO where can I get this from?
ir_node *block = get_irg_start_block(env->irg);
- mips_attr_t *attr;
ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
int initialstackframesize;
initialstackframesize = 24;
// - setup first part of stackframe
- sp = new_rd_mips_addiu(dbg, irg, block, sp);
- attr = get_mips_attr(sp);
- attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
+ sp = new_rd_mips_addu(NULL, irg, block, sp,
+ mips_create_Immediate(initialstackframesize));
+ mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ set_mips_flags(sp, arch_irn_flags_ignore);
/* TODO: where to get an edge with a0-a3
int i;
*/
reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
- store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
- attr = get_mips_attr(store);
- attr->tv = new_tarval_from_long(16, mode_Hs);
+ store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16);
mm[4] = store;
reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
- store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
- attr = get_mips_attr(store);
- attr->tv = new_tarval_from_long(20, mode_Hs);
+ store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20);
mm[5] = store;
- // TODO ideally we would route these mem edges directly towards the epilogue
+ /* Note: ideally we would route these mem edges directly towards the
+ * epilogue, but this is currently not supported so we sync all mems
+ * together */
sync = new_r_Sync(irg, block, 2, mm+4);
*mem = sync;
} else {
initialstackframesize = 4;
// save old framepointer
- sp = new_rd_mips_addiu(dbg, irg, block, sp);
- attr = get_mips_attr(sp);
- attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
+ sp = new_rd_mips_addu(NULL, irg, block, sp,
+ mips_create_Immediate(-initialstackframesize));
+ mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ set_mips_flags(sp, arch_irn_flags_ignore);
reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
- store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
- attr = get_mips_attr(store);
- attr->tv = new_tarval_from_long(0, mode_Hs);
+ store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0);
*mem = store;
}
// setup framepointer
- fp = new_rd_mips_addiu(dbg, irg, block, sp);
- attr = get_mips_attr(fp);
- attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
- mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
- //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
+ fp = new_rd_mips_addu(NULL, irg, block, sp,
+ mips_create_Immediate(-initialstackframesize));
+ mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]);
+ set_mips_flags(fp, arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
{
- mips_abi_env_t *env = self;
+ mips_abi_env_t *env = self;
+
ir_graph *irg = env->irg;
- dbg_info *dbg = NULL; // TODO where can I get this from?
- mips_attr_t *attr;
ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
ir_node *load;
int fp_save_offset = env->debug ? 16 : 0;
// copy fp to sp
- sp = new_rd_mips_move(dbg, irg, block, fp);
- mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
- //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
+ sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero());
+ mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
+ set_mips_flags(sp, arch_irn_flags_ignore);
// 1. restore fp
- load = new_rd_mips_lw(dbg, irg, block, *mem, sp);
- attr = get_mips_attr(load);
- // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
- attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Hs);
+ load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL,
+ fp_save_offset - initial_frame_size);
+ set_mips_flags(load, arch_irn_flags_ignore);
fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
*mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+static void mips_get_call_abi(const void *self, ir_type *method_type,
+ be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
int n = get_method_n_params(method_type);
ir_mode **modes;
const arch_register_t *reg;
be_abi_call_flags_t call_flags;
+ (void) self;
memset(&call_flags, 0, sizeof(call_flags));
call_flags.bits.left_to_right = 0;
be_abi_call_param_reg(abi, i, reg);
} else {
/* default: all parameters on stack */
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
}
}
}
}
-static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- return &mips_irn_ops;
-}
-
-const arch_irn_handler_t mips_irn_handler = {
- mips_get_irn_ops
-};
-
-const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
- return &mips_irn_handler;
-}
-
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
+{
+ (void) self;
return &mips_code_gen_if;
}
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+static int mips_get_reg_class_alignment(const void *self,
+ const arch_register_class_t *cls)
+{
ir_mode *mode = arch_register_class_mode(cls);
+ (void) self;
return get_mode_size_bytes(mode);
}
-static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
+static const be_execution_unit_t ***mips_get_allowed_execution_units(
+ const void *self, const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
/* TODO */
assert(0);
return NULL;
}
-static const be_machine_t *mips_get_machine(const void *self) {
+static const be_machine_t *mips_get_machine(const void *self)
+{
+ (void) self;
/* TODO */
assert(0);
return NULL;
/**
* Return irp irgs in the desired order.
*/
-static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
+static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
return NULL;
}
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *mips_get_libfirm_params(void) {
- static arch_dep_params_t ad = {
- 1, /* allow subs */
- 0, /* Muls are fast enough on Mips */
- 31, /* shift would be ok */
- 0, /* no Mulhs */
- 0, /* no Mulhu */
- 32, /* Mulhs & Mulhu available for 32 bit */
- };
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ 0, /* no immediate floating point mode. */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ NULL, /* no if conversion settings */
+ NULL /* no immediate fp mode */
};
- p.dep_param = &ad;
return &p;
}
+static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
+ const char **c)
+{
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int mips_is_valid_clobber(const void *self, const char *clobber)
+{
+ (void) self;
+ (void) clobber;
+ return 0;
+}
+
const arch_isa_if_t mips_isa_if = {
mips_init,
mips_done,
mips_get_reg_class,
mips_get_reg_class_for_mode,
mips_get_call_abi,
- mips_get_irn_handler,
mips_get_code_generator_if,
mips_get_list_sched_selector,
mips_get_ilp_sched_selector,
mips_get_allowed_execution_units,
mips_get_machine,
mips_get_irg_list,
+ mips_parse_asm_constraint,
+ mips_is_valid_clobber
};
void be_init_arch_mips(void)
projects / libfirm / blobdiff