-/**
- * This file implements the x87 support and virtual to stack
- * register translation for the ia32 backend.
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
*
- * @author: Michael Beck
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
*
- * $Id$
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
+/**
+ * @file
+ * @brief This file implements the x87 support and virtual to stack
+ * register translation for the ia32 backend.
+ * @author Michael Beck
+ * @version $Id$
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
static x87_state _empty = { { {0, NULL}, }, 0, 0 };
static x87_state *empty = (x87_state *)&_empty;
-/** The type of an instruction simulator function. */
+enum {
+ NO_NODE_ADDED = 0, /**< No node was added. */
+ NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
+};
+
+/**
+ * The type of an instruction simulator function.
+ *
+ * @param state the x87 state
+ * @param n the node to be simulated
+ *
+ * @return NODE_ADDED if a node was added AFTER n in schedule,
+ * NO_NODE_ADDED else
+ */
typedef int (*sim_func)(x87_state *state, ir_node *n);
/**
be_lv_t *lv; /**< intrablock liveness. */
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
- waitq *worklist; /**< list of blocks to process. */
+ waitq *worklist; /**< Worklist of blocks that must be processed. */
};
/**
*/
static int x87_get_depth(const x87_state *state) {
return state->depth;
-}
-
-#if 0
-/**
- * Check if the state is empty.
- *
- * @param state the x87 state
- *
- * returns non-zero if the x87 stack is empty
- */
-static int x87_state_is_empty(const x87_state *state) {
- return state->depth == 0;
-}
-#endif
+} /* x87_get_depth */
/**
* Return the virtual register index at st(pos).
static int x87_get_st_reg(const x87_state *state, int pos) {
assert(pos < state->depth);
return state->st[MASK_TOS(state->tos + pos)].reg_idx;
-}
+} /* x87_get_st_reg */
/**
* Return the node at st(pos).
x87_set_st(state, reg_idx, node, 0);
} /* x87_set_tos */
-#if 0
-/**
- * Flush the x87 stack.
- *
- * @param state the x87 state
- */
-static void x87_flush(x87_state *state) {
- state->depth = 0;
- state->tos = 0;
-} /* x87_flush */
-#endif
-
/**
* Swap st(0) with st(pos).
*
} /* x87_push_dbl */
/**
- * Push a virtual Register onto the stack, double pushes are NOT allowed..
+ * Push a virtual Register onto the stack, double pushes are NOT allowed.
*
* @param state the x87 state
* @param reg_idx the register vfp index
/**
* Pop a virtual Register from the stack.
+ *
+ * @param state the x87 state
*/
static void x87_pop(x87_state *state) {
assert(state->depth > 0 && "stack underrun");
return res;
} /* x87_alloc_state */
-#if 0
-/**
- * Create a new empty x87 state.
- *
- * @param sim the x87 simulator handle
- *
- * @return a new empty x87 state
- */
-static x87_state *x87_alloc_empty_state(x87_simulator *sim) {
- x87_state *res = x87_alloc_state(sim);
-
- x87_flush(res);
- return res;
-} /* x87_alloc_empty_state */
-#endif
-
/**
* Clone a x87 state.
*
/**
* Patch a virtual instruction into a x87 one and return
- * the value node.
+ * the node representing the result value.
*
* @param n the IR node to patch
* @param op the x87 opcode to patch in
}
}
}
- }
- else if (mode_is_float(mode))
+ } else if (mode_is_float(mode))
set_irn_mode(n, mode_E);
return res;
} /* x87_patch_insn */
res = arch_get_irn_register(sim->arch_env, irn);
assert(res->reg_class->regs == ia32_vfp_regs);
return res;
-}
+} /* x87_get_irn_register */
/* -------------- x87 perm --------------- */
*
* @return the fxch node
*/
-static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
-{
+static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
ir_node *fxch;
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E);
- attr = get_ia32_attr(fxch);
+ attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
* @return the fxch
*/
static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) {
- ir_node *fxch;
- ia32_attr_t *attr;
- ir_graph *irg = get_irn_irg(n);
- ir_node *block = get_nodes_block(n);
+ ir_node *fxch;
+ ia32_x87_attr_t *attr;
+ ir_graph *irg = get_irn_irg(n);
+ ir_node *block = get_nodes_block(n);
x87_fxch(state, pos);
fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E);
- attr = get_ia32_attr(fxch);
+ attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
*/
static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
ir_node *fpush, *pred = get_irn_n(n, op_idx);
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
const arch_register_t *out = x87_get_irn_register(state->sim, pred);
x87_push_dbl(state, arch_register_get_index(out), pred);
fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
- attr = get_ia32_attr(fpush);
+ attr = get_ia32_x87_attr(fpush);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
* @param state the x87 state
* @param n the node after the fpop
* @param num pop 1 or 2 values
- * @param pred node to use as predecessor of the fpop
*
* @return the fpop node
*/
-static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node *pred) {
- ir_node *fpop = pred;
- ia32_attr_t *attr;
+static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
+{
+ ir_node *fpop;
+ ia32_x87_attr_t *attr;
while (num > 0) {
- keep_alive(pred);
-
x87_pop(state);
fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
- attr = get_ia32_attr(fpop);
+ attr = get_ia32_x87_attr(fpop);
attr->x87[0] = &ia32_st_regs[0];
attr->x87[1] = &ia32_st_regs[0];
attr->x87[2] = &ia32_st_regs[0];
sched_add_before(n, fpop);
DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
- pred = fpop;
--num;
}
return fpop;
* @param state the x87 state
* @param n the node that should be simulated (and patched)
* @param tmpl the template containing the 4 possible x87 opcodes
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
int op2_idx = 0, op1_idx;
int out_idx, do_pop = 0;
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
ir_node *patched_insn;
ir_op *dst;
x87_simulator *sim = state->sim;
}
/* patch the operation */
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
if (reg_index_2 != REG_VFP_NOREG) {
attr->x87[1] = op2 = &ia32_st_regs[op2_idx];
arch_register_get_name(out)));
}
- return 0;
+ return NO_NODE_ADDED;
} /* sim_binop */
/**
* @param state the x87 state
* @param n the node that should be simulated (and patched)
* @param op the x87 opcode that will replace n's opcode
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
int op1_idx, out_idx;
x87_simulator *sim = state->sim;
const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
const arch_register_t *out = x87_get_irn_register(sim, n);
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
out_idx = 0;
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[0] = op1 = &ia32_st_regs[0];
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
- return 0;
+ return NO_NODE_ADDED;
} /* sim_unop */
/**
* @param state the x87 state
* @param n the node that should be simulated (and patched)
* @param op the x87 opcode that will replace n's opcode
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
const arch_register_t *out = x87_get_irn_register(state->sim, n);
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
assert(out == x87_get_irn_register(state->sim, n));
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
- return 0;
+ return NO_NODE_ADDED;
} /* sim_load */
/**
ir_node *val = get_irn_n(n, STORE_VAL_IDX);
const arch_register_t *op2 = x87_get_irn_register(sim, val);
unsigned live = vfp_live_args_after(sim, n, 0);
- int insn = 0;
- ia32_attr_t *attr;
+ int insn = NO_NODE_ADDED;
+ ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
int live_after_node;
ir_mode *mode;
op2_reg_idx = arch_register_get_index(op2);
if (op2_reg_idx == REG_VFP_UKNWN) {
- // just take any value from stack
+ /* just take any value from stack */
if(state->depth > 0) {
op2_idx = 0;
DEBUG_ONLY(op2 = NULL);
live_after_node = 1;
} else {
- // produce a new value which we will consume imediately
+ /* produce a new value which we will consume immediately */
x87_create_fldz(state, n, op2_reg_idx);
live_after_node = 0;
op2_idx = x87_on_stack(state, op2_reg_idx);
x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX);
x87_pop(state);
x87_patch_insn(n, op_p);
- }
- else {
+ } else {
ir_node *vfld, *mem, *block, *rproj, *mproj;
ir_graph *irg;
/* rewire all users, scheduled after the store, to the loaded value */
collect_and_rewire_users(n, val, rproj);
- insn = 1;
+ insn = NODE_ADDED;
}
- }
- else {
+ } else {
/* we can only store the tos to memory */
- if(op2_idx != 0)
+ if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
/* mode != mode_E -> use normal fst */
x87_patch_insn(n, op);
}
- }
- else {
+ } else {
/* we can only store the tos to memory */
- if(op2_idx != 0)
+ if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
x87_pop(state);
x87_patch_insn(n, op_p);
}
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[1] = op2 = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
* @param state the x87 state
* @param n the node that should be simulated (and patched)
* @param arch_env the architecture environment
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
ir_mode *mode = get_irn_mode(n);
if (mode_is_float(mode))
set_irn_mode(n, mode_E);
- return 0;
+ return NO_NODE_ADDED;
} /* sim_Phi */
#define _GEN_BINOP(op, rev) \
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_fCondJmp(x87_state *state, ir_node *n) {
int op1_idx;
int op2_idx = -1;
int pop_cnt = 0;
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
ir_op *dst;
x87_simulator *sim = state->sim;
const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
x87_pop(state);
/* patch the operation */
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
op1 = &ia32_st_regs[op1_idx];
attr->x87[0] = op1;
if (op2_idx >= 0) {
DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
arch_register_get_name(op1)));
- return 0;
+ return NO_NODE_ADDED;
} /* sim_fCondJmp */
+static
+int sim_Keep(x87_state *state, ir_node *node)
+{
+ const ir_node *op;
+ const arch_register_t *op_reg;
+ int reg_id;
+ int op_stack_idx;
+ unsigned live;
+
+ op = get_irn_n(node, 0);
+ op_reg = arch_get_irn_register(state->sim->arch_env, op);
+ if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+ return NO_NODE_ADDED;
+
+ reg_id = arch_register_get_index(op_reg);
+ live = vfp_live_args_after(state->sim, node, 0);
+
+ op_stack_idx = x87_on_stack(state, reg_id);
+ if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
+ x87_create_fpop(state, sched_next(node), 1);
+ return NODE_ADDED;
+ }
+
+ return NO_NODE_ADDED;
+}
+
+static
+void keep_float_node_alive(x87_state *state, ir_node *node)
+{
+ ir_graph *irg;
+ ir_node *block;
+ ir_node *in[1];
+ ir_node *keep;
+ const arch_register_class_t *cls;
+
+ irg = get_irn_irg(node);
+ block = get_nodes_block(node);
+ cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
+ in[0] = node;
+ keep = be_new_Keep(cls, irg, block, 1, in);
+
+ assert(sched_is_scheduled(node));
+ sched_add_after(node, keep);
+}
+
+/**
+ * Create a copy of a node. Recreate the node if it's a constant.
+ *
+ * @param state the x87 state
+ * @param n the node to be copied
+ *
+ * @return the copy of n
+ */
static ir_node *create_Copy(x87_state *state, ir_node *n) {
x87_simulator *sim = state->sim;
ir_graph *irg = get_irn_irg(n);
ir_node *res;
const arch_register_t *out;
const arch_register_t *op1;
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
/* Do not copy constants, recreate them. */
switch (get_ia32_irn_opcode(pred)) {
case iro_ia32_fldln2:
cnstr = new_rd_ia32_fldln2;
break;
+ default:
+ break;
}
out = x87_get_irn_register(sim, n);
op1 = x87_get_irn_register(sim, pred);
- if(cnstr != NULL) {
+ if (cnstr != NULL) {
/* copy a constant */
res = (*cnstr)(n_dbg, irg, block, mode);
x87_push(state, arch_register_get_index(out), res);
- attr = get_ia32_attr(res);
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr = get_ia32_x87_attr(res);
+ attr->x87[2] = &ia32_st_regs[0];
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
x87_push(state, arch_register_get_index(out), res);
- attr = get_ia32_attr(res);
- attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr = get_ia32_x87_attr(res);
+ attr->x87[0] = &ia32_st_regs[op1_idx];
+ attr->x87[2] = &ia32_st_regs[0];
}
arch_set_irn_register(sim->arch_env, res, out);
return res;
-}
+} /* create_Copy */
/**
* Simulate a be_Copy.
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Copy(x87_state *state, ir_node *n) {
x87_simulator *sim;
const arch_register_t *out;
const arch_register_t *op1;
ir_node *node, *next;
- ia32_attr_t *attr;
+ ia32_x87_attr_t *attr;
int op1_idx, out_idx;
unsigned live;
DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
arch_get_irn_register(sim->arch_env, node)->name));
- return 0;
+ return NO_NODE_ADDED;
}
op1_idx = x87_on_stack(state, arch_register_get_index(op1));
if (is_vfp_live(arch_register_get_index(op1), live)) {
+ ir_node *pred = get_irn_n(n, 0);
+
/* Operand is still live, a real copy. We need here an fpush that can
hold a a register, so use the fpushCopy or recreate constants */
node = create_Copy(state, n);
+ /* We have to make sure the old value doesn't go dead (which can happen
+ * when we recreate constants). As the simulator expected that value in
+ * the pred blocks. This is unfortunate as removing it would save us 1
+ * instruction, but we would have to rerun all the simulation to get
+ * this correct...
+ */
next = sched_next(n);
sched_remove(n);
exchange(n, node);
sched_add_before(next, node);
+
+ if(get_irn_n_edges(pred) == 0) {
+ keep_float_node_alive(state, pred);
+ }
+
DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
arch_get_irn_register(sim->arch_env, node)->name));
} else {
if (out_idx == 0) {
/* best case, simple remove and rename */
x87_patch_insn(n, op_ia32_Pop);
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[0] = op1 = &ia32_st_regs[0];
x87_pop(state);
op1_idx = 0;
}
x87_patch_insn(n, op_ia32_Pop);
- attr = get_ia32_attr(n);
+ attr = get_ia32_x87_attr(n);
attr->x87[0] = op1 = &ia32_st_regs[out_idx];
x87_pop(state);
} else {
/* just a virtual copy */
x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
+ /* don't remove the node to keep the verifier quiet :),
+ the emitter won't emit any code for the node */
+#if 0
sched_remove(n);
DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
exchange(n, get_unop_op(n));
+#endif
}
}
-
- return 0;
+ return NO_NODE_ADDED;
} /* sim_Copy */
/**
* Returns the result proj of the call, or NULL if the result is not used
*/
-static ir_node *get_call_result_proj(ir_node *call)
-{
+static ir_node *get_call_result_proj(ir_node *call) {
const ir_edge_t *edge;
ir_node *resproj = NULL;
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if(pn == pn_be_Call_first_res) {
+ if (pn == pn_be_Call_first_res) {
resproj = proj;
break;
}
}
- if(resproj == NULL) {
+ if (resproj == NULL) {
return NULL;
}
/* the result proj is connected to a Keep and maybe other nodes */
foreach_out_edge(resproj, edge) {
ir_node *pred = get_edge_src_irn(edge);
- if(!be_is_Keep(pred)) {
+ if (!be_is_Keep(pred)) {
return resproj;
}
}
/* only be_Keep found, so result is not used */
return NULL;
-}
+} /* get_call_result_proj */
/**
* Simulate a be_Call.
* @param state the x87 state
* @param n the node that should be simulated
* @param arch_env the architecture environment
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
ir_type *call_tp = be_Call_get_type(n);
assert(state->depth == 0 && "stack not empty before call");
if (get_method_n_ress(call_tp) <= 0)
- return 0;
+ return NO_NODE_ADDED;
/*
* If the called function returns a float, it is returned in st(0).
mode = get_type_mode(res_type);
if (mode == NULL || !mode_is_float(mode))
- return 0;
+ return NO_NODE_ADDED;
resproj = get_call_result_proj(n);
if (resproj == NULL)
- return 0;
+ return NO_NODE_ADDED;
reg = x87_get_irn_register(state->sim, resproj);
x87_push(state, arch_register_get_index(reg), resproj);
- return 0;
+ return NO_NODE_ADDED;
} /* sim_Call */
/**
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Return(x87_state *state, ir_node *n) {
int n_res = be_Return_get_n_rets(n);
for (i = n_float_res - 1; i >= 0; --i)
x87_pop(state);
- return 0;
+ return NO_NODE_ADDED;
} /* sim_Return */
typedef struct _perm_data_t {
*
* @param state the x87 state
* @param irn the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Perm(x87_state *state, ir_node *irn) {
int i, n;
/* handle only floating point Perms */
if (! mode_is_float(get_irn_mode(pred)))
- return 0;
+ return NO_NODE_ADDED;
DB((dbg, LEVEL_1, ">>> %+F\n", irn));
}
DB((dbg, LEVEL_1, "<<< %+F\n", irn));
- return 0;
-} /* be_Perm */
+ return NO_NODE_ADDED;
+} /* sim_Perm */
/**
* Kill any dead registers at block start by popping them from the stack.
* @param sim the simulator handle
* @param block the current block
* @param start_state the x87 state at the begin of the block
+ *
+ * @return the x87 state after dead register killed
*/
static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
x87_state *state = start_state;
if (keep)
x87_set_st(state, -1, keep, i);
- keep = x87_create_fxch(state, first_insn, i, -1);
+ x87_create_fxch(state, first_insn, i, -1);
}
- else if (! keep)
- keep = x87_get_st_node(state, 0);
if ((kill_mask & 3) == 3) {
/* we can do a double-pop */
depth -= num_pop;
kill_mask >>= num_pop;
- keep = x87_create_fpop(state, first_insn, num_pop, keep);
+ keep = x87_create_fpop(state, first_insn, num_pop);
}
keep_alive(keep);
}
*
* @param sim the simulator handle
* @param block the current block
- *
- * @return non-zero if simulation is complete,
- * zero if the simulation must be rerun
*/
static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
ir_node *n, *next;
ir_node *start_block;
assert(state != NULL);
- // already processed?
- if(bl_state->end != NULL)
+ /* already processed? */
+ if (bl_state->end != NULL)
return;
- //update_liveness(sim, block);
-
DB((dbg, LEVEL_1, "Simulate %+F\n", block));
DB((dbg, LEVEL_2, "State at Block begin:\n "));
DEBUG_ONLY(x87_dump_stack(state));
node_inserted = (*func)(state, n);
/*
- sim_func might have added additional nodes after n,
+ sim_func might have added an additional node after n,
so update next node
beware: n must not be changed by sim_func
(i.e. removed from schedule) in this case
*/
- if (node_inserted)
+ if (node_inserted != NO_NODE_ADDED)
next = sched_next(n);
}
ir_node *succ = get_edge_src_irn(edge);
blk_state *succ_state;
- if(succ == start_block)
+ if (succ == start_block)
continue;
succ_state = x87_get_bl_state(sim, succ);
} else {
/* There is already a begin state for the successor, bad.
Do the necessary permutations.
- Note that critical edges are removed, so this is always possible. */
+ Note that critical edges are removed, so this is always possible:
+ If the successor has more than one possible input, then it must
+ be the only one.
+ */
x87_shuffle(sim, block, state, succ, succ_state->begin);
}
}
sim->n_idx = get_irg_last_idx(irg);
sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
-
DB((dbg, LEVEL_1, "--------------------------------\n"
"x87 Simulator started for %+F\n", irg));
ASSOC_BE(Reload);
ASSOC_BE(Return);
ASSOC_BE(Perm);
+ ASSOC_BE(Keep);
ASSOC(Phi);
#undef ASSOC_BE
#undef ASSOC_IA32
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
} /* x87_destroy_simulator */
-static void update_liveness_walker(ir_node *block, void *data)
-{
+/**
+ * Pre-block walker: calculate the liveness information for the block
+ * and store it into the sim->live cache.
+ */
+static void update_liveness_walker(ir_node *block, void *data) {
x87_simulator *sim = data;
update_liveness(sim, block);
-}
+} /* update_liveness_walker */
/**
* Run a simulation and fix all virtual instructions for a graph.
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
- ir_graph *irg = birg->irg;
+ ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
x87_init_simulator(&sim, irg, arch_env);
sim.worklist = new_waitq();
waitq_put(sim.worklist, start_block);
- be_invalidate_liveness(birg);
be_assure_liveness(birg);
- sim.lv = birg->lv;
+ sim.lv = be_get_birg_liveness(birg);
+// sim.lv = be_liveness(be_get_birg_irg(birg));
+ be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
* because the simulator adds new nodes (possible before Phi nodes) which
do {
block = waitq_get(sim.worklist);
x87_simulate_block(&sim, block);
- } while (! pdeq_empty(sim.worklist));
+ } while (! waitq_empty(sim.worklist));
/* kill it */
del_waitq(sim.worklist);
x87_destroy_simulator(&sim);
} /* x87_simulate_graph */
+
+void ia32_init_x87(void) {
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
+} /* ia32_init_x87 */
projects / libfirm / blobdiff